CN105938827B - 半导体装置及用于制造半导体装置的方法 - Google Patents

半导体装置及用于制造半导体装置的方法 Download PDF

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CN105938827B
CN105938827B CN201610120953.0A CN201610120953A CN105938827B CN 105938827 B CN105938827 B CN 105938827B CN 201610120953 A CN201610120953 A CN 201610120953A CN 105938827 B CN105938827 B CN 105938827B
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layer
intermetallic compound
semiconductor device
copper
solder layer
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CN105938827A (zh
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萧友享
李秋雯
杨秉丰
林光隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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    • B23K35/302—Cu as the principal constituent
    • C—CHEMISTRY; METALLURGY
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Abstract

本发明涉及一种半导体装置及一种用于制造所述半导体装置的方法。所述半导体装置包含半导体裸片、半导体元件及焊料层。所述半导体裸片包含铜柱。所述半导体元件包含表面处理层，其中所述表面处理层的材料为镍、金及钯中的至少两者的组合。所述焊料层位于所述铜柱与所述表面处理层之间。所述焊料层包含第一金属间化合物IMC及第二金属间化合物，其中所述第一金属间化合物包含铜、镍及锡中的至少两者的组合。所述第二金属间化合物为金与锡的组合、钯与锡的组合或两者。

Description

半导体装置及用于制造半导体装置的方法
技术领域
本发明涉及半导体结构及半导体过程的领域，且更特定来说，涉及半导体倒装芯片结合装置及用于制造所述半导体倒装芯片结合装置的半导体过程。
背景技术
在常规半导体倒装芯片结合方法中，镍(Ni)材料的势垒层涂布到上部裸片的铜柱，且焊料形成于镍势垒层上。接着，上部裸片置放于底部裸片或衬底上，使得铜柱上的焊料接触底部裸片或衬底的焊垫。在回焊过程之后，焊料经熔融而连接到焊垫以便形成半导体倒装芯片结合装置。
在回焊过程期间，焊料可与底部裸片或衬底的焊垫反应以便形成金属间化合物(Intermetallic Compound,IMC)。通常，焊料的材料为锡银合金(例如，SnAg)，焊垫的材料为铜(Cu)，且金属间化合物的材料因此为锡、银及铜的组合，例如铜锡合金(Cu6Sn5或Cu3Sn4)或镍锡合金(Ni6Sn5或Ni3Sn4)。金属间化合物可使焊料与焊垫之间的结合更紧密。然而，如果焊垫较薄，则整个焊垫可能会与焊料反应而使得焊垫破裂。另外，由于金属间化合物为脆性的，因此较厚的金属间化合物层将减小半导体倒装芯片结合装置的剪切强度(Shear Strength)。此外，如果焊料极薄(例如，小于30μm)，则金属间化合物与焊料的体积比可大于80％，此可导致接合破裂(Joint Crack)。
因此，需要新的半导体装置及用于控制金属间化合物的量的半导体过程。
发明内容
本发明的一个方面涉及半导体装置及用于制造所述半导体装置的方法。所述半导体装置包含半导体裸片、半导体元件及焊料层。半导体裸片包含铜柱。半导体元件包含表面处理层，其中表面处理层的材料为镍、金及钯中的至少两者的组合。焊料层位于铜柱与表面处理层之间。焊料层包含第一金属间化合物(IMC)及第二金属间化合物。第一金属间化合物包含铜、镍及锡的组合。第二金属间化合物包含金与锡的组合、钯与锡的组合或两者。
本发明的另一个方面涉及半导体装置。在实施例中，所述半导体装置包括半导体裸片、半导体元件及焊料层。半导体裸片包含铜柱、势垒层及金属层。势垒层位于铜柱的末端上，且金属层位于势垒层上。半导体元件包含电性接点及位于所述电性接点上的表面处理层。表面处理层的材料为镍、金及钯中的两者或两者以上的组合。焊料层位于半导体裸片的金属层与半导体元件的表面处理层之间。焊料层包含第一金属间化合物及第二金属间化合物。第一金属间化合物包含铜、镍及锡中的两者或两者以上的组合。第二金属间化合物包含金与锡的组合、钯与锡的组合或两者。
本发明的另一个方面涉及用于制造半导体装置的方法。在实施例中，所述方法包括：(a)提供包括铜柱的半导体裸片；(b)邻近于铜柱的末端形成焊料层；(c)将所述半导体裸片置放于半导体元件上，使得焊料层接触所述半导体元件的电性接点上的表面处理层，其中表面处理层的材料为镍、金及钯中的两者或两者以上的组合；及(d)进行回焊过程以在焊料层中形成第一金属间化合物及第二金属间化合物，其中第一金属间化合物包括铜、镍及锡的组合，且第二金属间化合物包含金与锡的组合、钯与锡的组合或两者。
附图说明
图1说明根据本发明的实施例的半导体封装的横截面图。
图2说明图1的半导体封装中的半导体裸片与半导体元件之间的半导体倒装芯片结合的区域的放大图。
图3说明根据本发明的另一实施例的半导体倒装芯片结合的横截面图。
图4说明根据本发明的另一实施例的半导体倒装芯片结合的横截面图。
图5、图6及图7说明根据本发明的实施例的用于制造半导体装置的方法。
图8说明根据本发明的另一实施例的用于制造半导体装置的方法。
具体实施方式
参看图1，说明根据本发明的实施例的半导体封装的横截面图。半导体封装1包括衬底10、多个外部焊球36、半导体裸片42、半导体元件38、第一底胶(Underfill)40、多个焊料层44、第二底胶46及封装材料(Molding Compound)48。
衬底10可为(例如)硅衬底、晶片或玻璃衬底。衬底10包含上部表面101、下部表面102、上部电路层20、下部电路层30、上部保护层32及下部保护层34。上部电路层20位于衬底10的上部表面101上，且下部电路层30位于衬底10的下部表面102上。上部保护层32覆盖衬底10的上部电路层20及上部表面101，且界定多个开口321以曝露上部电路层20的一部分。下部保护层34覆盖衬底10的下部电路层30及下部表面102，且界定多个开口341以曝露下部电路层30的一部分。在实施例中，上部电路层20及下部电路层30的材料为铜，且上部保护层32及下部保护层34为焊料掩模(Solder Mask)，且其材料为(例如)聚酰亚胺(PI)。外部焊球36位于曝露的下部电路层30上以用于外部连接。
半导体元件38可为(例如)硅衬底、晶片或玻璃衬底。在实施例中，半导体元件为中介层(Interposer)。半导体元件包含上部表面381、下部表面382、上部电路层383、下部电路层384、多个导电通道(Conductive Via)385、下部保护层387及多个焊球388。上部电路层383及下部电路层384分别位于半导体元件38的上部表面381及下部表面382上。导电通道385贯穿半导体元件38，且接触且电连接上部电路层383及下部电路层384。下部保护层387覆盖半导体元件38的下部电路层384及下部表面382，且界定多个开口以曝露下部电路层384的一部分。焊球388接触且电连接半导体元件38的下部电路层384的曝露部分及衬底10的上部电路层20的曝露部分。第一底胶40位于半导体元件38与衬底10之间以用于保护焊球388。在实施例中，下部保护层387为焊料掩模，且其材料为(例如)聚酰亚胺(PI)。
半导体裸片42借助于半导体裸片42上的多个铜柱424附接于半导体元件38。每一焊料层44位于所述铜柱424的一者与上部电路层383的曝露部分之间，以便将铜柱424结合到上部电路层383。第二底胶46位于半导体裸片42与半导体元件38之间以用于保护铜柱424及焊料层44。在一些实施例中，除了铜之外，铜柱424包括不同金属、金属合金或其它导电材料，且所形成的金属间化合物的组成将因此不同。
封装材料48位于衬底10的上部表面101上以包覆半导体元件38、第一底胶40、半导体裸片42及第二底胶46。在一些实施例中，可省去第一底胶40及第二底胶46中的一者或两者。
在图1的实施例中，半导体倒装芯片结合装置包括具有铜柱424的半导体裸片42、半导体元件38及焊料层44。
参看图2，说明图1的半导体倒装芯片结合装置的区域A的放大图。如图2中的区域A的放大图所说明，半导体裸片42包含主动面421、金属电路层422、晶种层423、铜柱424及保护层425。金属电路层422位于主动面421上。在一些实施例中，金属电路层422包含彼此绝缘的多个区段，且所述区段的材料为(例如)铝(Al)、铜(Cu)或铝铜合金(例如，AlCu)。保护层425覆盖主动面421及金属电路层422，且界定多个开口4251以曝露金属电路层422的部分。在实施例中，保护层425为包括金属氧化物的钝化层。铜柱424邻设于金属电路层422，且电连接到金属电路层422。在图1及图2中所说明的实施例中，晶种层423位于开口4251中的金属电路层422上，且铜柱424位于晶种层423上。即，晶种层423的一部分位于每一铜柱424与金属电路层422之间。然而，可省去晶种层423，且铜柱424可直接位于金属电路层422上。在实施例中，晶种层423的材料为钛合金(例如，TiCu)。
半导体元件38包含用于电连接到半导体裸片42的电性接点。在所说明的实施例中，上部电路层383的一部分形成焊垫3831，焊垫3831为上文所提及的电性接点。在此实施例中，半导体元件38包含位于焊垫3831上的表面处理层(Surface Finish Layer)39，其中表面处理层39形成于例如镍(Ni)、钯(Pd)及金(Au)或其合金(例如，Ni/Au、Ni/Pd或Ni/Pd/Au)的层的一或多个层中，且焊垫3831的材料为铜(Cu)。举例来说，表面处理层39的镍层充当势垒层，其可阻挡自焊垫3831到焊料层44的一些铜扩散，以避免因消耗整个焊垫3831而导致的上部电路层383破裂。另外，位于镍层上的表面处理层39的金(Au)、钯(Pd)或钯金(Pd/Au)层可用于增加焊料层44的可湿润性(Wettability)，以避免因镍层的较差可湿性而导致焊料结合不充分。
焊料层44位于铜柱424与表面处理层39之间，且当经制造时，包括主焊料部分45、第一金属间化合物47及第二金属间化合物49。在此实施例中，焊料层44直接接触铜柱424。主焊料部分45的材料为锡(Sn)或锡银合金(SnAg)。第一金属间化合物47及第二金属间化合物49为在主焊料部分45与铜柱424之间及在主焊料部分45与具有处理层39的焊垫3831之间的金属相互作用的产物。第一金属间化合物47为铜(Cu)、镍(Ni)及锡(Sn)的组合，且第二金属间化合物49为金(Au)及锡(Sn)的组合(例如，AuSn4)，钯(Pd)及锡(Sn)的组合(例如，PdSn4)或金(Au)及锡(Sn)的组合及钯(Pd)及锡(Sn)的组合两者。在实施例中，第一金属间化合物47包含(Cu,Ni,Au,Pd)6Sn5(即，Cu6Sn5、Ni6Sn5、Au6Sn5或Pd6Sn5中的一或多者)及其它金属间化合物，且第二金属间化合物49包含(Au,Pd,Ni)Sn4(即，AuSn4、PdSn4或NiSn4中的一或多者)及其它IMC。
第一金属间化合物47包含由与主焊料部分45进行金属反应(Metal Reaction)所形成的顶部层50及底部层52。在实施例中，顶部层50及底部层52为同一材料。由主焊料部分45与铜柱424的相互作用在铜柱424的末端处形成顶部层50，且由焊料层44与表面处理层39的相互作用邻近于电性接点(即，焊垫3831)形成底部层52。在一些实施例中，势垒层可位于(例如，涂布于)铜柱424及表面处理层39中的一者或两者上；然而，在图2中所说明的实施例中，可省去此势垒层。
第二金属间化合物49也由金属反应形成，且在主焊料部分45中不连续地形成，如图2中的说明所示。
如所描述，在图2的实施例中，例如Ni层的势垒层并不位于铜柱424的末端上。因此，在回焊过程期间，铜柱424中的铜(Cu)及表面处理层39中的镍(Ni)将快速进入焊料层44，以形成第一金属间化合物47的顶部层50及底部层52。具体来说，来自铜柱424的一些铜穿过焊料层44且与表面处理层39中的镍相互作用(反应)以形成底部层52，且来自表面处理层39的一些镍穿过焊料层44且与铜柱424中的铜相互作用以形成顶部层50。在实施例中，金属相互作用导致第一金属间化合物47的顶部层50及底部层52包含同一材料。举例来说，顶部层50及底部层52可都包含相同的一或多种化合物，所述化合物可为(Cu,Ni,Au,Pd)6Sn5中的一或多者。以类似方式，来自铜柱424及表面处理层39的金属穿过焊料层44以形成非连续第二金属间化合物49。
第一金属间化合物47及第二金属间化合物49的组合的体积相对于焊料层44的体积的体积比被控制为小于80％，借此避免接合破裂且增加半导体倒装芯片结合装置的机械可靠性(Mechanical Reliability)。在一些实施例中，第一金属间化合物47相对于焊料层44的体积比大于第二金属间化合物49相对于焊料层44的体积比。然而，在其它实施例中，归因于过程公差(Process Tolerance)，表面处理层39的一或多层(例如，金(Au)、钯(Pd)或钯金(Pd/Au)层中的一或多者)的厚度可使得第一金属间化合物47相对于焊料层44的体积比小于第二金属间化合物49相对于焊料层44的体积比。
可在加工期间通过控制铜柱424、表面处理层39及焊料层44的厚度来控制第一金属间化合物47的厚度。此上下文中的“厚度”指图2中所展示的定向中的垂直尺寸。因此，给定图2中的厚度T1、T2及T3(分别为铜柱424、焊料层44及表面处理层39的厚度)，第一金属间化合物47的顶部层50将形成为T5的厚度，且第一金属间化合物47的底部层52将形成为T6的厚度。举例来说，铜柱424的厚度T1为约5微米(μm)到约20μm；焊料层44的厚度T2为约5μm到约30μm；且表面处理层39的厚度T3为约1μm到约15μm；使得顶部层50的所得厚度T5为约2μm到约3μm，且底部层52的所得厚度T6不大于或小于T5，且为约1μm到约2μm。
因此，第一金属间化合物47的顶部层50及底部层52的组合的厚度为约3μm到约5μm，且可因此控制第一金属间化合物47，使得其不完全替换焊料层44。此外，通过控制T1、T2及T3的厚度，可控制第二金属间化合物49的厚度，且所述厚度可经控制以使得第一金属间化合物47及第二金属间化合物49的组合的厚度小于焊料层44的厚度(即，不完全替换焊料层44)。在一个实施例中，焊垫3831的厚度T4为约1μm到约10μm；然而，通过利用表面处理层39阻挡焊垫3831中的铜的迁移，在此实施例中，焊垫3831的厚度并不显著影响第一金属间化合物47或第二金属间化合物49的厚度。
控制金属间结合(Metallic Bonding)以形成第一金属间化合物47及第二金属间化合物49的额外益处为避免焊料层44中的空隙；因此，半导体倒装芯片结合装置的寿命增加。
参看图3，说明根据本发明的另一实施例的半导体倒装芯片结合装置的横截面图。此实施例的半导体倒装芯片结合装置类似于图2的半导体倒装芯片结合装置，且差异为铜柱424具有位于铜柱424的侧壁上以包围铜柱424的外围保护层54。外围保护层54的材料为例如氧化铜的金属氧化物，其被如下形成：首先，将掩模层用于覆盖铜柱424的末端的底部表面。接着，将具有掩模层的铜柱424置放到氧化气体中，使得外围保护层54形成于铜柱424的侧壁上。在移除掩模层之后，将焊料层44形成于铜柱424的末端处。
参看图4，说明根据本发明的另一实施例的半导体倒装芯片结合装置的横截面图。此实施例的半导体倒装芯片结合装置类似于图2的半导体倒装芯片结合装置，且差异为半导体裸片42进一步包含势垒层426及金属层427。势垒层426位于铜柱424的末端上，且金属层427位于(例如，涂布于)势垒层426上。在实施例中，势垒层426的材料为镍(Ni)，且金属层427的材料与铜柱424的材料相同，即，都为铜(Cu)。因此，第一金属间化合物47的顶部层50直接形成于金属层427上。在实施例中，第一金属间化合物47的顶部层50及底部层52的材料为(Cu,Ni,Au,Pd)6Sn5中的一或多者，且顶部层50及底部层52可为同一合金。另外，此实施例的铜柱424可包含类似于图3中所说明的外围保护层54的外围保护层。在实施例中，为了控制第一金属间化合物47及第二金属间化合物49的厚度，势垒层426的厚度T7为约1μm到约5μm，且金属层427的厚度T8为约2μm到约8μm。
参看图5、图6及图7，说明根据本发明的实施例的用于制造半导体装置的方法。此实施例用于制造半导体倒装芯片结合装置，例如图2中所展示的半导体倒装芯片结合装置。
参看图5，提供半导体裸片42。在此实施例中，半导体裸片42包含主动面421、金属电路层422、晶种层423、铜柱424及保护层425。金属电路层422位于主动面421上。在此实施例中，金属电路层422包含彼此绝缘的多个区段，且所述区段的材料为铝(Al)、铜(Cu)或铝铜(AlCu)。保护层425覆盖主动面421及金属电路层422，且界定多个开口4251以曝露金属电路层422的一部分。在实施例中，保护层425为金属氧化物的钝化层。铜柱424邻设于金属电路层422，且电连接到金属电路层422。在此实施例中，晶种层423位于每一开口4251中的金属电路层422上，且每一铜柱424位于晶种层423上。即，晶种层423位于每一铜柱424与金属电路层422之间。然而，可省去晶种层423，且每一铜柱424可直接位于金属电路层422上。在实施例中，晶种层423的材料为钛铜(TiCu)。
参看图6，邻近于铜柱424的末端形成焊料层44。在此实施例中，焊料层44形成于铜柱424的末端处。即，不存在位于铜柱424的末端上的势垒层(例如，镍层)，使得焊料层44直接接触铜柱424的末端。焊料层44的材料为锡(Sn)或锡银(SnAg)。焊料层44的外围表面与铜柱424的外围表面共面，因此，焊料层44的半径与铜柱424的半径实质上相同。
接着，提供半导体元件38。在实施例中，半导体元件38为中介层，且包含用于电连接到半导体裸片42的一或多个电性接点。半导体元件38的上部电路层383的一部分形成焊垫3831。在此实施例中，半导体元件38进一步包含位于焊垫3831上的表面处理层39。在实施例中，表面处理层39的材料为Ni/Au、Ni/Pd或Ni/Pd/Au的组合，且焊垫3831的材料为铜。
在图6中所说明的实施例中，铜柱424的厚度T1为约5μm到约20μm，焊料层44的厚度T2为约5μm到约30μm，表面处理层39的厚度T3为约1μm到约15μm，且焊垫3831的厚度T4为约1μm到约10μm。
参看图7，半导体裸片42置放于半导体元件38上，使得铜柱424上的焊料层44接触半导体元件38的电性接点(例如，焊垫3831)上的表面处理层39。接着，执行回焊以将铜柱424与焊料层44结合且将焊料层44与表面处理层39结合。此回焊过程在焊料层44中形成第一金属间化合物47及第二金属间化合物49，在所述金属间化合物47、49之间留下主焊料部分45。在实施例中，主焊料部分45的材料为锡(Sn)或锡银(SnAg)，第一金属间化合物47由铜(Cu)、镍(Ni)及锡(Sn)的组合制成且包含Cu6Sn5，且第二金属间化合物49为基于AuSn4的(AuSn4Based)、基于PdSn4的(PdSn4Based)或其组合。
在图5到图7描述的实施例中，例如Ni层的势垒层不涂布于铜柱424的末端上；因此，在回焊过程期间，铜柱424中的铜及表面处理层39中的镍将快速进入焊料层44，以便形成第一金属间化合物47的顶部层50及底部层52。在实施例中，顶部层50及底部层52中的每一者的材料包含(Cu,Ni,Au,Pd)6Sn5中的一或多者，且顶部层50及底部层52可为同一材料。根据Gibb能量方程式，如果形成能量不同，则将首先形成具有较低的形成能量及较高稳定性的金属间化合物。因为(Cu,Ni,Au,Pd)6Sn5的形成能量低于(Au,Pd,Ni)Sn4的形成能量，且因为(Cu,Ni,Au,Pd)6Sn5比(Au,Pd,Ni)Sn4更稳定，所以将首先形成第一金属间化合物47的顶部层50及底部层52(都呈(Cu,Ni,Au,Pd)6Sn5形式)。
在一些实施例中，第一金属间化合物47(包含顶部层50及底部层52)的Cu6Sn5相对于焊料层44的最大体积比为约15％。此外，如果焊料层44中的铜的浓度大于1重量百分比(1wt％)，则将抑制AuSn4及/或PdSn4的形成。在例如关于图5到图7描述的实施例中，在势垒层不涂布于铜柱424的末端上的情况下，来自铜柱424的Cu可抑制第二金属间化合物49的形成。举例来说，在回焊过程期间，铜柱424中的铜自由进入焊料层44，焊料层44中的铜首先形成Cu6Sn5，且因此，焊料层44中剩余的相对大量(例如，大于1wt％)的铜抑制AuSn4及/或PdSn4的形成。因此，在一些实施例中，第一金属间化合物47相对于焊料层44的体积比将大于第二金属间化合物49相对于焊料层44的体积比。然而，在其它实施例中，归因于过程公差，表面处理层39的金(Au)、钯(Pd)或钯金(Pd/Au)层的厚度可使得其抵消焊料层44中剩余的铜的作用，且因此AuSn4及/或PdSn4的形成得不到抑制。在此情况下，第一金属间化合物47相对于焊料层44的体积比可小于第二金属间化合物49相对于焊料层44的体积比。然而，第一金属间化合物47与第二金属间化合物49的组合相对于焊料层44的体积比可被控制为小于80％，以避免接合破裂且增加半导体倒装芯片结合装置的机械可靠性。
参看图8，说明根据本发明的另一实施例的用于制造半导体装置的方法。此实施例用于制造半导体倒装芯片结合装置，例如图4中所展示的半导体倒装芯片结合装置。此实施例的方法类似于图5到图7的方法，且差异为半导体裸片42进一步包含势垒层426及金属层427。在实施例中，势垒层426的材料为Ni，且势垒层426位于铜柱424的末端上。金属层427的材料与铜柱424的材料相同，即，都为铜。金属层427位于势垒层426上。势垒层426的厚度T7为约1μm到约5μm，且金属层427的厚度T8为约2μm到约8μm。焊料层44位于金属层427上。在此实施例中，焊料层44的外围表面与铜柱424及金属层427的外围表面共面，因此，焊料层44的半径与铜柱424及金属层427的半径实质上相同。
在此实施例中，金属层427的厚度T8与焊料层44的厚度T2之间的关系式为约T8≥0.09T2，其被如下导出。在此实施例中，势垒层426涂布于铜柱424的末端上，因此，在回焊过程期间，铜柱424中的铜将不进入焊料层44。即，焊料层44中的铜仅或主要来自铜金属层427。
铜金属层427的厚度T8可视为第一部分与第二部分的组合。铜金属层427的第一部分的厚度用于控制Cu6Sn5的形成，且铜金属层427的第二部分的厚度用于抑制AuSn4及/或PdSn4的形成。为方便起见，铜金属层427的第一部分的厚度在本文中被称作T81，且铜金属层427的第二部分的厚度在本文中被称作T82。
T81是由以下方式所决定。如上文所陈述，在一些实施例中，Cu6Sn5相对于焊料层44的最大体积比为约15％。因此，V1＝(0.15)V2，其中V1表示Cu6Sn5的体积，且V2表示焊料层44的体积。因为Cu6Sn5中的铜(Cu)的体积比为所以铜(Cu)的体积为在几何关系中，铜(Cu)的体积为πr2×T81，且焊料层44的体积为V2＝πr2×T2，其中r表示焊料层44的半径(其与铜金属层427的半径相同)。如在方程式(1)中，使铜(Cu)的体积的两个描述相等，且通过求解方程式(1)，如在方程式(2)中决定厚度T81。
铜金属层427的第二部分的厚度T82是由以下方式所决定。如上文所陈述，在一些实施例中，如果焊料层44中的铜(Cu)的浓度大于1wt％，则将抑制AuSn4及/或PdSn4的形成。因此，在一些实施例中，当(即，当99W1≥W2时)时，抑制发生，其中W1表示铜(Cu)的重量，且W2表示SnAg的重量。铜(Cu)的重量为W1＝πr2×T82×8.96，且焊料层44的重量为W2＝πr2×T2×7.31，其中r表示焊料层44的半径(其与铜金属层427的半径相同)，8.96为铜(Cu)的密度，且7.31为SnAg的密度。方程式(3)始于关系式99W1≥W2，且在所述关系式中代入W1及W2，且在方程式(4)中求解厚度T82。
99(πr2×T82×8.96)≥(πr2×T2×7.31) (3)
T82≥0.00824T2 (4)
厚度T8为厚度T81及T82的总和，因此，根据方程式(2)及(4)，T8＝T81+T82≥0.0818T2+0.00824T2≥0.09004T2。即，铜金属层427的厚度T8与焊料层44的厚度T2之间的关系式为约T8≥0.09T2。
仍参看图8，半导体裸片42置放于半导体元件38上，使得焊料层44接触半导体元件38的电性接点(例如，焊垫3831)上的表面处理层39。接着，执行回焊以在焊料层44中形成第一金属间化合物47及第二金属间化合物49连同剩余主焊料部分45，以获得如图4中所展示的半导体倒装芯片结合装置。在此实施例中，铜金属层427的厚度T8与焊料层44的厚度T2之间的关系式满足上文所提及的方程式T8≥0.09T2，因此，第一金属间化合物47及第二金属间化合物49相对于焊料层44的体积比小于80％，借此避免接合破裂且增加半导体倒装芯片结合装置的机械可靠性。
如本文中所使用，术语“实质上”及“约”用于描述及解释较小变化。当与事件或情形相结合使用时，所述术语可指事件或情形精确发生的情况，及事件或情形极近似地发生的情况。举例来说，所述术语可指小于或等于±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。因此，将一个半径描述为与另一半径“实质上相同”指示：一个半径小于或等于另一半径的±10％，例如小于或等于±5％，小于或等于±4％，小于或等于±3％，小于或等于±2％，小于或等于±1％，小于或等于±0.5％，小于或等于±0.1％或小于或等于±0.05％。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是为便利及简洁起见而使用，且应灵活地理解为不仅包含明确指定为范围的极限的数值，且也包含涵盖于那个范围内的所有个别数值或子范围，就如同明确指定每一数值及子范围一般。
虽然已参考本发明的特定实施例描述并说明本发明，但这些描述及说明并不限制本发明。所属领域的一般技术人员应理解，在不脱离如由所附权利要求书界定的本发明的真实精神及范围的情况下，可作出各种改变且可取代等效物。说明可能未必按比例绘制。归因于制造过程及公差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未具体说明的本发明的其它实施例。应将本说明书及图式视为说明性而非限制性的。可作出修改，以使特定情形、材料、物质组成、方法或程序适应于本发明的目标、精神及范围。所有这些修改意欲在随附的权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本文中所揭示的方法，但应理解，在不脱离本发明的教示的情况下，可组合、再分，或重新定序这些操作以形成等效方法。相应地，除非本文中具体指示，否则操作的次序及分组并非本发明的限制。

Claims (12)

1.一种半导体装置，其包括：
半导体裸片，其包括铜柱；
半导体元件，其包括电性接点及位于所述电性接点上的表面处理层，其中所述表面处理层的材料为镍、金及钯中的至少两者的组合；以及
焊料层，其位于所述铜柱与所述表面处理层之间，所述焊料层包括主焊料部分、第一金属间化合物及第二金属间化合物，其中所述第一金属间化合物包括顶部层及底部层，所述顶部层接触所述铜柱，所述底部层接触所述表面处理层，所述第二金属间化合物不连续地形成在所述主焊料部分中，所述第一金属间化合物包括铜、镍及锡中的两者或两者以上的组合，且所述第二金属间化合物包含金与锡的组合、钯与锡的组合或金与锡的组合及钯与锡的组合两者。
2.根据权利要求1所述的半导体装置，其中所述第一金属间化合物的所述顶部层及所述底部层的材料相同。
3.根据权利要求1所述的半导体装置，其中所述半导体元件为裸片或中介层，且所述电性接点为铜焊垫。
4.根据权利要求1所述的半导体装置，其中所述第一金属间化合物与所述第二金属间化合物的组合相对于所述焊料层的体积比小于80％。
5.根据权利要求1所述的半导体装置，其中所述第一金属间化合物包含Cu6Sn5，且所述第一金属间化合物的所述Cu6Sn5相对于所述焊料层的体积比为约15％。
6.根据权利要求1所述的半导体装置，其中所述焊料层的厚度为约5μm到约30μm。
7.根据权利要求1所述的半导体装置，其中所述第一金属间化合物相对于所述焊料层的体积比大于所述第二金属间化合物相对于所述焊料层的体积比。
8.一种半导体装置，其包括：
半导体裸片，其包括电路层、暴露部分所述电路层的保护层及位于所述电路层经暴露的部分上的晶种层；
铜柱，其位于所述晶种层上；
半导体元件，其包括焊垫及位于所述焊垫上的表面处理层；及
焊料层，其位于所述铜柱与所述表面处理层之间，所述焊料层包括主焊料部分、第一金属间化合物及第二金属间化合物，其中所述第一金属间化合物包括顶部层及底部层，所述顶部层接触所述铜柱，所述底部层接触所述表面处理层，所述第二金属间化合物不连续地形成在所述主焊料部分中，且所述第一金属间化合物的体积与所述第二金属间化合物的体积之和小于所述焊料层的体积的80％。
9.根据权利要求8所述的半导体装置，其中所述第一金属间化合物包括铜、镍及锡中的两者或两者以上的组合，且所述第二金属间化合物包含金与锡的组合、钯与锡的组合或金与锡的组合及钯与锡的组合两者。
10.根据权利要求8所述的半导体装置，其进一步包含衬底，其中所述半导体裸片通过所述半导体元件电连接至所述衬底。
11.根据权利要求10所述的半导体装置，其进一步包含封装材料，所述封装材料包覆所述半导体裸片、所述半导体元件及所述衬底的一部分表面。
12.根据权利要求8所述的半导体装置，其中所述第一金属间化合物相对于所述焊料层的体积比大于所述第二金属间化合物相对于所述焊料层的体积比。
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