TW545098B - Fine pad pitch organic circuit board with plating solder and method for fabricating the same - Google Patents

Abstract

A fine pad pitch organic circuit board with plating solder and a method for fabricating the circuit board with plating solder are provided. The circuit board is formed with a plurality of densely arranged contact pads on at least a surface thereof in the absence of solder mask being applied over the surface. After deposition of a conductive seed layer on the contact pads, a resist layer is applied over the surface of the circuit board, and formed with a plurality of openings for exposing the seed layer corresponding in position to the contact pads. Then, a solder material is deposited in the openings by a plating method. Finally, the resist layer and the seed layer underneath the resist layer are removed, making the circuit board readily subject to subsequent fabrication processes for forming flip-chip joints or board-to-board joints.

Description

545098 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a circuit board with solder plating and its manufacturing method for electronic packages; specifically, it relates to a circuit board with solder plating A micro-pad pitch organic circuit board, the plated solder is used to form a flip-chip solder joint and a board-to-board solder joint, and a method for manufacturing the micro-pad pitch organic circuit board with plated solder. [Previous technology] Since the introduction of flip chip package technology by IBM in early 960, due to the small thermal expansion coefficient difference between silicon wafers and ceramic substrates, flip chip components are mainly set at price Expensive pottery actually on the substrate. Compared with wire bonding (wier e b o n d) technology, flip chip technology is characterized in that the electrical connection between the chip and the substrate is through solder bumps instead of wire bonding. The advantage of this flip-chip technology is that it can increase the packaging density to reduce the outline of the components. At the same time, this flip-chip technology does not need to use a longer = ^ line, so it can improve the electrical performance. In view of this, the industry has been using control-collapse chip connection (C4) for ceramic substrates with high-temperature solder, the so-called control-collapse chip connection technology (C4). However, in recent years, due to the need for high density , High-speed and low-cost semiconductor components, and chip-on-chip devices on low-cost organic circuit boards (for example, printed circuits) in response to the gradual shrinking of electronic products

Board or substrate), filled with epoxy resin (underf 丨 u resin), under the chip to reduce the thermal expansion between the silicon wafer and the structure of the organic circuit board due to thermal stress: growing up. The use of low-temperature flip-chip solder joints and organic circuit boards in the industry can be reduced

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545098 V. Description of the invention (2) Manufacturing cost of flip chip device. In the current low-cost flip-chip technology, the semiconductor body is provided with electrical electrodes Xue Yiyi ... s). This plate of Γ =: has a corresponding contact welding pad. Materials are attached to the wafer and the circuit. , =] Low temperature solder bumps or other conductive adhesive plates are installed, and the " sheet is placed on the circuit circuit with the contact surface facing downward; fe s Μ, the solder bumps or conductive adhesive The material provides the wafer with bump output (1/0) and mechanical connections. As far as soldering = block soldering (S0lder bump j0int), you can enter _ + 2 = fill in the organic substrate in the gap between the circuit boards, in order to suppress ^ 2: 1 metal bump as shown in the figure ☆ Electricity of wafer 13: JHT picture and contact pads 15 of several pre-solder bump organic circuit boards 16 made of low temperature solder. 1 is formed under the condition of the freshness temperature of the melt, by preliminarily. =: = Ghost 14 f metal bump u can form a fresh tin connection 17. Then, the interstitial material 18 filled between the wafer 13 and the circuit board 16 is tinned 17 and covered, thereby completing the flip chip. Section ^ This solder illustrates another flip-chip component 1, 2B without pre-solder bumps. Several solder bumps 19 are formed in the heart of the wafer 13, and the wafer 13 is re-soldered to Circuit board 16; wherein the 12 is on. The contact pads 15 connected to the circuit board 16 form solder joints. Old ^ 19 welding ^ after ‘to the bottom

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545098 V. Description of the invention (3) ^ '-----The adhesive material 1 8 is filled in the gap between the wafer 丨 3 and the circuit board 丨 6, and the solder joint 17 is wrapped in it, that is, Complete the flip chip 丨,. FIG. 3 illustrates a conventional organic circuit board 100 for a flip-chip package. The circuit board has a contact pad 101 and the pad gap ι09 is greater than 0.18 * m. The insulating layer i 〇2 of the organic circuit board 100 may be made of organic materials, organic materials with mixed fibers, or organic materials with mixed particles, and the like (for example, epoxy resin (polyimide), polyimide (polyimide), cis-butadiene Made from diimide diimide / biseleimide triazine, cyanate ester, polybenzocyclobutene or glass fiber composite materials, etc. to make. The contact pad 1 0 1 is typically formed of a metal material (for example, copper). The general metal barrier layer 103 includes a nickel adhesion layer and a gold protective layer formed on the pad 101. However, the barrier layer can also be made of gold, nickel, palladium, silver, tin, nickel / palladium, chromium / titanium, palladium / gold or nickel / palladium / gold, etc., by electroplating, electroless plating Or physical vapor deposition (physical vapor deposition). An organic soldering mask layer 104 is deposited on the surface of the circuit board 100 to protect the circuit layer 105 and provide insulation characteristics. The top two circuit layers 105 and 106 are generally electrically connected through vias 107 which are well known in the field. Referring to FIG. 3, in a case where the pad gap 1 0 9 is large (for example, greater than 0.18 mm), the circuit wire 108 may be disposed between the two contact pads 101. Pre-soldering bumps 1 10 are formed on the contact pads 101 for forming flip-chip solder joints. Among them, the industry currently mainly deposits tin solder by I stencil printing technology.

545098 V. Description of the invention (4) '1 to form solder bumps.的 For common methods for forming pre-solder bumps on circuit boards (such as stencil printing technology), refer to U.S. Patent No. 5'203'0 7 5 Ungulas et al) and U.S. Patent No. 5 4 9 2, 2 6 6 ( Hoebener et al) and U.S. Patent No. 5, 8 28, 1 2 8 (HlgaShlg Uchl et al. Related prior art disclosed. However, in the interim operation, when the pad gap 109 is reduced to 0. 5 Below millimeters, the stencil printing technology becomes too low to be viable; in addition, the red pad gap of 109 is reduced, and the insulation protection layer 1 〇4 is in contact with the circuit board 001. The contact area 111 It becomes smaller, and the adhesion of the insulating protective layer i 4 to the circuit board 100 itself tends to weaken. The use of electroplating to form solder bumps can overcome this type of pad spacing, limiting the use of two Prior art related to the formation of solder bumps on flip-chip circuit boards by electroplating has been disclosed in U.S. Patent No. 5,391,514 (Gall al) and U.S. Patent No. 5,48,083 (Hobeener). However, the electrical: process still exists that has the potential to make the circuit board Insulation protective layer »Uniformity after plating and the height of the bumps. Edge: The existence of the protective layer " adversely affects the efficiency of the circuit board ^ ^ When the pad spacing is less than ϋ.15 mm; In this case, the insulating protective layer of the shape tl / board Lu, the adhesion of the circuit board becomes ϋν: described in Figure 3/3), under the influence of the environment, due to the metal, it loses its absolute strength. Raw. Moreover, because the other materials constituting the organic circuit board generally have relatively high CTE and low giass transition temperature; therefore, between the micro-pads of the circuit board

545098 V. Description of the invention (5) Insulation can be found at the distances · The sinking of the pads and the board-to-board solder of the above-mentioned micro pads of the circuit board and the board-to-board solder [Content of the Invention] The main distance organic circuit board and the invention There are a plurality of arrays densely covering the soldering between the pads and the board-to-board. The other pitch organic circuit of the present invention is away from the organic circuit board, and the surface does not have a seed layer deposited thereon and exposed to the corresponding seed layer. Deposited on the opening; a seed layer. According to the invention, the pad-pitch organic circuit is away from the organic circuit board, and the surface does not have the connection distance of the circuit set. The solder-destination board is the circuit insulation surface of the circuit. : It must cause a problem of reduced reliability. The micro-soldering method is a kind of method that does not have an insulating protective layer on the gate < U I dry pad pitch organic circuit branch, and a solder bump, which is shaped as a coil. The design of the daily fresh tin connection is to provide a method for manufacturing a micro-pad interlayer with tin-plated tin. The surface of the circuit board is formed with a contact pad, and the surface is taught without an insulating protective layer. Tin to form flip-chip solder. A method for forming a micro-soldering method with a plated solder is provided. The method is to first provide a micro-solder pad board with a surface provided with at least one contact pad covering the pad pitch; conductive; A seed layer is covered on the seed layer, and at least one opening is formed at the position so that the cladding method (P1atingmethod) removes the solder material from the resist layer and the electrical conduction under the resist layer. The purpose is to provide a A method for forming a micro-soldering board with a bell solder. The method is to first provide a micro-soldering pad. The circuit board has a surface provided with at least one contact fresh insulation protective layer covering the pad spacing.

Page 10 545098 5. Description of the invention (6) A resist layer is covered on the surface, and an opening is formed to expose the seed layer + at least one opening is formed at the position of the pad so that On that day, the seed layer was exposed to g = electroless plating, and the "" electroless plating was removed and the resist layer was removed. The material was deposited on the microchip with plated solder of the present invention to form a flip-chip solder joint. Or, an organic circuit board with electrical spacing can be used to connect the crystals to the surface using conventional soldering method. ^ = The circuit board may be effective for the circuit board. The edge protection layer covers the pad spacing. Applying an insulating protective layer to the circuit = f adversely affects; the present invention is not applicable, and can be plated on the area pads arranged in close contact with the contact pads, ... Insufficient reliability is used on the surface with an insulating protective layer. [Embodiments] 'Figures 4 to 13 illustrate in detail the distance between the organic circuit board and the micro pads with plated solder and their manufacturing methods. The preferred embodiment is shown in Figure 4A. Road layer 2 0 2, among which, Xi Chu_ 〇 括 一 一路 路 201 and the second question 1 ^ ”There is an insulation between the circuit layer 2 0 1 and the first lightning 9 9 D 9 The layer 202 is electrically connected to the layer 202. Xi milk $ s 9nc 2 0 makes the brother and the second circuit material 枓 +, θ as μ, 巴, and the edge layer 205 can be made of organic materials, mixed fiber piles, or mixed particles. The fiber is organic or its glass fiber: ::: Made from triazo brand, cyanoacetate, polybenzocyclobutene, etc.). On the first circuit layer W thereon. Visible; ΐ 204 and no other metal wires (traces) are formed at the A need ’gold m, tin, gold / nickel,

] .b974.ptd Page 11 545098 V. Description of the invention (7) ^-Gold made of metals such as nickel / palladium or nickel / palladium / gold and touching the solder pads 204.衮 七 工, ^ ^ ^ ^ ^ On the other hand, as shown in FIG. 4B, the organic circuit board 300 is two red Γ, and only contains the contact pad 3 01, and the contact pad 3 〇1 is the right v hole 3 0 2 above the surface. The contact pads 3 01 can also form 2 2,! Bar, silver, tin, gold / nickel, nickel / feather or nickel / gold are barrier layers. The organic circuit board 300 also includes a first circuit layer @ ^ \ 弟 T circuit layer 304, and there is an insulation between the first and second circuit layers: Γ !, and the first and second sections are made through the vias 30 2. The two circuit layers are electrically connected. Γ ί Ϊ Made of organic materials, organic materials of mixed fibers or mixed particles, such as materials, such as epoxy resins, polyimide, maleic acid t Ξ t ^ dinitrogen trap, cyanate, Made of polybenzocyclobutene or its glass fiber ". Likewise, the surface of the circuit board 300 does not have an insulating protective layer formed thereon. "Generally, when the contact pads 2 0 4 and 3 0 1 are arranged at a high density or there is a microgastric pad pitch, a plating method (for example, electroplating or no electricity, and depositing #tin material) can be used. To the contact pads 2 0 4 and 3 0 1 of the circuit board 2 0, 3 0 0. Before the solder material is deposited on the contact pads 2 0 4 and 3 01, the contact pads may be preceded by the contact pads A conductive seed layer (to be described in detail later) is formed on the 304 and 301 to facilitate the deposition of solder materials. The conductive seed layer can be formed by physical vapor deposition (PVD) or chemical vapor deposition. (CVD), electroless plating or chemical precipitation, such as sputtering (S pu 11 ering), evaporation (arc vapor eposition), ion beam sputtering (ion beam sputtering), Laser Fused Deposition (laser ablati〇n dep〇si ti〇n), Plasma to promote chemistry

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Page 12 545098 V. Description of the invention (8) = phase precipitation ^ (PECVD) or organic metal chemical vapor deposition (MOCVD) and other methods, formed on the surface of the circuit board 2000, 300. 2〇Λν ^ / 2: 4: ιιι :: 02?: 6: ^ ZU4 then directly puts the resistive layer 207 on the conductive seed to make the resistive layer 2G7 at the position corresponding to the contact pad 204. There are at least 208, in order to partially expose the conductive seed crystals hqj and 丄 a fine plating process (preferably electroplating), the solder material is H; exposed to the conductive seed layer 2 0 6 Open the hole 2 0 8; then, if iim'η removes the resist layer 20 7 and the conductive reflow covered by the resist layer, after the product is removed, it is sufficient to make the deposited solder material 2 09 Under the melted part, a process of reflow soldering is performed. A piece of Til tin π material 209 is reflowed to form a solder bump on the contact pad 204. Similarly, referring to FIG. 6A The circuit board 300 shown in the figure is electrically conductive. The contact pads 301 on the circuit board 300 are placed on the conductive seed layer 306, and the resistance layer 3 is placed on the conductive seed layer 306. 0 7 is formed at a position corresponding to the contact pad 301 to at least partially expose the conductive seed layer 3 06. Next, Ershun * 8 'deposits solder material 309 on the opening 3: the cutting process removes the resistance layer 307 and the electrical conductivity after the conductive layer under the resistance layer is shown as follows: The process of re-soldering “makes the deposited solder material”: forming a solder bump 31 on the solder pad 304. +9, ^ plane and in the contact metal layer = seed layer, 3-6 can be made of metal, alloy or stacked layers of gold 2 0 6, 3 0 6r, but 'depending on the experience of the occasion' the conductive seed layer Xijia is composed of copper or palladium particles (especially electroless plating). The

545098 V. Description of the invention (9) The tin material 2 0 9 and 3 9 may be selected from the group consisting of lead, tin, silver, copper, bismuth, antimony, Hehonglu, Cone's town, marriage, tellurium, and gallium The composition of the elements of the group is also an alloy; It should be noted that a conductive line is formed between the contact pads if necessary or feasible. Washing According to the present invention, the solder materials 209, 309 can also be formed by the continuous plating method. For example, in the openings 208 and 308, the tin :: silver thin layer and tin I are sequentially used, and the silver will eventually melt to form a eutectic tin-silver solder bump 2 after the reflow process. 1 〇. : Another embodiment of the present invention +, before depositing the solder material, a metal pad is formed on the solder pad to contact the pad to improve the subsequent material deposited thereon. As shown in FIG. 7A, taking the circuit board 300 as an example, after the pair 1307 is cast, by electroplating or electroless plating, the conductive seed bank 30 = j should be at the position of the contact pad 301 and penetrate Openings 30 8 Exposure / mesh: Several metal pads 311 are formed. Such a metal pad 311 may be made of a single metal layer, and preferably made of copper or a high-temperature solder material (J-layer SnPb, SnAg, or SnCii alloy, etc.). Then, (for example: 9 is deposited on each metal 塾 311; then, reflow through; dry, easy material display 硪 metal pad 311 to form the final solder bump 312, as shown in Figure 8 As shown in the figure, the seed layer 30 can be selectively touched on the pad 301 'instead of the resist layer 3 07 formed on the circuit board 3001, which can be The solder material is deposited on the surface of the solder material, and the electroless ore is directly deposited on the seed layer 3 06. (not shown in the figure) The seed layer 306 is actually used as a catalyst for the electroless ore process; 545098 V. Description of the Invention (ίο) Even in the absence of the catalytic layer (ie, the seed layer) 3 06, the tin-tin material 3 0 9 can be directly deposited on the contact by an electroless plating process. Welding pads 3 0 1 on. Therefore, by using an electroless plating process, the solder materials 209, 309 can also be deposited on the resistive layer 207, 3 in the absence of the seed layer 206, 3 06. The openings of 0 7 are within 2 0 8 and 3 0 8. The seed layer 2 06, 3 6 on the circuit board 2 0, 3 0 0 should have a thinner extent, so as to facilitate the easy removal of the seed layer by means of the last name. Actually, the seed layer is more effective with a thickness of 0. 0. 01 to 0. 0. 1 mm. Regarding I insect carved solution ’, please refer to known metallographic (me t a 1 1 〇 g r a p h y) books (for example,“ Metallographic etching ”, Gunter Petzow

Metal

American Society for Metals, M ^ tais rarK, uhiU (1 9 78)). In addition, the via holes 203 and 30 may be filled by plating, or the via holes may be filled or partially filled with a conductive substance (for example, copper, solder alloy, metal-filled resin or carbon-filled metal, etc.). Provide the characteristics of electrical conduction of the via holes 203, 302. More specifically, when the composition of the conductive material is the same as the composition of the solder materials 209 and 309, the 〇3, ^ "material plating, the same plating step is performed. Then rough Γ Bar: 2: 2 or 3 0 5 can be used for chemical or physical surface / k & QIS / after "packaging process to provide better adhesion characteristics. f. The ί can be coated on the contact pad 301 of the circuit board 3 0 ° with a high-grade tin bump 3 1 0 to be applied to a joint-covered structure. Quasi 偌 古 轱 / n, set daily fresh tin connection (fllP — chiP 401, with the current position of the semiconductor wafer bump 310 carrying # electrode pads 402 f ^ k corresponds to the circuit board 3 0 The solder type of 0 'sets the semiconductor wafer 4 0 1 to the circuit 545098. 5. Description of the invention (11) t H, and then' refreshing process' is performed as shown in Figure 9β to reflow the solder to the electrode. The pad 400 is formed so that a plurality of flip-chip solders for electrically connecting the semiconductor wafer 400 to the circuit board 300 are formed between the semiconductor wafer 400 and the board 300. ^ In another embodiment of the present invention, the solder bump 31 ° f: the circuit board 3 0 0 can be applied to a semiconductor wafer having a metal bump to form a coating. As shown in FIG. 10, the semiconductor wafer 501 has A plurality of electrodes and stems 3 are formed on the active surface of the semiconductor wafer 501. The electrode pad has a plurality of metal bumps 502 for forming flip-chip solder joints. The semiconductor wafer 501 is made of the metal bumps. 502 are arranged on the circuit board 300 in a manner corresponding to the positions of the solder bumps 310 of the circuit board 300 respectively. Then, as shown in FIG. 10B, the solder bump 3 丨 0 is re-soldered to the metal bump 502 to form a flip-chip solder between the semiconductor wafer 5〇 丨 and the circuit board 30.00. Connect 5 04. The metal bump 502 can be made of metal, alloy, or a combination of several metals, such as solder bumps, gold bumps, copper bumps, or copper pillars covered with solder caps. And the metal bumps can be of any shape, such as stud bumps, spherical bumps, pillar bumps, or other shapes of bumps. According to the present invention, the circuit board can also be used to form flip-chip solders at the same time. And board-to-board soldering. In this embodiment, the circuit board 2 0 with solder bumps 2 1 0 will be used for illustration. As shown in FIG. 1 a, a circuit board 6 0 is prepared. 0 (hereinafter referred to as a "second circuit board"), the circuit board may be an organic or ceramic circuit board, and the wafer 6 0 2 is disposed at an appropriate position close to the circuit board; at the second circuit board 6 0 0, put several contact pads 6 0 1

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(12) The description of the invention is also formed on the periphery of the wafer 602, in which a plurality of metal bumps 604, 605 are respectively formed on the contact pads 6 of the second circuit board 600. 〇1 and electrode pad β 〇3 of the wafer 602. Then, the second circuit board 600 is formed with the metal bumps 604 and 605 facing the solder formed on the circuit board 2000 (hereinafter referred to as "π first circuit board"). The method of the bump 2 1 0 is provided on the second circuit board 200. As shown in FIG. 1B, the metal bumps 6 and 4 are re-soldered to the corresponding solder bumps. 21〇, so that a flip chip solder joint 606 is formed between the wafer 602 and the first circuit board 200, and between the second circuit board ^ 0 0 and the first circuit board 2 0 0 The board-to-board solder joints are formed between 6 and 07. 碡 Metal bumps 604, 605 can be composed of metals, alloys, or a combination of several metals, such as solder bumps, gold bumps, copper bumps, or Steel pillars covered with solder caps, etc .; and the metal bumps can be of any shape, such as studs, spherical bumps, columnar bumps, or other shapes of bumps. Α Please refer to Figure 1 2Α, according to In the present invention, a similar process of the circuit board 200 shown in the fourth figure can be used to form a substrate or wafer carrier for manufacturing a flip-chip structure 7 1 0 (as shown in FIG. 12C). Piece of organic circuit board 700. This circuit board 700 is manufactured by a similar method without the use of an insulating protective layer, and is formed on the upper and lower surfaces of the circuit board 704 and 705 respectively. The contact pad 70b 7 0 2. Please refer to FIG. 12B, and a plurality of solder bumps 7 0 3 are formed on the contact pad 7 0 1 by a plating method. Referring to FIG. 2c, The wafer 706 is placed on the circuit board 700 in a flip-chip manner, and the Luo Yue arrangement is such that the electrode pads 7007 formed on the wafer 706 are formed on the circuit board 7 0 0 The solder bump 7 03; then, a gap y 7 0 9 is used to fill the gap between the wafer 7 06 and the circuit board 7 0 > + quot

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545098 V. Description of the invention (14) As shown in Fig. 1 3C, 'the upper surface of the circuit board 8 00 and the lower surface 8 0 4' can be applied with an insulating protective layer 8 2 1 to cover the conductive The line 8 0 1; however, the insulating protective layer 8 2 1 will expose the contact pad 8 05 and the bump area (the area included by the dotted line 8 07 as shown in FIG. 13B). Then, a wafer 8 0 9 having an electrode pad 8 10 is set on the circuit board 8 0, and a gap between the wafer 8 9 and the circuit board 8 0 0 is filled with a primer material 8 1 2. in. Finally, the external terminal 8 (such as a solder ball, a pin, or a metal post, etc.) is connected to the contact pad 8 05 located on the surface § 〇4 of the lower surface of the circuit board 8 to complete the coating.晶 结构 装 8 1 3． On the other hand, as shown in FIG. 3D, a surface coating 8 1 4 (eg, gold, nickel / gold or a solderable organic protective agent (〇sp), etc.) can be formed on each contact welding pad 8 0 5. A surface coating 815 (for example, gold, nickel / gold, or epoxy resin) is formed on the conductive lines t0i and 806 to prevent corrosion. Further, as shown in FIG. 3E, another option is to form a surface coating 8 1 8 on each conductive wire 8 0 1 on the surface 8 0 3 of the circuit board 8 0 (for example, 0 Sp, Epoxy resin, gold, nickel / gold, etc.), and an insulating protective layer 816 is covered on the surface 804 below the circuit board 80 to restore the conductive wire 8 06; however, the insulating protective layer 8 丨The 6-series exposed the contact pad 8O $ through a plurality of openings 8 1 7 formed in the 4A 'layer. In summary, the present invention has been described in detail with reference to preferred specific examples. However, it should be noted that the present invention is not limited to the disclosed examples. The offense of the present invention should cover modifications and variations that do not depart from the spirit defined by the scope of the following patent applications.

β1 16 ° 74.ptd Page 19 545098 Brief description of drawings [Simplified description of drawings] Figures 1 A and 1 B are schematic cross-sectional views showing the process of a conventional flip chip device; Figures 2 A and 2 B Fig. 3 is a schematic cross-sectional view showing a process of another conventional flip-chip device; Fig. 3 is a cross-sectional view of a conventional circuit board with an insulating protective layer; Figs. 4A and 4B are respectively a circuit according to an example of the present invention Sections of the board; Figures 5A and 5B are schematic cross-sectional views showing the process of forming bumps on the circuit board shown in Figure 4A; Figures 6A and 6B are the circuits shown in Figure 4B respectively A schematic cross-sectional view of an example of a process for forming bumps on a board; FIGS. 7A and 7B are schematic cross-sectional views of another example of a process for forming bumps on a circuit board shown in FIG. 4B; Cross-sectional views of a contact solder pad with a catalytic layer applied to a circuit board according to the present invention; Figures 9 A and 9 B are schematic cross-sectional views of a reflow process for forming a flip-chip solder joint according to an example of the present invention; Figures 0 A and 1 0 B are reflow soldering processes for forming flip-chip solder joints according to another example of the present invention. Figures 1 1 A and 1 1 B are schematic cross-sectional views of the reflow process for forming flip-chip solder joints and board-to-board solder joints according to examples of the present invention; Figure 1 C is a diagram of the technique of using plated solder in accordance with the present invention.

16 ^ 74.pid Page 20 545098 Schematic cross-sectional view briefly explaining the process of forming a flip-chip structure; Figures 1 2 D and 1 2 E are sectional views showing a circuit board according to another example of the present invention, respectively. FIG. 1 A is a cross-sectional view of a circuit board according to another example of the present invention, and FIG. 1 B is a top view of the circuit board shown in FIG. Cross-sectional views of a flip-chip structure with a flip-chip solder joint are formed using the technique of plating solder; and the 13D and 1E diagrams are cross-sectional views showing a circuit board according to yet another example of the present invention. 1 Flip-chip component 1, Flip-chip component 11 Metal bump 12 Electrode pad 13 Wafer 14 Pre-solder bump 15 Contact pad 16 Organic circuit board 17 Solder connection 18 Primer material 19 Solder bump 100 Organic circuit board 101 Contact solder Pad 102 Insulation layer 103 Metal barrier layer 104 Insulation protection layer 105, 106 ,: [08 circuit layer 107 via hole 109 pad gap 110 pre-solder bump 111 contact area 200 circuit board 201 first circuit layer 202 second circuit layer 203 vias 204 contact pads

16974.ptcl Page 21 545098 Brief description of the diagram 205 Insulation layer 207 Resistance layer 209 Solder material 300 Organic circuit board 302 Via hole 304 Second circuit layer 306 Conductive seed layer 308 Opening hole 310 Solder bump 312 Solder bump 402 Electrode Fresh 501 semiconductor wafer 503 electrode pad 601 contact pad 603 electrode pad 606 flip chip solder 701, 7 〇2 contact pad 704 upper surface 706 wafer 708 outer end 710 crystal structure 722 opening 732 surface coating 801, 8 0 6 Conductive wire layer seed hole 6 8 ο ο 210 Solder bump 301 Contact pad 303 First circuit layer 305 Insulation layer 307 Resistive layer 309 Solder material 311 Metal pad 401 Semiconductor wafer 403 Chip-on-chip solder Connect 502 metal bump 600 second circuit board 602 wafer 6 0 4, 6 0 5 metal bump 700 organic circuit board 703 solder bump 705 lower surface 707 electrode pad 709 primer material 721 insulation protection layer 731 conductive wire 800 organic Circuit board 802 contact pad

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Brief description of the drawing 803 Upper surface 804 Lower surface 805 Contact pad 807 Dotted line 808 Solder bump 809 Wafer 810 Electrode pad 811 External end 812 Primer material 813 Crystal structure 814, 815, 818 Surface coating 816 Insulation protective layer 817 Open Hole 821 Insulating protective layer 16974.p; cl Page 23

Claims (1)

545098 VI. Application Patent Scope 1. A micro-pad pitch organic circuit board with plated solder, comprising: at least one surface for soldering (solder j (3 int) formed on at least one contact pad, Is formed on the surface, and the surface is not formed with an insulating protection layer (solder mask 1 ay e) Γ; and a plating solder (plating solder), which is deposited on the contact pads. The circuit board of the first scope of the patent, wherein 'the bell fresh tin is a solder formed by electroplating. 3. The circuit board of the first scope of the patent, wherein the solder is formed by electroless plating 4. For example, please refer to the circuit board in item 1 of the patent scope, wherein the bell solder is a solder formed by a combination of electroplating and M electroplating. 5. As a patent, please refer to λ- / γ target range. The circuit board of item 1, wherein there is no task on the surface of the circuit board Ho conductive wire (conductiv e trace) 〇6. _ A micro-pad pitch organic circuit board with solder plating, the circuit board includes • at least a surface for solder to be formed thereon 9 at least two contact pads, forming On the surface, there is not formed an insulating protective layer and a conductive wire between the pads; and a plated solder is deposited on the contact pads. 7. The circuit board of item 6 of the patent scope, wherein, the Solder-plated solder is fresh tin formed by electroplating. 8. Please refer to the patent No. 6 Circuit Board of Capricorn, where the solder-plated solder is borrowed 16974.ptcl Page 24 545098 6. Scope of patent application Solder formed by electroless plating. 9. The circuit board according to item 6 of the patent application, wherein the solder plating is a solder formed by a combination of electroplating and electroless plating. 1 0. A method for manufacturing a micro-pad pitch organic circuit board with solder plating, the method includes: providing an organic circuit board, the circuit board includes a surface, and at least one contact pad is formed on the surface, and The surface is not covered with an insulating protection layer; a conductive seed layer is formed on the surface of the circuit board, a resistive layer is deposited on the conductive seed layer, and at least one opening is formed at the resistive layer corresponding to the pad. Holes; depositing solder material on the openings by a method of p 1 ating; and removing the resist layer and the conductive seed layer under the resist layer. 1 1. The method according to item 10 of the scope of patent application, wherein the conductive seed layer is formed of a metal selected from the group consisting of copper, tin, and a tin-lead alloy. 12. The method of claim 10, wherein the conductive seed layer has a multilayer structure. 13. The method according to item 12 of the scope of patent application, wherein the multilayer structure is made of a metal selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-boat alloy. form. 14. The method according to item 10 of the scope of patent application, wherein the solder material is selected from the group consisting of copper, tin, silver, copper, silver, zinc, zinc, zinc, magnesium, 16974.ptd Page 25 545098 VI. Scope of patent application Alloy formed by a mixture of elements of the group consisting of indium, tellurium and gallium. 15. The method according to item 10 of the scope of patent application, wherein the plating method is an electroplating method. 16. The method according to item 10 of the scope of patent application, wherein the plating method is an electroless plating method. 17. The method according to item 10 of the scope of patent application, wherein the plating method is a combination of electroplating and electroless plating. 18. The method according to item 10 of the scope of patent application, further comprising the step of forming a metal pad on the contact pad before the solder material is deposited in the opening. 9. A micro-pad pitch with plated solder is organic. A method for manufacturing a circuit board, the method includes: providing an organic circuit board, the circuit board includes a surface, and at least two contact pads are formed on the surface, and the surface is not formed with an insulating protective layer and conductive wires. Between pads; a conductive seed layer is formed on the surface, a resist layer is deposited on the conductive seed layer, and at least two openings are formed at the resist layer corresponding to the pad; A solder material is deposited in the opening; and the resist layer and the conductive seed layer under the resist layer are removed. 20. The method according to item 19 of the patent application scope, wherein the conductive seed layer is formed of a group woven metal selected from the group consisting of copper, tin and tin-slanted alloy. 10974.ptd Page 26 545098 6. Scope of patent application 2 1. The method according to item 19 of the patent application scope, wherein the conductive seed layer has a multilayer structure. 22. The method according to item 21 of the scope of patent application, wherein the multilayer structure is made of a metal selected from the group consisting of copper, tin, copper, copper, copper, copper-copper alloys, and tin-copper alloys. form. 2 3. The method according to item 19 of the scope of patent application, wherein the solder material is composed of a substance selected from the group consisting of impurity, gadolinium, silver, copper, surface, hafnium, zinc, nickel, indium, gadolinium, indium, titanium and gallium. An alloy formed by a mixture of elements of a group. 24. The method according to item 19 of the scope of patent application, wherein the plating method is an electroplating method. 25. The method according to item 19 of the scope of patent application, wherein the plating method is an electroless plating method. 26. The method according to item 19 of the patent application scope, wherein the plating method is a combination of electroplating and electroless plating. 27. The method according to item 19 of the scope of patent application, further comprising the step of forming a metal pad on the contact pad before the solder material is deposited in the opening. 0 8. A micro-pad pitch with plated solder A method for manufacturing an organic circuit board. The method includes: providing an organic circuit board, the circuit board including a surface, and forming at least one contact pad on the surface, and the surface is not covered with an insulating protective layer; A resist layer is deposited on the surface of the board and corresponds to the resist layer 16974.piJ Page 27 545098 6. Scope of patent application At the pad, remove and remove the 2 9 · If applying for a patent, it is selected from lead, indium, tellurium and gallium gold. 3 0 · If applying for a patent, the steps will be carried out before deposition. 31 · As the patented fin particles 3 2 ·-has a plating, the method package provides a surface with insulation protection on the surface of the pad by removing and removing the 3 3. At least one opening is formed; a method of electroplating deposits solder material on the opening; and resists the layer. The range is composed of tin and silver. The range is composed of catalytic layers. Soldering includes: Organic electricity to the layer and the surface of the circuit board to form a resistive layer of money. The method of the 28th item, wherein the fresh tin material is a method of the 28th item formed by a mixture of elements of the group of copper, bismuth, antimony, zinc, nickel, aluminum, magnesium, and the group, further including The method of depositing the solder material (CatalytlC laYer) on the 30 holes of the opening '", the catalytic layer is a method of manufacturing a micro-pad pitch organic circuit board, and the circuit board includes a surface with less two contact pads. R # Shiya deposits a resistive layer on the wire between the solder pads. /, The surface does not form a resistive layer on the surface, and _ Yar + at least two openings in the resistive layer; / 1 Continue the corresponding method to solder the material Accumulate in the opening; by the method of item 32, wherein the delta solder material is 16974.Pid Page 28 545098 6. The scope of the patent application is a mixture of elements selected from the group consisting of erbium, gadolinium, silver, copper, noodles, zinc, zinc, zinc, inscriptions, towns, indium, tellurium and gallium. Formed alloy. 34. The method according to item 32 of the scope of patent application, further comprising the step of depositing a catalytic layer (c a t a 1 y t i c 1 a y e r) on the opening before the solder material is deposited. 35. The method of claim 34, wherein the catalytic layer is formed of I bar particles. 16974.ptd Page 29