TW200409575A - Fine pad pitch organic circuit board with plating solder and method for fabricating the same - Google Patents

Abstract

A fine pad pitch organic circuit board with plating solder and a method for fabricating the circuit board with plating solder are provided. The circuit board is formed with a plurality of densely arranged contact pads on at least a surface thereof in the absence of solder mask being applied over the surface. After deposition of a conductive seed layer on the contact pads, a resist layer is applied over the surface of the circuit board, and formed with a plurality of openings for exposing the seed layer corresponding in position to the contact pads. Then, a solder material is deposited in the openings by a plating method. Finally, the resist layer and the seed layer underneath the resist layer are removed, making the circuit board readily subject to subsequent fabrication processes for forming flip-chip joints or board-to-board joints.

Description

200409575. V. Description of the invention (1) ------[Technical field to which the invention belongs] ^ ^ The Ming is related to ~ types used in electronic packages and have solder plating ^ are gone; specifically The invention relates to an organic circuit board with a plated solder, a 4 1 dry pitch, the plated solder is used to form a flip-chip solder joint and a board-to-board solder joint, and relates to a method for manufacturing the micro-fresh plated solder.塾 Pitch method of organic circuit board. [Prior technology] — Since ίβΜ introduced flip chip ~ package technology in early 960, because the difference in thermal expansion coefficient between the silicon wafer and the ceramic substrate is small, so the flip chip is mainly installed in Expensive ceramic substrate. Compared with wire bond technology, flip chip technology is characterized in that the electrical connection between the chip and the substrate is through solder bumps instead of wire bonding. The advantage of this flip-chip technology is that this technology can increase the packaging density to reduce the component outline; at the same time, this flip-chip technology does not require the use of longer metal wires, so it can improve electrical performance. In view of this, the industry has used high-temperature solder on ceramic substrates, the so-called control-col 1 apse chip connect technology (C4) 5 for 40 years. However, in recent years, due to the need for high-density, high-speed, and low-cost semiconductor components, and in response to the gradual shrinking of electronic products,-flip-chip devices are provided on low-cost organic circuit boards (for example, printed circuit boards) Or substrate), and filled with epoxy resin primer (UnderflU resin) under the wafer to reduce the thermal stress caused by the difference in thermal expansion between the structure of the Shixi wafer and the organic circuit board, has been explosive growth. The industry's attention to low-temperature flip-chip soldering

16974 · ptd ^ page 6 --- ~ --- 5. Description of the invention (2) The manufacturing cost of the flip chip. Electricity is arranged on the surface of the current low-cost overlay body: electrodes: pads, f-conductor body circuit (K) wafers can use ^ contact pads. Materials are attached to the wafer and the circuit. The chip 俜 = 二 地 5 is also provided with low-temperature solder bumps or other conductive adhesive boards, with the neutral contact surface facing down, and is provided between the circuit boards; the adhesive material provides ... tin bump solder connections (s 〇 〇 Der 0) and mechanical connection. As far as soldering the wafer and the circuit board (22: p 2 1nt), the thermal expansion between the wafer and the circuit board can be further advanced, and an organic primer can be used to suppress the first 1 A and Figure 1B illustrates that the stress of the solder joint is reduced. The solder joint is formed by combining a conventional flip-chip device with a metal, in which several metal bumps and two pre-solder bumps are formed as shown in the soldering. As shown in the figure, a number of pre-solder bumps 14 formed by contact soldering of the electrode pads 1 2 ^ machine circuit board 16 formed on the wafer 13 by low temperature soldering are formed on the molten reflow temperature conditions ^ . If the pre-solder bumps 1 4 are sufficient for the metal bumps 11 corresponding to the shape of the pre-solder bumps 1 4, the pre-solder bumps Η can be re-soldered to the wafer 13 and the zinc-tin solder 17 17. Then, the primer material 1 8 is soldered and 7 is wrapped in it, that is, the gap between the circuit board 6 and the welding is described as another unused pre-soldering: forming flip chip components 2A and 2B The diagram shows that teaches a solder bump 119 = chip-on-chip component 1. As shown in the figure, the wafer 13 is re-soldered to the electrode pads 12 formed on the wafer 13. The contact solder | board ^ 1 6 connected to the circuit board 16; wherein, the solder bump 19 is soldered with 塾 15 to form a solder joint 7. And finally

Page 7, 200409575, V. Description of the invention (3) 1 glue material 1 8 is filled in the gap between the wafer 丨 3 and the circuit board 丨 6, and the solder joint 17 is wrapped in it, and the coating is completed. Crystal element 1, FIG. 3 illustrates a conventional organic circuit board 100 for a flip-chip package. The circuit board has a contact pad 10 and the pad gap 10 is larger than 0. 18 mm. The insulating layer 10 of the organic circuit board 100 may be made of an organic material, an organic material mixed with fibers, or an organic material mixed with particles (for example, epoxy resin (ρ ο 1 yimide), polyurethane ρ 〇1 yimide , Bis (succinimide / diazine), biseleimide triazine, cyanate _ ester, polyicyclobutene (poiybenzocyclobutene) or glass fiber (g 1 assfiber) composite materials, etc.) Made of. The contact pad 1 0 1 is typically formed of a metal material (for example, copper). A general metal barrier layer 103 includes a nickel adhesion layer and a gold protective layer formed on the pad 101. However, the barrier layer can also be made of gold, nickel, palladium, silver, tin, nickel / ί 巴, ///, 把 / 金 or // 妃 / 金, etc., by electroplating, electroless plating) or physical vapor deposition (physical ca 1 vapor depos iti on). On the surface of the circuit board 100, an organic insulating protective layer (organic sol d e r m a s k 1 a y e r) 104 is deposited to protect the circuit layer 105 and provide insulation characteristics. The top two circuit layers, 105 and 106, are generally electrically connected through vias 10 7 which are well known in the field. Referring to FIG. 3, in a case where the pad gap -10 9 is large (for example, greater than 0.18 mm), the circuit wire 108 may be disposed between the two contact pads 101. Pre-fresh tin bumps 1 10 are formed on the contact pads 101 to form flip-chip solder joints. Among them, the current industry mainly uses stencil printing technology (s ΐ enci 1 printingtech η〇1 〇gy) to deposit fresh solder. tin

16974.ptd Page 8 200409575 V. Description of the Invention (4) To form solder bumps. ^ ^ P: n Si 44- η Λ on the handle of the circuit, so the common method of forming pre-solder bumps (such as stencil printing technology) can be removed > Kokoku Patent No. 5, 2 0 3 , 0 7 5 (Angulas et an, Gaiyang by rw κ, al) Wu Guo Patent No. 5, 4 9 2, 266 C Hoebener et al) and Mioka direct production to Guangzhou rw. U · Fuyuan Patent Brother 5 , No. 8 2 8, 1 2 No. 8 Chigashiguchi et al), etc., especially Fen Imu;! Related related prior art disclosed by Xunli. However, the reduction of 0 ^ 1 < to n Chen 1 0 9 is reduced to less than 0.15 mm. 〇 Noon is not feasible; in addition, with the reduction of the red pad gap 1 0 9, the insulation can sound 彳 nj " Book 1 of the return of the person's body 丨 "~ 104 for the circuit board 100 open contact area 1 1 1 becomes smaller, and ^ ^, i makes the insulating protective layer 1 0 4 for The adhesive strength of the children's board 100 has a tendency to weaken. 1. The use of electroplating to form solder bumps KB A,, can be used to overcome the limitation of this type of I drylands, use electroplating to dry in flip chip! Prior art related to pitch has been disclosed in U.S. Patent No. 5 = t solder bump et al) and U.S. Patent No. 5,48,0 3,5 (h, if Tiger (Gall plating process still exists to make it possible to form In this: _ However, the shortcomings are known, and the uniformity of the plating needs to be considered, and the high Tang of the bumps is also considered. Σ 'The existence of a protective layer on the edge will also affect the circuit board -f- Λ% Spreading the moon dagger produces unfavorable orders, especially when the pad spacing is less than 0.15 mm; 'the insulation protection layer formed on this circuit board is small for the Emperor to change the moon condition' (see As described in Figure 3 above), under the influence of the environment *, the adhesion of the circuit board ^ deteriorates the surface and spreads easily, which makes it easy to lose its insulation properties. Compared with the organic circuit board, the metal / spoon edge protective layer Its' Yu Bian Jui Ji I material, usually has a higher CTE and a lower glass transition temperature (rr / / tr ".. ^ Vglass ansition temperature); therefore, the Micro-pad

200409575

• V. Description of Invention (5). The protective layer touches the conductive resistance layer between the micro-soldering pads covered with a crystal protective layer on the surface of the electric solder connected with the pads, and a conductive resistance layer is provided to make the crystal tin material conductive. There is an insulating protective layer at the distance. May reduce reliability ^ In view of the above problems, it is necessary to provide an organic circuit with a micro-pad pitch between micro-pads of an insulated circuit board ^ A method of depositing solder bumps on the pads of a circuit board Solder connection to the board. [Design of the Invention] The main object of the present invention is to provide a contact pad having a plurality of arrays of printed circuit boards, which are formed by solder plating, and the contact pads are arranged on the surface. ^ Covering the soldering heat,… ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, and During Up Up-Up-Up the Solder Joints of the Tin-to-Board Solder Joints. The 4 pad spacing organic # = 4 purpose is to provide a method for forming an organic electric pole with a plated solder pitch. The method is to first provide a micro and the table ^ ^ The circuit board has-Table S is provided with at least one crystal A seed layer deposition edge protective layer covers the pad spacing; and is connected to the corresponding pad; a layer is exposed on the conductive seed layer to expose at least one opening is formed at the position for deposition; At this opening, a seed layer is welded by a plating met hod. And 'removing the resist layer and the present invention under the resist layer—the pad pitch organic circuit 7 aims to provide a method for forming a micro-pitch organic circuit board with plated solder, and the reverse method, which first provides a There is no right pen circuit board on the surface between the micro-welding pads and the surface is provided with at least one contact pad /, and the edge protection layer covers the pad pitch;

200409575 V. Description of the invention (6) The surface is covered with a resistive layer, and less....

A hole is made so that the seed wind should contact the welding I. The layer is exposed at the position where the potential is exposed (eleCtr0less plau: mined, and the main material is deposited on the opening through the non-doped material; and, removed The resistance layer is used to form a solder chip, and the present invention has a plated solder sheet to form a flip-chip solder joint. The moment between the micro-pads is much larger than the conventional method. It is used: a circuit board forming board; The circuit board may have a solder connection on the tertiary surface of the circuit with insulation and spectrum spreading. The application of the insulating protective layer to the 2 efficiency produces no :: ί in the soldering pitch space, you can use the contact front Pad 22, the invention of the non-soldering pad 'χ will not produce ^' Sink the solder material successfully: dense area of the circuit board and affect the reliability ° The surface is used in the method and there is: :: [实施 方式] 孭 改The problem of a protective layer with edges is shown in Figures 4 to 13 in detail from the organic circuit board and its manufacturer. The preferred embodiment is the circuit layer 2 0 2, wherein the jigsaw board 200 includes a first circuit layer 2Q1 and a second space. 'The insulating layer layer 201 is electrically connected to the second circuit layer 202. The insulating acoustic core :: L This-is connected to the second circuit amine, cis-butene-lacks food ingredients (such as epoxy resin) , Polyimide, or complex * ^ dilute primary imine / triazine, cyanate ester, polybenzocyclobutene with only: Ϊ: Ϊ: ίπ materials,). On the first circuit layer 201 Compound /,, and dry without other metal wires (traces) formed in accordance with the needs of the current, gold, nickel, palladium, silver, tin, gold / nickel,

Page 11

200409575, V. Description of the invention (7) Recording / Ji or Recording / 1 '~', covered with metal such as surface / gold, etc. Touch pad 2 0 4j: v The metallic barrier sound composed by v is open. ^. On the other hand, the ammonium anion formed on this connection can also be designed as a person. As shown in the figure 4β, the organic connection is only ^ The surface only contains the contact pad qni, and the circuit board 30 is located exactly at t Hai pilot hole ship 301 ′ The contact welding pad has a metal layer made of gold, nickel, “w 1 5 接触 contact pad 3 0 1” and a barrier layer. The organic + Circuit / nickel / handle or nickel / free / gold, etc. 3 0 3 and the second circuit layer 304, 4%: 3. 0 also includes the-circuit layer ^ 3. and 11 through the via 302 makes the first layer have -Insulation M edge layer 305 can be electrically connected by organic materials, silicon, and circuit layers. Organic materials, such as epoxy tree II, organic materials or mixed particles of donkey imine / triazine, It is made of cyanoacetate, polythionylamine, maleic acid, etc.). Similarly, a 12: 2 FF glass field fiber is provided with an insulating protective layer formed thereon. X% 路The surface of the board 3 does not have I and a. 'When the contact pads 2 0, 4 and 3 1 have a micro pad pitch, they can be arranged or plated.) The solder material is deposited to This method (for example, plating Or the non-electricity / branches of the main circuit board 2 00, 3 0 0 on the contact pads 2 0, 3 0 1. Before depositing solder material on the contact pad 2 0 41, A conductive seed layer (to be described in detail later) is formed on the contact pads 2 0 4 and 3 1 to facilitate the deposition of solder material. The conductive seed layer can be formed by physical vapor deposition (PVD), chemical Vapor deposition (CVD), electroless plating or chemical sinking, such as spu 11 ering, evaporation-electric arc i: gas vapor deposition, ion beam sputtering (ion beam sputtering) Lightning in laser ablation deposition, plasma to promote chemistry

16974.ptd

200409575 V. Description of the invention (8) Methods such as vapor deposition (PECVD) or organic metal chemical vapor deposition (mCVD) are formed on the surfaces of the circuit board 2000 and 300. As shown in Figure 5A, the conductive seed layer 2 0 6 is first deposited on the contact pad 2 4 of the circuit board 2 0, and then the resist layer 2 7 is directly applied to the conductive seed layer 2 0. 6; and at least one opening 2 0 8 is formed in the resist layer 2 0 7 at a position corresponding to the contact pad 2 0 4 to partially expose the conductive seed layer 2 0 6. Through a plating process (preferably electricity), a fresh tin material 209 is deposited on the openings 2 0 8 that expose the conductive seed layer 206; then, as shown in FIG. 5B, Remove the resist layer 207 and the conductive seed layer 206 covered by the resist layer; finally, perform reflow at a reflow temperature sufficient to melt the deposited solder material 009 ( re Π 〇w — s 0 1 dering), so that the solder material 209 is re-soldered to form a group of solder bumps 2 1 0 on the contact pad 2 04. Similarly, referring to the circuit board 3 00 shown in FIG. 6A, the conductive seed layer 3 06 is first deposited on the contact pad 3 3 of the circuit board 3 0, and then the resistance layer 3 7 Directly cast on the conductive seed layer 3 06; and make the resistance layer 3 07 form at least one open S hole 3 08 at a position corresponding to the contact pad 3 01 to partially expose the Conductive seed layer 306. Next, a solder material 3 0 9 is deposited on the opening 3 0 8 by a ^ coating process; then, as shown in FIG. 6B, the resist layer 3 7 and the conductive seed under the resist layer are removed. The layer 3006; ^ a process of reflow soldering causes the deposited solder material 309 to be reflowed: a solder bump 3 1 0 is formed on the contact pad 3 0 4. The conductive seed layer 206 and 306 can be made of metal, alloy, or a plurality of layers of gold). However, according to practical experience, the conductive sounds 2 0 6 and 3 6 6 are preferably made of copper or particles (especially without electricity).

16974.ptd Page 13 200409575 V. Description of the invention (9) Ping tin materials 2 0 9 and 3 0 9 may be selected from the group consisting of potential, zinc, nickel, zirconium, magnesium, indium, tellurium; tin, silver, copper, An alloy of bismuth, antimony, and compounds. It should be noted that the composition of the group of elements can also be formed between the contact pads. If necessary or feasible, according to the present invention, the solder material is formed in a manner of depositing elements. For example, ^ 9, 3 0 9 can also be used to deposit a thin silver layer and a tin layer by continuous forging plating. In the back = 208, 3 0 8 in order to form eutectic tin-silver solder bumps 2 by tin. After being clothed, silver will eventually dissolve in another embodiment of the present invention, 0310. The solder material can also be formed before the metal is formed on the contact pad. As shown in FIG. 7A, after the resist layer 3 07 deposited on it is subsequently lifted, the position corresponding to the contact pad 3 01 is cast by using electroplating or i-percent circuit board 300 as an example. In addition, a plurality of metal pads 311 are formed on the conductive seed layer by 306 phases. This type of metal is composed of exposed portions or multiple layers of metal layers, and is preferably made of jade: pad, 3 ^ can be made of a single metal layer such as Snpb, SnAg, or SnCu alloy, or steel or south temperature solder (Example material 3 0 9 is deposited on each metal pad 31 丨; then. Then, a solder material is formed on the metal pad 3 1 1 to perform the re-soldering process, as shown. 312, as shown in FIG. 7B, as shown in FIG. 8, it is possible to selectively contact the pad 3 0 1 instead of being formed on the Thai 1 ~ seed layer 3 0 6 formed on the resist layer 3 formed thereon. For example, it can be deposited on the entire surface of the plate 3 0; directly deposited on the seed layer f tin material (not shown) by electroless plating. The seed layer 3 6 is actually the | Electric \ 6. In this case, the ..., the catalyst layer of the process of money. However,

200409575 V. Description of the Invention (ίο) Even in the absence of the catalytic layer (ie, the seed layer) 3 06, the solder material 3 0 9 can be directly deposited on the contact pad by an electroless plating process. 3 0 1 on. Therefore, by using an electroless plating process, the solder materials 209, 309 can also be deposited on the resistive layer 207, 3 without the seed layer 206, 3 06. The openings of 0 7 are within 208, 308. The seed layer 2 06 and 3 6 on the circuit board 2 0, 3 0 0 should have a relatively thin thickness, so that it can be easily removed by etching. Actually, the seed layer is more effective with a thickness of 0. 0. 01 to 0. 0. 1 mm. Regarding Chankelo, you can refer to known metallographic books (meta 1 1 〇gra P hy) (for example, nMetallographic etching 1, Gunter Petzow, American Society for Metals, Metals Park, Ohio (1 9 7 8)) to choose . In addition, the via holes 203, 302 can be filled by plating, or the via holes can be filled or partially filled with a conductive substance (for example, copper, a solder alloy, a resin filled with a metal, or a metal filled with a slave, etc.). Provide the characteristics of electrical conduction of the via holes 203, 302. More specifically, when the composition of the conductive material is the same as that of the solder materials 209 and 309, the via holes 203, 302, and the plating of the solder material can be performed in the same plating step. In progress. In addition, the insulating layers 205 and 305 may be chemically or physically roughened as required to provide better adhesion characteristics in subsequent packaging processes. As shown in FIG. 9, the solder bump 3 1 0 can be manufactured on the contact pad 3 0 1 of the circuit board 3 0 0 for application to Fei Yue # 姐 枝 / 'Crystal fresh tin connection (f 1 i Ό _ chi η j〇int). Prepare a number of semiconductor wafers 4 (H, with electrode pads 4 0 2). The electrode pads 4 0 2 are used to match each other. ^ Slice m corresponds to the position of the circuit 柘 锃 瓴 bump 310. = Board 3 0 0 1 dry tin V daily day film 4 0 1 set in this circuit

ϋ 1— 1 ϊ — -1 ·

16974.ptd 8 Lr.

200409575, V. Description of the invention (11) 舨 3 0 0; then, as shown in FIG. 9 β, a reflow process is performed to re-solder the solder bump 3 1 0 to the electrode pad 4 0 2 to Between the semiconductor wafer 400 and the circuit board 300, a plurality of flip-chip solder joints 403 for electrically connecting the semiconductor wafer 401 and the circuit board 300 are formed. In another embodiment of the present invention, the circuit board 300 having a solder bump 3 丄 0 can be applied to a semiconductor wafer having a metal bump to form a flip-chip solder joint. As shown in FIG. 10A, the semiconductor wafer 501 has a plurality of electric pads 503 formed on the active surface of the semiconductor wafer 501, and the electrode 501 has several applications. In order to form a flip chip solder metal bump 502. The semiconductor wafer 501 is disposed on the circuit board 300 in such a manner that the metal bumps 502 correspond to the positions of the solder bumps 310 of the circuit board 300 respectively. Then, as shown in FIG. 10B, the solder bump 3 10 is re-soldered to the metal bump 5 2 to form a double & amp between the semiconductor wafer 5 0 1 and the circuit board 3 0 0. Jing Jing Yu tin connection 5 0 4. The metal bump 502 may be made of metal, alloy, or most racial metal, such as solder bumps, gold bumps, copper bumps. Μ 4 dry solder towels covered with copper pillars, etc .; and The metal bump can be of any shape: for example, a stud bump, a spherical bump, a stud bump, or 'other bump'. According to the present invention, the circuit board can also be used to form a connection and a board-to-board Solder connection. In this embodiment, the circuit board 2000 of the 2 tin bump 210 will be used for illustration. As shown in the m-th figure, it is controlled by a circuit board 600 (hereinafter referred to as "second circuit" Put the machine on or prepare the circuit board, i will place the chip 6 = a suitable position of the board; on the second Φρ%, press the circuit board 6 0 0 to the circuit board, and place several contact pads 6. 1

200409575 V. Description of the invention Q2) is formed on the periphery of the wafer 602, wherein a plurality of metal bumps 604, 6 05 are respectively formed on the contact pads 6 0 of the second circuit board 600 1 and the electrode pads 603 of the wafer 602. Then, the second circuit board 6 0 is formed on the circuit board 2 0 (hereinafter referred to as “the first circuit board”) by orienting the metal bumps 6 0 4 and 6 5. The manner of the solder bump 2 1 0 is set on the first circuit board 2000. As shown in FIG. 11B, the metal bumps 6 0 4 and 6 0 5 are refreshed to the corresponding solder bumps, respectively. Block 2 1 0, so that a flip chip solder joint 6 0 6 is formed between the wafer 6 0 2 and the first circuit board 2 0 0, and the second circuit board 2 0 0 and the first circuit board 2 0 Board-to-board solder joints 6 and 0 are formed between 0. The metal bumps 604, 605 can be made of metal, alloy, or a combination of several metals such as solder bumps, gold bumps, and copper bumps. Or copper pillars covered with solder caps; and the metal bumps can be of any shape, such as stud bumps, spherical bumps, columnar bumps, or other shapes of bumps. Please refer to Figure 12A According to the present invention, the circuit in FIG. 4A and a similar process of 2000 can be used to form a substrate or wafer carrier for manufacturing a flip-chip structure '7 1 0 (not shown in FIG. 12 C). The organic electric circuit board 700 is manufactured by using the similarity of an insulating protective layer, and the upper and lower surfaces of the circuit board 704, == $, and the contact pads 701, 7 0 2. Please 夂The γ cage 19R is formed into several pieces called Lingzhuangdi 12B, and a plurality of solder bumps 703 are formed on the "contact pad 701" by plating. Please refer to the figure ': the wafer 706 is placed on the circuit board 700 in a flip-chip manner, and this kind of method is to weld the electrode pad 塾 m formed on the wafer 7.6 into a wt circuit board 7GG. Solder bump 703; Then, / 709 fills the gap between the wafer 706 and the circuit board 700.

16974.ptci 200409575 V. Description of the invention (13) Writing 'Plug several external terminals 7 0 8 (for example, fresh balls as exemplified in the figure) into the contact pad 7 0 2 of the circuit board 7 0 0, Thus, the flip-chip structure 710 is completed. ^ On the other hand, as shown in FIG. 12D, an insulating protective layer 7 2 丨 can be applied to the circuit board 7 0 0 provided with a lower surface of a contact pad 70 2, and the insulating protective layer 7 2 1 A plurality of openings 7 2 2 are formed at positions corresponding to the contact pads 702, and the contact pads 7 02 are exposed through the openings, so as to facilitate subsequent external end implantation (not shown) ). Also, as shown in the figure i 2E, conductive lines 7 3 1 ′ may be formed on the lower surface of the circuit board 7 0 0 provided with contact pads 7 0 2, and a surface may be formed on each conductive line 7 3 丨. Coating 7 3 2 (eg, gold, nickel / gold or epoxy, etc.) to prevent corrosion. In FIG. 13A, the circuit board 200 shown in FIG. 4A can be used to fabricate a flip chip structure 813 (as shown in FIG. Circuit board 800. The circuit board 800 is made of unused insulation material; ^ is formed on the upper surface 8003 of the board 800; ^ is manufactured by a similar method; and a conductive line is formed on the circuit +4 801 and the contact pad 802, and the circuit board 800 under the cu ^ ^ ^ ^ ^ Sense surface 8 0 4 is formed with the contact pad 805 and the adjacent two adjacent photos hidden on the visual surface. ΐ3B diagram 'Because it is located on (for example, at least less than the welding gap between 塾 ⑽2 is quite small adjacent to the contact pad 8 〇 2 ^ the conductive line 8 0 1 can not pass through the connection to the dotted line 8 0 It is included in 7. Therefore, the conductive wire 801 is mainly connected back to FIG. 13A, and the contact pad 802 is located on the inner edge of the bump region. Several pads 8 are formed on the pad 8202. 〇The upper surface 803 contacts the welding ghost 8 008 for use in subsequent processes.

16974.ptd Page 18, 200409575 V. Description of the invention (14) ------ As shown in the following sound image, an insulating protective layer 8 2 1 can be applied on the upper surface of the circuit board 8 0 0 and ^ The area covered by the dotted line 807 is exposed as shown by covering the conductive line 8 0. 4 1 I. Then, a wafer 8 0 9 with electrode pads 8 0 is set on the circuit board 8 00, and a primer material 8 1 2 is filled between the wafer 8 0 9 and the circuit board 8 0 0 ^ Gap. Finally, connect the external terminals 8 (such as solder balls, pins, or metal posts). The contact pads 805, which are located on the surface of the circuit board 800 below the 800, are further formed into the flip-chip structure 813. On the other hand, as shown in the first figure, a surface coating layer 8 1 4 (for example, a tor / metal or solderable organic protective agent (〇SP), etc.) can be formed on each contact pad 8 0 5, and A surface coating 8 1 5 (for example, gold, gold / epoxy or epoxy resin) is formed on the conductive wires 801, 806 to prevent rot I. Furthermore, as shown in FIG. 13E, another option is to form a surface coating 8 1 8 on each conductive wire 8 0 1 located on the surface 8 0 3 of the circuit board 8 0 (for example, 0SP, Epoxy resin, gold, copper / gold, etc.), and an insulating protective layer 8 i 6 is covered on the surface 8 0 4 of the circuit board 800 to cover the conductive wire 8 06; however, the insulating protection The layer 8 1 6 exposes the contact pad 8 05 through a plurality of openings 8 1 7 formed in the protective layer. In summary, the present invention has been described in detail with reference to preferred specific examples. It should be understood, however, that the invention is not limited to the disclosed examples. The scope of the present invention should cover modifications and changes made without departing from the spirit defined by the scope of the following patent applications.

16974.ptd Page 19, 200409575. Brief description of the drawings 1 [Simplified illustration of the drawings] Figures 1 A and 1 B are schematic cross-sectional views showing the process of a conventional flip chip device; Figures 2 A and 2 B are A schematic cross-sectional view showing a process of another conventional flip-chip device; FIG. 3 is a cross-sectional view showing a conventional circuit board with an insulating protective layer; and FIGS. 4 A and 4 B are views respectively showing examples according to the present invention. Cross-sectional view of a circuit board; Figs. 5A and 5B are schematic cross-sectional views respectively showing a process of forming bumps on the circuit board shown in Fig. 4A; Figs. 6 A and 6 B are respectively shown in Fig. 4B A schematic cross-sectional view of a process example of forming bumps on the circuit board shown; FIGS. 7A and 7B are schematic cross-sectional views of another process example of forming bumps on the circuit board shown in FIG. 4B, respectively; Figure 8 is a cross-sectional view of a contact pad with a catalytic layer applied to a circuit board according to the present invention; Figures 9 A and 9 B are schematic cross-sectional views of a reflow process for forming a flip-chip solder joint according to an example of the present invention Figures; Figures 10 A and 10 B are another example of the present invention, forming a flip-chip solder joint Cross-sectional schematic diagrams of the reflow process; Figures 1 1 A and 1 1 B are schematic cross-sectional diagrams of the reflow process of forming flip-chip solder joints and board-to-board solder joints according to an example of the present invention; Section 1 2 Figures A to 1 C are diagrams of the techniques used in the present invention using plated solder.

16974.ptd Page 20 200409575 Schematic cross-sectional diagrams briefly explaining the process of forming a flip-chip structure; Figures 1 2 D and 1 2 E are cross-sectional views of a non-invented plate by Genji; Figure 1 3 A The drawing shows a cross-section of the circuit of the circuit board of the first example according to the present invention. # 1SB is a 苐 1 3 C diagram of the circuit board shown in FIG. 13A, which shows a view according to the present invention; A cross-section view of the chip-on-chip structure. The solder-plated technology board is a cross-sectional view. The knife shows according to the present invention that another 1 flip chip 1, 11 metal bump 1 flip chip 13 wafer 12 * 1 electrode pad 15 contact pad 14 pre-solder bump 17 solder connection 16 organic circuit board 19 fresh tin bump 18 Primer material 101 Contact pad 100 Organic circuit board 103 Metal barrier layer 102 Insulating layer 105, 106, 108 Circuit layer 104 Insulating protective layer 109 Pad gap 10 7 Via 111 Contact area 110 Pre-soldering bump Block 201 First circuit home 200 Circuit board 2 03 Via g 202 Second circuit layer 204 Contact pad example circuit

Page 21, 200409575 Brief description of the diagram 405 Insulation layer 207 Resistive layer 209 Solder material 300 Organic circuit board 302 Via 304 Section --- Circuit layer 306 Conductive seed layer 308 Opening hole 310 Solder bump 312 Solder bump 402 Electrode welding Pads 501 Semiconductor wafers 503 Electrode pads 601 Contact pads 603 Electrode pads 606 Chip solders 701, 7 0 2 Contact fresh 704 Upper surface 706 Wafer 708 External end 710 Crystal structure 722 Opening 732 Surface coating 8 0 1,8 0 6 Conductive wire layer \ lCul Seed hole opening 210 Solder bump 301 Contact pad 303 First circuit layer 305 Insulation layer 307 Resistive layer 309 Solder material 31 1 Metal pad 401 Semiconductor wafer 403 Chip-on-chip solder Connect 502 metal bump 600 second circuit board 602 wafer 6 0 4, 6 0 5 metal bump 700 organic circuit board 703 solder bump 705 lower surface 707 electrode pad 709 primer material 721 insulation protection layer 731 conductive wire 80 0 Organic circuit board 802 contact pad

16974.ptci p. 22 200409575 i

Brief description of I® drawing 803 Upper surface 804 Lower surface 805 Contact pad 807 Dotted line 808 Solder bump 809 Wafer 810 Electrode pad 81 1 External end 812 Primer material 813 Crystal structure 814, 815, 8H 丨 Surface coating 816 Insulating protective layer 817 Opening hole 821 Insulating protective layer 16974.rtd Page 23

Claims (1)

200409575-VI. Patent application scope '1. A micro-pad pitch organic circuit board with solder plating, comprising: at least one surface for forming a solder joint (s ο 1 derj 〇int) on it; at least one The contact pad is formed on the surface, and a solder mask layer is not formed on the surface; and a plating solder is deposited on the contact pad. 2. For the circuit board under the scope of patent application item 1, wherein the solder plating is fresh tin formed by electricity ore. 3. For the circuit board of item 1 of the patent application scope, wherein the solder plating is a solder formed by electroless plating. 4. For the circuit board of the scope of patent application item 1, wherein the solder plating is a solder formed by a combination of electroplating and electroless plating. 5. The circuit board according to item 1 of the scope of patent application, wherein the surface of the circuit board does not have any conductive traces. 6. An organic circuit board having a micro-pad pitch with solder plating, the circuit board comprising:-at least one surface for solder formation thereon; at least two contact pads formed on the surface, No insulating protection layer and conductive wire are formed between the pads; and a solder plating is deposited on the contact pads. 7. For a circuit board with the scope of application for patent item 6, wherein the solder plating is a solder formed by electricity ore. 8. For a circuit board with the scope of patent application item 6, wherein the solder plating is borrowed 16974.ptd Page 24 200409575 6. Scope of patent application Solder formed by electroless plating. 9. The circuit board according to item 6 of the application, wherein the solder plating is a solder formed by a combination of electroplating and electroless plating. 1 0. A method for manufacturing a micro-pad pitch organic circuit board with solder plating, the method comprising: providing an organic circuit board, the circuit board including a surface, and forming at least one contact pad on the surface, and The surface is not covered with an insulating protection layer; a conductive seed layer is formed on the surface of the circuit board; a resistance layer is deposited on the conductive seed layer, and at least one opening is formed at the resistance layer corresponding to the pad. Holes; depositing solder material on the openings via a method of p 1 ating; and removing the resist layer and the conductive seed layer under the resist layer. Π. The method of claim 10, wherein the conductive seed layer is formed of a metal selected from the group consisting of copper, tin, and a tin-lead alloy. -12. The method according to item 10 of the scope of patent application, wherein the conductive seed layer has a multilayer structure. 13. The method according to item 12 of the scope of patent application, wherein the multilayer structure is made of a metal selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy. form. 14. The method according to item 10 of the scope of patent application, wherein the solder material is selected from the group consisting of tin, tin, silver, copper, surface, antimony, zinc, nickel, I, Lu, 鎭, 16974. ptci, page 25, 200409575, VI. Application scope < Alloys formed by a mixture of elements of the group consisting of indium, tellurium and gallium ° 15. The method according to item 10 of the scope of patent application, wherein: This plating method is a plating method. 16. The method according to item 10 of the scope of patent application, wherein the plating method is an electroless plating method. 17. The method according to item 10 of the scope of patent application, wherein the plating method is a combination of electroplating and electroless plating. 18. The method according to item 10 of the scope of patent application, further comprising the step of forming a metal pad on the contact pad before the solder material is deposited in the opening. 9. A micro-pad pitch with plated solder is organic. A method for manufacturing a circuit board, the method includes: providing an organic circuit board, the circuit board includes a surface, and at least two contact pads are formed on the surface, and the surface is not formed with an insulating protective layer and conductive wires. Between the pads;. Forming a conductive seed layer on the surface, depositing a resistance layer on the conductive seed layer, and forming at least two openings at the resistance layer corresponding to the pad; A method of depositing solder material in the opening; and removing the resist layer and a conductive seed layer under the resist layer. 20. The method according to item 19 of the patent application scope, wherein the conductive seed layer is formed of a group woven metal selected from the group consisting of copper, tin, and tin-lead alloy. 16974.ptd Page 26 200409575 VI. Scope of Patent Application 2 1. The method according to item 19 of the patent application scope, wherein the conductive seed layer has a multilayer structure. 22. The method according to item 21 of the scope of patent application, wherein the multilayer structure is made of a metal selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy. form. 2 3. The method according to item 19 of the scope of patent application, wherein the solder material is composed of copper, tin, silver, copper, silver, antimony, zinc, nickel, aluminum, magnesium, indium, tellurium, and gallium An alloy formed by a mixture of elements of a group. 24. The method according to item 19 of the scope of patent application, wherein the plating method is an electroplating method. 25. The method according to item 19 of the scope of patent application, wherein the plating method is an electroless plating method. 26. The method according to item 19 of the patent application scope, wherein the plating method is a combination of electroplating and electroless plating. 27. The method according to item 19 of the scope of patent application, which includes the step of forming a metal pad on the contact pad before the solder material is deposited in the opening. 0 8. A micro-solder with plated solder A method for manufacturing a pad-pitch organic circuit board, the method comprising: providing an organic circuit board including a surface, and forming at least one contact pad on the surface, and the surface is not covered with an insulating protective layer; A resist layer is deposited on the surface of the circuit board, and corresponds to the resist layer 16974.ptd Page 27 200409575 / VI. Patent application scope At least one opening is formed in the solder joint; a solder material is deposited in the opening through an electroless plating method; and the resist layer is removed. 29. The method according to item 28 of the scope of patent application, wherein the solder material is composed of copper, tin, silver, copper, silver, antimony, zinc, copper, metal, town, indium, tellurium, and gallium An alloy formed by a mixture of elements of a group. 30. The method according to item 28 of the scope of patent application, further comprising a step of depositing a catalytic layer on the openings before the solder material is deposited. 31. The method of claim 30 in the scope of patent application, wherein the catalytic layer is formed of palladium particles. 3 2. —A method of manufacturing a micro-pad pitch organic circuit board with solder plating, the method comprising: providing an organic circuit board, the circuit board including a surface, and forming at least two contact pads on the surface And the surface is not formed with an insulating protection layer and a conductive wire between the bonding pads; a resistance layer is deposited on the surface of the circuit board, and at least two openings are formed at the resistance layer corresponding to the bonding pads; An electroless method deposits a solder material on the opening; and removes the resist layer. 3 3. The method according to item 32 of the scope of patent application, wherein the solder material is 16974.ptd Page 28, 200409575 6. The scope of the patent application is a mixture of elements selected from the group consisting of tin, tin, silver, copper, silver, zinc, zinc, zinc, inscriptions, towns, indium, tellurium and gallium. The formed alloy ° 3 4. The method according to item 32 of the patent application scope further comprises the step of depositing a catalytic layer on the openings before the solder material is deposited. 35. The method according to item 34 of the scope of patent application, wherein the catalytic layer is formed of palladium particles. 16974.ptd Page 29