TW519859B - Method of forming electroplated solder on organic circuit board - Google Patents

Abstract

A method of forming electroplated solder on the organic circuit board is disclosed in the present invention and can be applied in the formation of flip-chip package. According to the invented method, an organic circuit board having circuit layout on its surface is provided, and at least one contact pad is installed on the organic circuit board. The circuit board surface is covered with an organic insulation layer (solder mask layer), which is then patterned to form an opening at the corresponding pad position on the organic circuit board. Then, a metal seed layer is formed on the circuit board surface, in which the metal seed layer is formed by using the manner of physical vapor deposition, chemical vapor deposition or electroless plating with the incorporation of catalytic copper, or the electroplating with the incorporation of catalytic copper. Thus, a plating resist layer can be formed to cover the metal seed layer and expose the opening stated above. Finally, a metal barrier layer is formed along the opening surface and is followed by forming solder material inside the opening by electroplating. The plating barrier layer and the metal seed layer under the plating barrier layer are removed so as to complete the electroplated solder on the circuit board.

Description

519859

FIELD OF THE INVENTION: The present invention relates to a method for electroplating solder on an organic circuit board (printed circuit board or substrate). The method is used to form a flip-chip package, and electroplating solder is used to form a flip-chip on a circuit board. Solder between package and circuit board. Background of the Invention: Since 1M Company revealed the flip-chip sealing technology in the early 1960s, flip-chip packaging components have been mainly installed on expensive ceramic plates. Due to the small difference between the thermal expansion bone system and the circuit board, it does not cause obvious problems in use. Compared with the general wire-bonding packaging method, the flip-chip method can provide a higher packaging density (low component outline) and high flexibility (more wire and low inductance). In view of this, the industry has said that the packaging technology has used high-temperature solder on ceramic circuit boards for 40 years: the so-called control chip disassembly connection technology (c〇ntr〇 卜 c〇1Upse chip 1〇n, & gt C4). However, in recent years, under the trend of modern electronic products becoming smaller, faster and cheaper, chip-on-chip devices are embedded in low-cost organic circuit boards and filled with epoxy primer (print, 1 U). Beneath the chip to reduce the inconsistency caused by the thermal stress between the silicon wafer and the structure of the organic circuit j, 6 presents an explosive path and the industry's attention to the use of low-temperature flip-chip soldering and the use of organic circuit boards can enable the industry to achieve low The purpose of cost flip chip packaging. In the general low-cost flip-chip packaging technology, the semiconductor IC chip's fifth, invention description (2) There are several pads on the upper surface & anti-consistent contact windows (c 2 :: twelve organic circuit boards also have Several phases have low-temperature soldering * μ ^ ° and ^, the surface between the wafer and the circuit board is face down and embedded in the circuit board, and the wafer is provided with a fresh material to provide the wafer: circuit board Block or conductive adhesive ^ slZ Electrical output / input between boards and mechanically connected organic underfiU (underfiU) ^ The gap between the board and the circuit board can be filled to reduce the stress of solder joints. This can suppress the incoordination of thermal expansion. And blocks, will be: In order to make the solder joints form flip-chip assembly, the electricity of metal bumps is usually used; ί blocks, gold bumps, or copper bumps, etc., are formed in advance on the crystal ^ u Ν η-surface, where The bumps can be of any shape, such as nails 4¾ Λ & / + spherical bumps, columnar bumps, or other shapes. The corresponding welding name; solder bumps (ρ—) usually use low-alloy zinc tin, also It is formed on the contact pad of the circuit board. At a refl0w temperature, the chip is soldered. The circuit boards are bonded together: after the primer is laid between the wafer and the circuit board, the chip-on-chip component is completed. A typical example of forming a chip-on-chip component by soldering can be shown in Figure 1 to Figure 2B. See Figure-A and the figure show typical examples of the application of metal bumps and pre-solder bumps. The metal bumps 101 are formed on the electrode pads 102 of the wafer 103, and the pre-forms are formed by low-temperature solder. The solder bump 104 is formed on the contact pad 105 of the circuit board 106 as shown in FIG. 1A. Then, the pre-solder bumps 104 are melted and reshaped at a reflow temperature. A solder joint 107 (solder joint) is formed. After laying an underfoil U10 on the gap between the wafer 103 and the circuit board 106, the chip-on-chip device 100

Page 6 519859

V. Description of the invention (3) 焉 Completed, as shown in Figure 1B. Referring again to FIG. 2A and FIG. 2B, this is another typical example of the application of pre-solder bumps. The solder bump 201 is formed on the electrode pad 202 of the wafer 203, and the wafer 203 is bonded to the circuit board 206 at a reflow temperature. At this time, the solder joint 207 is formed on the contact pad 205, as shown in the figure. As shown in two A. Similarly, after laying the primer 208 on the gap between the wafer 203 and the circuit board 206, the flip chip device 200 is completed, as shown in FIG. 2B. Generally speaking, the most common method for forming pre-solder bumps on circuit boards is stencil printing. Some reference materials disclose stencil printing techniques can refer to U.S. Pat. No. 5,203,075 (c / Γ Angulas et al), 5,492,266 (K. G. Hoebener et al) and 5,828,128 (Y. Higashiguchi et al). For flip-chip assembly welding, the choice of bump technology includes dual considerations of bump pitch and size reduction. According to actual experience, when the bump pitch is less than 0.15 mm, the stencil printing method will cause production difficulties, and the electroplating method must be used instead. Known technology about flip-chip packaging to produce plated bumps on circuit boards. See US Pat. No. 5,391,514 (T. P. Gall et al) and (K G Hoebener et al). However, although the distance between the solder bumps produced on the circuit board is better than the stencil printing method by electroforging, there are still some shortcomings in implementation. For example, in the process of solder bumps, the organic insulating protective layer must not be damaged. To avoid affecting product reliability. At the same time, the consistency of plating and bump height must be controlled. These details were not disclosed in U.S. Pat. No. 5,391,514 and 5 4880 835.

Note on page 7 (4) There is a furnace in the present invention. # 方 方 朴 系 on the circuit board provides a way to form electroplated solder in the right ridge; L will not only harm the organic insulating protective layer, ΐ :: Consistency of electrical location. Brief description of the invention of power plating and invention: The main purpose of the present invention is the method of the drawer circuit board, which does not harm the organic insulation and crystal-protecting sealing element and the circuit board or another object of the present invention. The method on the circuit board is the method of layer and fresh tin. Another object of the present invention is a method for a circuit board, which is a seed layer method. Another object of the present invention is a method for a circuit board, which is a seed layer method. Another object of the present invention is to provide electroless plating in which a water-soluble solution of an organic insulating protective layer and a solder is used to reduce the copper and copper. A metal seed layer can be formed by providing an electroplated solder on an organic 5 machine circuit board. A metal seed protective layer is used to form electroplated solder for making soldering between the circuit board and the circuit board. Provided is a method for forming a plated solder on an organic organic circuit board to provide metal plating barriers. Provides a method for forming a plated solder on organic-physical vapor deposition to form metal crystals. Provides a method for forming a plated solder on organic-chemical vapor deposition to form metals. Jingyu provides a method for forming a metal seed layer by electroless plating. The surface of the gadolinium is coated with at least steel ion to form a catalytic copper. Formed electrolessly by catalysis. 519859 V. Description of the invention (5) Yet another object of the present invention is a method for a seed layer, in which A = the metal is formed by electroplating to contain at least steel ions; t the surface of the insulating protective layer and the pad is covered with: copper. Formation-catalyzed formation is assisted by catalytic copper. The first f 溥 metal layer can be formed by electroless plating. And all a ... electrodes, the second thin metal layer can be a thin metal layer. The formed metal seed layer includes a first thin metal layer and a second organic electricity to form an electrical solder. First of all, it is provided on the surface = mounting: fresh organic circuit board between circuit boards is provided with at least one soldered organic circuit board, the surface of the board is covered with -organic insulation protection protective layer, so that the organic insulation protection layer is phase-shaped: "Let's belong to ρ", an opening is formed there; and then 'on the surface of the circuit board = metal seed I, which is a physical vapor deposition, chemical vapor deposition or electroless plating with catalytic steel, or It is formed by the method of electricity ore and catalytic steel, thereby forming a plating resist layer on the metal seed layer, and exposing the opening. Finally, a metal barrier layer is formed on the surface of the substrate, and a fresh tin material is formed by electroplating to remove the electrical resistance layer and the metal seed layer thereunder, and electroplated solder is completed on the circuit board. In order for your reviewers to further understand and approve the purpose, features, and effects of the present invention, the detailed description with the drawings is as follows:

519859 V. Description of the invention (6) Detailed description: In order for your review committee to have a better understanding and approval of the purpose of the present invention and special visits, we hereby assign a person with the characteristics and effectiveness. However, the present invention can be various Pingjia explained later. As described in. The method of implementation is not limited to this specification. The present invention relates to a solder that forms a thunderbolt {say u ^ ^ # γ γ Λ, mesh & wind zinc galvanized tin bumps on an organic circuit board = ΐelectric ore consistent solder The bumps, however, are drawn according to the actual scale, that is, they do not reflect the actual size and characteristics of each level of the chip 1 = in the middle, which will be described first. Please refer to FIG. 3A to FIG. 3F, which are schematic diagrams of a method for electroplating solder on a circuit board according to the first preferred embodiment of the present invention. In a preferred embodiment of the present invention, an organic circuit board 1 having a circuit layout on the surface is first provided, and at least one contact pad 2 is provided on the surface of the organic circuit board 1. Among them, the organic circuit board 1 can be composed of organic materials, fiber-reinf0rced organic materials, or particle-reinforced (particie-reinforced) base materials, such as epoxy resin, polyethyleneamine (P〇iyimide), bismaleimide triazine / based nitrogen resin (bismaleimide triaz ine-based) resin, cyanate ester, p〇lybenzoCyCi〇butane or glass fiber (glass fiber) Composite materials, etc. The contact pad 2 is typically formed of a metal material, such as copper. An organic insulating protective layer 3 (solder mask layer) is deposited on the surface of the circuit board 1 to protect the circuit layout and provide insulation, and then the organic insulating protective layer 3 is added.

Page 10 519859 V. Description of the invention (7) ′ The pattern is formed so that the organic insulating protective layer 3 forms an opening 6 at a position corresponding to the contact pad 2, as shown in FIG. 3 a. Secondly, a solder bump is formed by electroplating on a non-conductive surface. Before electroplating, a conductive seed layer must be formed on the non-conductive surface. In the general circuit board industry, the seed layer is often Electroplating is formed. In this process, the surface must be immersed in a chemical solution to form a catalytic surface (ie, a sensitizer (sensiUzer), vaporized tin, titanium chloride, etc .; and an activat. r), such as acidified gasified palladium, acidified gold chloride, acidified silver chloride, etc., and then immersed in the helmet plating solution to form a conductive seed layer. With this seed layer, metal bumps can be formed by electroplating. However, there are still some disadvantages to forming a seed layer on an organic circuit board by electroless plating. One is that the organic circuit board is exposed to a chemical solution, that is, a sensitizer solution, an activator solution, and an electroless plating solution, which will result in An insulating protective layer is eroded, which reduces the reliability of the circuit board. The second is that the sensitizer solution and the activator solution usually contain a large amount of chloride ions, which easily penetrate the organic protective layer, and are in the immersion step. After that, it will stay in the protective layer, which will easily reduce the reliability of the circuit board. Another problem is that inert metals, that is, palladium, gold, and silver, usually play the role of a catalytic metal on the surface of non-conductors. Therefore, it is difficult to remove from the surface of the protective layer, and it is easy to form a residue on the surface; at the same time, etching the inert metal also easily hurts the organic protective layer. In this case, the reliability of the organic circuit board becomes a problem. In order to avoid the above-mentioned problem of damaging the organic protective layer, the present invention provides a method for forming a metal seed layer without immersing the circuit board in the substrate.

Page 11 519859 V. Description of the invention (8) In solution. The invention uses a metal layer as a seed layer, and uses physical deposition or chemical physical vapor deposition, such as sputtering, evaporation, arc vapor deposition, and ion beam. A metal layer is formed on the surface of the organic circuit board by sputtering, laser ablation deposition, plasma enhanced CVD, and metallorganic CVD. The following is a process of forming a plated solder bump on an organic circuit board by using the seed layer. Referring to FIG. 3B, the surface shape of FIG. 3a is covered with a metal seed layer 4 on the organic circuit board through the method steps described above. Then, a mineral resistance layer 5 (which may be an organic resistance material) is deposited and covered on the metal seed crystal :, and the opening 6 is exposed. As shown in FIG. 3 ^, the system is: a metal barrier layer 7 is formed on the surface of the port 6. The metal barrier layer? Often the second adhesive layer and a protective layer of gold. Then ^), kick (Sn), network ~ (Cr / T ", antimony ^ (two) ... gen, electricity Λ Γ Γ / record / handle / gold (Ni / Pd / Au), etc., it can be "(electr 〇Plating), electroless ore (elec-type filling-soldering please open in this two-party type: drawing .: Then ... ^ In addition to the removal of the electroplating resist layer 5 mentioned above and electricity such as: resistance two two Then, the layer 4 is shifted, as shown in FIG. 3E. Finally, the first, second, and lower metal seed solder material 8 is formed to form f ^ # Q, which melts and reshapes the I into cup tin at a temperature of 烊. The bump 9 is on the contact pad 2, as shown in FIG. 30.

519859

The metal barrier layer 7 described in at least the examples can be the following and the metal 3 is a seed layer: can be made of gold, nickel, nickel? , Steel, cobalt and Ming. It is composed of steel, aluminum alloy, or multilayer metal (bimetallic sound, chrome copper alloy, lead-tin alloy, tin / copper system such as gold: i: r, v chromium / ... gold / steel Wait, however inert gold

Sr seed layer 4, because in _ shift: this heart /;. And ίί :: The preferred thickness of the metal seed layer 4 lies in. .1 mm: Lead, tin, ΪΓ, preferably an alloy of the following metals: etc. After re-soldering di-bismuth, antimony, zinc, nickel, aluminum, manganese, indium, tellurium, and gallium, it can be removed and dissolved in a cleaning step, such as ultrasound, clear seed crystals: column 'Λ metal crystal The seed layer 4 is preferably thinner. Because of the thin metal, the layer 4 can be removed relatively quickly in the etching solution, which makes ^ t ^ ^ M ^ t Λ and the solder material 8 祜 舳 Zhao, masterpiece & a < — π wind, edge 4 floors and 3 walls. The degree of damage will be reduced to an acceptable level 2. During the reflow process, when the metal seed layer 4 (such as = ^ is embedded in the solder material 8, the fresh tin = gold, and the thinner metal The seed layer 4 will have less kick; :: tin :: bump 9; therefore, in this case, the solder bump 9 :: = = easy. = More. In practical terms, the metal crystal The second choice is best in the case of Dongshi 005. The composition of the etching solution is also selected; and the metallography (metal 10graphy) technical book shows that

519859 Fifth, the invention description (ίο) is, such as, Metal lographic etching'1, Gunter Petzow, American Society for Metals, Metals Park, Ohio, (1978). The metal seed layer 4 can also be formed by electroless plating or electroplating. The catalytic metal does not use an inert metal, but uses copper as the catalytic metal. An example of the formation of catalytic copper on a typical non-conductive surface, in U. s. Pat ·

No. 3,993,491 and 3,993,848 are disclosed. By means of the catalytic copper surface, the metal seed layer 4 can be formed by electroless plating. Of course, the metal seed layer 4 can also be formed by electroplating after a short period of electroless plating. At the beginning, catalytic copper is formed on a non-conductive surface, and then a first thin metal layer is formed on the catalytic copper by electroplating. Then, a second thin metal layer is formed on the first thin metal layer, so the metal seed layer 4 includes a first and a second thin metal layer. In addition, the damage of the organic insulating protective layer 3 can also be reduced, because the catalytic copper (non-inert metal) can be easily removed from the etching solution. Through the above electroless plating or electroplating process, the solder bump 9 can be formed on the organic circuit board 1. The organic insulating protective layer 3 is not limited to cover the surface of the contact pad 2 in part. Referring to FIG. 4a, the organic insulating protection layer 3 is deposited on the surface of the organic circuit board 1a, but does not cover any part of the surface of the contact pad 2a. The metal seed layer 4a and the plating resist layer 5a having an opening 6 & are completed, the metal barrier layer 7a is formed along the surface of the opening 6a, and then a plating solder material ga is formed in the opening 6a. After the plating resist layer 5a and the metal seed layer 4a are removed, the solder bump 9a can be completed in a reflow process. However, due to the dissolution of the metal seed layer 4a in the solder bump

Page 14 519859 V. Description of the invention (11) There are also two different phenomena in the same degree .... In terms of lower melting, the metal seed layer 4a will still exist after the reflow process. As shown in FIG. 4B, relatively speaking, in terms of higher melting, the metal seed layer 4a will disappear after the reflow process, as shown in FIG. 4c. The contact pads 2 are not limited to any shape and size. As shown in the figure, the top three circuit layers 11 of the organic circuit board 1b are shown. The surface of the contact pad 2b and the surface of the insulating layer 12 are in the same layer, and an organic insulating protective layer 3b is formed and patterned with a lion. The vertical circuit line 13 is completed by a so-called stacked via (stacked via) technology. The solder bump 91) is formed on the contact pad "as shown in Fig. 5-6. In addition, the invention has the following advantages in forming electroplated solder on an organic circuit board: This :: Forms a solder :: organic protective layer on an organic circuit board, and can provide a power bump A: One (2) The present invention provides a method for forming a metal seed layer

The board is immersed in a chemical solution to reduce the circuit board. It is not necessary to make the circuit as described above. The invention provides a high process Q and the cost is very low. The mass production and the high efficiency are rich in implementation. Elements of the invention patent stipulated in the New Invention Law = show the purpose of the invention and the use price of the industry. Therefore, Yuma no Yuma, this invention has been in line with the patent, please 'respect your process difficulties and yield loss Etc. are missing, and the present invention uses jms9 five invention descriptions (12) Examines Tailu—the person will review it, and grant the patent as a prayer. The half of the board uses the above description to form the electroplated solder on the organic circuit only for the present invention. Any preferred embodiment of ^ 1 is not intended to limit the implementation of the present invention, and those skilled in the art will not violate it. The amendment made by the spirit of the present invention should belong to the scope of the present invention, so the protection scope of the present invention should be based on the scope of patent application described below.

Page 16 519859 Brief description of the diagrams Brief explanation of the diagrams: Figures 1A and 1B are schematic diagrams of the conventional application of metal bumps and pre-solder bumps. Fig. 2A and Fig. 2B are schematic diagrams showing another conventional structure for applying solder bumps. Figures 3A to 3F are schematic diagrams of a method for plating solder on a circuit board according to the first preferred embodiment of the present invention. Figures 4A to 4C are schematic diagrams of a method for electroplating solder on a circuit board according to a second preferred embodiment of the present invention. Figures 5A to 5B are schematic diagrams of a method for plating solder on a circuit board according to a third preferred embodiment of the present invention. Description of drawing number: 1 0 0, 2 0 0 ~ flip chip device 1 (Π ~ metal bump 2 0 1 ~ tin recording bump 1 0 2, 2 0 2 ~ electrode pad 103, 203 ~ wafer 1 0 4 ~ Pre-soldering bumps 105, 205 to pads 106, 206 to circuit boards 1 0 7, 2 G 7 to solder joints 108, 208 to primers 1, 1 a, 1 b to organic circuit boards

Page 519859 Brief description of the drawings 11 ~ Circuit layer 1 2 ~ Insulation layer 1 3 ~ Circuit line 2, 2a, 2b ~ Contact pad 3, 3a, 3b ~ Organic insulation protection layer 4, 4a ~ Metal seed layer 5 5a ~ plating resist layer 6, 6a ~ opening 7, 7a ~ barrier layer

8, 8 a ~ tin recording material 9, 9a, 9b ~ solder bump

Page 18

Claims (1)

519859 Method on a circuit board, the steps include An electroplated solder formed on an organic substrate includes: (a) an organic circuit board provided on the surface with a thunderbolt # Γ layout, which is provided with at least a contact pad; and the organic circuit board is covered with organic insulation protection. C. The organic insulating protective layer is formed, so that the organic insulating protective layer forms an opening at a corresponding pad. (D) A metal seed layer is covered with the surface shape of the step (c) above. (E) forming a plating resist layer overlying the metal seed layer and exposing the opening; (f) forming a metal barrier layer along the surface of the opening; (g) filling with a power ore method Insert a solder material into the opening; (h) remove the plating resist layer and the metal seed layer under the plating resist layer. 2. The method for forming electroplated solder on an organic circuit board according to item 1 of the scope of the patent application, wherein the material of the metal seed layer is copper, tin, oblique tin alloy or tin / copper bimetal layer. 3. The method for forming an electroplated solder on an organic circuit board according to item 1 of the scope of the patent application, wherein the thickness of the metal seed layer is below 0. 0 1 mm. 4. The method for forming electroplated solder on an organic circuit board according to item 1 of the scope of the patent application, wherein the metal B seed layer includes at least one thin metal layer. Page 19, 519859 VI. Application for Patent Scope 5 · Affirming the method of forming electroplated fresh tin on organic circuits as described in item 丨 of the patent, 'wherein this step: it is covered with the metal seed layer by physical vapor deposition method . 6. ^ Declaration of the special rules for the formation of electric ore fresh tin in organic circuits described in ^: ^ t: f η wherein step (d) is a step of coating the metal seed layer with a chemical vapor deposition method. 7 ^ The method of forming electroplated solder on organic circuits as described in item 1 of Liganwei, wherein this step is a method of forming electroplated fresh tin on organic circuit boards as described in item ΙΙΪίΠ! Wherein, step (d) is to coat the metal crystal with electrless plating ^ 9 The metal barrier layer described in ^ m described in item 丨 of the patent application range may be at least- Superposition of various metals: gold, nickel, titanium, copper, hafnium "to-10 · The method for forming a solder plate as described in item i of the patent application scope, in which the solder material, Alloys composed of alloys: copper, tin, silver, steel, alloys, alloys, indium, tellurium, and thallium. Record, resign, record,