CN102148211A - 半导体组件、半导体元件及其制法 - Google Patents

半导体组件、半导体元件及其制法 Download PDF

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Publication number
CN102148211A
CN102148211A CN2010102133584A CN201010213358A CN102148211A CN 102148211 A CN102148211 A CN 102148211A CN 2010102133584 A CN2010102133584 A CN 2010102133584A CN 201010213358 A CN201010213358 A CN 201010213358A CN 102148211 A CN102148211 A CN 102148211A
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layer
base material
semiconductor
copper
lead
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CN102148211B (zh
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赖怡仁
韩至刚
詹前彬
简智源
杨怀德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件、半导体组件及半导体元件的形成方法，半导体元件包括一半导体基材；一焊盘区域，位于该半导体基材上；以及一凸块结构，位于该焊盘区域之上且电性连接该焊盘区域。凸块结构包括铜层与位于铜层上的无铅焊料层。无铅焊料层为锡银合金层，且于锡银合金层中的银含量小于1.6重量百分比。当无铅凸块中的银含量较低时，凸块硬度会随之降低。较软的凸块可以消除由于热应力所引起的裂缝问题。

Description

半导体组件、半导体元件及其制法
技术领域
本发明涉及无铅焊料层(lead-free solder)，且特别涉及一种使用无铅焊料层的半导体元件与半导体组件(assembly)。
背景技术
现今的集成电路是由实质上数百万个有源元件所组成，其中有源元件例如晶体管与电容。这些元件初始彼此绝缘，但通过后续连接该些元件，以形成一功能性电路。典型的内连线结沟包括水平(latemal)内连线结构(例如金属线)与垂直内连线(例如导通孔(vias)与接触插塞(contacts))。对现今集成电路(IC)而言，内连线结构对于其性能与密度的极限的影响日益重要。接合焊盘(bond pad)会形成于内连线结构的最上层，并暴露于相对应芯片的表面上。通过接合焊盘将芯片电性连接到封装基材或另一裸片上。接合焊盘也使用于打线接合(wire bonding)与倒装芯片接合(flip-chip bonding)。晶片级芯片尺寸封装(wafer level chip scale packaging，WLCSP)是目前广泛被使用的一种封装方法，其成本低且工艺简单。于一般的晶片级芯片尺寸封装(WLCSP)中，内连线结构形成于金属层之上，接着形成凸块底层金属(under-bump metallurgy，UBM)与焊料球(solder ball)。
倒装芯片封装(flip-chip packaging)会利用凸块电性连接芯片输入/输出焊盘(I/O pad)与基材或封装的导线架(lead frame)。就结构上而言，凸块实质上包括凸块本身与介于凸块与输入/输出焊盘(I/O pad)之间的凸块底层金属(under-bump metallurgy，UBM)。一凸块底层金属(UBM)一般会包括粘着层(adhesion layer)、阻挡层(barrier layer)与湿润层(wetting layer)，并依此顺序排列于输入/输出焊盘(I/O pad)上。凸块依据自身材料的不同，区分成焊料凸块(solder bump)、金凸块(gold bump)、铜柱凸块(copper pillar bumps)与具有混合金属的凸块。近年来，内连线铜柱技术(copper interconnect post technology)被提出，取代焊料凸块的使用，电子元件通过铜柱(copper post)连接到基材上。内连线铜柱技术(copper interconnect post technology)因其凸块桥接的可能性最小而可达到较细的间距(finer pitch)，对于电路可降低电容承载(capacitanceload)，且可于高频下操作电子元件。然而，仍然需要焊料合金(solder alloy)盖住凸块结构与接合用的电子元件。
一般而言，焊料合金的材料即是所谓的锡-38质量％铅(Sn-38mass％Pb)的锡铅共晶焊料(Sn-Pb eutectic solder)。最近几年，实际应用亟需使用无铅焊料(Pb-free solder)。以二元锡银合金(binary Sn-Ag alloy)作为无铅焊料，其具有2.0～4.5重量％的银，其熔点为约240～260℃。对于无铅元件的回焊工艺(reflow soldering process)与设备皆与公知的共晶焊料类似。为了使用共熔点(eutectic point)以避免热伤害，焊料合金的发展纷纷朝向使合金的成分尽量接近合金的共晶组成。然而，无铅焊料材料的熔点(melting point)高于公知的锡铅共晶焊料，因此，当TCB测试时，会产生裂缝(crack)与应力(stress)可靠度的问题，特别对于大尺寸裸片而言，此问题更为严重。即使应用内连线铜柱技术(copper interconnect post technology)，使用无铅焊料材料作为倒装芯片组合(flip-chip assembly)的盖层(cap)，由于裸片边缘/基材介面的应力，仍然会引起裂缝(crack)的问题。
发明内容
为了克服现有技术中的上述缺陷，本发明提供一种半导体元件，包括：一半导体基材；一焊盘区域(pad region)，位于该半导体基材上；以及一凸块结构(bump structure)，位于该焊盘区域之上且电性连接该焊盘区域，其中该凸块结构包括一铜层与位于该铜层之上的一锡银合金层(SnAg layer)，且该锡银合金层(SnAg layer)中的银含量小于1.6重量百分比。
本发明另提供一种半导体组件(assembly)，包括：一第一基材；一第二基材；以及一接合结构(joint structure)设置于该第一基材与该第二基材之间；其中该接合结构包括介于该第一基材与该第二基材之间的一凸块结构，与介于该凸块结构与该第二基材之间的一焊料层(solder layer)；以及其中该焊料层包括银(silver，Ag)，且该焊料层中的银含量小于3.0重量百分比。
本发明也提供一种半导体元件的形成方法，包括以下步骤：提供一半导体基材；形成一焊盘区域(pad region)位于该半导体基材之上；形成一铜柱(copper post)位于该焊盘区域之上；形成一无铅焊料层(lead-free solder layer)位于该铜柱之上，其中该无铅焊料层包括银，且银含量小于1.6重量百分比；以及于温度240℃-280℃之间回焊(reflow)该无铅焊料层。
当无铅凸块中的银含量较低时，凸块硬度会随之降低。较软的凸块可以消除由于热应力所引起的裂缝问题。扫描式电子显微镜(SEM)的数据显示具有银含量较低的无铅凸块较能避免裂缝问题。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，进行详细说明。
附图说明
图1为一剖面图，用以说明本发明一半导体元件的实施例，其中半导体元件具有无铅焊料位于铜柱结构之上。
图2为一关系图，用以说明本发明无铅焊料中的银含量与凸块硬度的关系。
图3A～图3B为一系列剖面图，用以说明本发明具有无铅焊料的封装组件(package assembly)的实施例。
图4为一剖面图，用以说明对于晶片级芯片尺寸封装(WLCSP)，本发明的铜柱结构位于铜制保护层后内连线(Cu PPI)上的实施例。
图5为一剖面图，用以说明焊料凸块结构的实施例。
图6为一剖面图，用以说明具有焊料凸块结构的封装组件。
图7为一剖面图，用以说明对于晶片级芯片尺寸封装(WLCSP)，本发明的焊料凸块结构位于铜制保护层后内连线(Cu PPI)上的实施例。
图8A～图8C为一系列剖面图，用以说明使用无铅焊料制作垂直堆叠元件的实施例。
其中，附图标记说明如下：
10～基材
12～导电区域
14～保护层
15～开口
16～凸块底层金属(UBM)
16a～扩散阻挡层
16b～籽晶层
18、18a～铜柱(copper post)
20、20a～盖层
22、22a～无铅焊料层(lead-free solder layer)
24～保护层
25～凸块结构
25a～焊料凸块结构
26～保护层后内连线(PPI line)
100～基材
102～连接结构
104～接触焊盘
106～前焊料层
108～接合焊料结构
200～晶片
210～基材
210”～薄化基材
210a～第一表面
210b～第二表面
210b”～薄化基材的第二表面
214～第一介电层
216～导通孔
216a～导通孔的末端
218～第一内连线结构
220～保护层
222～金属焊盘
224～介电缓冲层
226～凸块结构
228～第二内连线结构
300～载板
302～粘着层
400～裸片
402～凸块结构
404～铜层
406～盖层
408～无铅焊料层
500～裸片对晶片(die-to-wafer)堆叠
502～接合结构
具体实施方式
本发明提供一种控制银含量与回焊(reflow)温度的无铅焊料(lead-freesolder)，其使用于具有铜柱(copper post)、保护层后内连线(post passivationinterconnects)、焊料凸块、及/或硅导通孔(through-silicon vias，TSVs)形成于其中的半导体元件，且可应用于倒装芯片组合(flip-chip assembly)、晶片级芯片尺寸封装(wafer level chip scale packaging，WLCSP)、三维集成电路堆叠(3D-IC stack)、及/或先进的封装技术领域中。于后续的叙述中，会详述特定的细节以充分了解本发明。然而，本领域普通技术人员应能了解的是，不需要特定的细节也能实行本发明。于一些实施例中，不再详述已知的结构与工艺，以避免混淆本发明。说明书中提及的“一实施例”意指与此实施例相关的特定的结构特征、结构或特性包括于至少一实施例中。因此，于各处出现的“一实施例”一词，并非意指相同的实施例。再者，特定的结构特征、结构或特性可以以适合的方式结合于一或多个实施例中。须注意的是，下述附图并非依据实际比例绘制，这些附图仅用于举例说明使用。
此处，图1显示一半导体元件于铜柱结构(copper post structure)之上具有无铅焊料的实施例。
使用于铜柱内连线工艺的基材10的例子，可包括应用于半导体集成电路工艺的一半导体基材与形成于其中及/或之上的集成电路。半导体基材意指任何包括半导体材料的结构，包括，但不限于，块状硅(bulk silicon)、半导体晶片(semiconductor wafer)、绝缘层上覆硅基材(silicon-on-insulator，SOI)或硅锗(silicon germanium)基材。也可使用包括IIIA族、IVA族、VA族元素的其他半导体材料。此处所谓的集成电路意指电子电路具有多种独立的电路元件，例如晶体管(transistors)、二极管(diodes)、电阻器(resistors)、电容(capacitors)、电感(inductors)及其他有源与无源半导体元件。基材10尚包括层间介电层(inter-layer dielectric layers)与金属结构(metallization structure)位于集成电路之上。于金属结构之中的层间介电层包括低介电常数(low-k)介电材料、未掺杂的硅酸盐玻璃(un-doped sislicate glass，USG)、氮化硅、氮氧化硅、或其他常用的材料。低介电常数(low-k)介电材料的介电常数值(k值)小于约3.9，或小于约2.8。于金属结构之中的金属线可由铜或铜合金所组成。本领域普通技术人员应能了解金属层的形成细节。
导电区域12是形成于最上层间介电层(top-level inter-layer dielectric layer)之中的顶部金属层，其为导电线路的一部分，且通过一平坦化工艺(例如化学机械研磨工艺(chemical mechanical polishing，CMP))处理后具有一暴露的表面。适合用于导电区域12的材料可包括，但不限于，例如铜、铝、铜合金或其他通信导电材料(mobile conductive materials)。于一实施例中，导电区域12为一焊盘区域12，其使用于接合工艺(bonding process)，以将各自芯片中的集成电路连接到外部结构特征。
形成保护层14于基材10之上并图案化之，以部分覆盖焊盘区域12。保护层14具有一开口15，借以暴露焊盘区域12的一部分。保护层14由非有机材料所组成，包括未掺杂的硅酸盐玻璃(un-doped silicate glass，USG)、氮化硅、氮氧化硅、氧化硅或上述的组合。另外，保护层14也可由高分子层所组成，例如环氧树脂(epoxy)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzoxazole，PBO)或类似材料。也可使用其他相对较软的材料，通常是有机或介电材料。
一凸块底层金属(under-bump-metallurgy，UBM)层16包括一扩散阻挡层16a与一籽晶层16b形成于保护层14的一部分上，且通过开口15电性连接到焊盘区域12。如图中所示，凸块底层金属(UBM)层16直接接触焊盘区域12暴露的部分，且衬垫于(lines)开口15的侧壁与底部间。扩散阻挡层16a也称为胶着层(glue layer)，其用以覆盖开口15的侧壁与底部。扩散阻挡层16a可由氮化钽(tantalum nitride)所组成，也可由其他材料所组成，例如氮化钛(titanium nitride)、钽(tantalum)、钛(titanium)或类似的材料。形成的方法包括物理气相沉积法或溅镀。籽晶层16b可以是形成于扩散阻挡层16a之上的铜籽晶层。籽晶层16b可以由铜合金所组成，铜合金中包括银(silver)、铬(chromium)、镍(nickel)、锡(tin)、金(gold)或上述的组合。于一实施例中，凸块底层金属(UBM)层16为一铜/钛(Cu/Ti)层。
铜柱(copper post)18形成于凸块底层金属(UBM)层16之上。如说明书中所述“铜柱(copper post)”意指实质存在的粘贴层(post)，其包括纯元素铜、含有无可避免不纯物的铜、或含少量其他元素的铜合金，其他元素包括钽(tantalum)、铟(indium)、锡(tin)、锌(zinc)、锰(manganese)、铬(chromium)、钛(titanium)、锗(germanium)、锶(strontium)、铂(platinum)、镁(magnesium)、铝(aluminum)或锆(zirconium)。形成的方法包括溅镀(sputtering)、印刷(printing)、电镀(electro plating)、无电镀(electroless plating)与一般常使用的化学气相沉积法(chemical vapor deposition，CVD)。例如，进行电化学电镀(electro-chemcial plating，ECP)以形成厚度大于40μm的铜柱。于其他实施例中，铜柱的厚度为约40-70μm，其厚度也可以更大或更小。
盖层(cap layer)20形成于铜柱18的上表面。盖层20可作为一阻挡层，用以避免铜柱18中的铜扩散到接合材料中，其中接合材料(例如焊料合金)用以接合基材10到外部结构特征。铜扩散的避免可以增加封装的可靠度与接合强度。盖层20可包括镍(nickel)、锡(tin)、锡铅合金(tin-lead，SnPb)、金(gold，Au)、银(silver)、钯(palladium，Pd)、铟(In)、镍钯金合金(nickel-palladium-gold，NiPdAu)、镍金合金(nickel-gold，NiAu)或其他类似的材料或合金。于一实施例中，盖层20为厚度约1-5μm的镍层。
无铅焊料层(lead-free solder layer)22形成于盖层20之上。因此，无铅焊料层22、盖层20与铜柱18形成于焊盘区域12之上，合称为凸块结构25。无铅焊料层22可通过电镀与回焊工艺形成。于一实施例中，无铅焊料层22为焊料球状(solder ball)，形成于盖层20之上。于另一实施例中，无铅焊料层22为一电镀锡层，位于盖层20之上。对于无铅焊料层系统而言，焊料层22是锡银合金(SnAg alloy)，其中银含量控制在低于1.6重量百分比。于回焊工艺中，调整无铅焊料层22的熔点为约240℃～280℃。于一实施例中，无铅焊料层22的银含量为约1.2重量百分比-约1.6重量百分比。于另一实施例中，无铅焊料层22的银含量为约1.5重量百分比。使用无铅焊料合金的封装工艺的可靠度与下列因素相关，包括：凸块硬度、金属间化合物(intermetalliccompounds，IMCs)以及孔洞(voids)的形成有关，这些因素可能会于焊料接点(solder joint)上造成裂缝或造成热-机械应力。如图2所示，当无铅凸块中的银含量较低时，凸块硬度会随之降低。较软的凸块可以消除由于热应力所引起的裂缝问题。扫描式电子显微镜(SEM)的数据显示具有银含量较低的无铅凸块较能避免裂缝问题。相反的，当无铅凸块中的银含量增加时，在一开始就会观察到金属间化合物(intermetallic compounds，IMCs)、孔洞(voids)与裂缝的形成。然而，于回焊工艺的冷却步骤期间，如果无铅凸块中的银含量降到1.2重量百分比时，只有一部分的焊料凸块会从熔融态变成固态，因此，热应力会集中于这些凸块而造成裂缝。关于无铅焊料层22于回焊工艺时的回焊温度，调整为约240℃～280℃，不但可避免形成不完整的球型，且能抑制金属间化合物(IMCs)与孔洞(voids)的产生。
图3A与图3B为一系列剖面图，其用以叙述具有无铅焊料的封装组合的示范实施例。
基材10可被割开并封装至一封装基材、或另一裸片、或具有焊料球(solder ball)或铜柱(copper post)粘着于结合焊盘上的封装基材或裸片。图1的结构反转向下且附着到位于底部的另一基材100。基材100可以是一封装基材、基板(例如印刷电路板(print circuit board，PCB))或另一合适的基材。连接结构102利用各种导电粘着点(conductive attachment points)接触基材100，例如，位于接触焊盘104及/或导电线(conductive trace)上的前-焊料层(pre-solder layer)106。前-焊料层(pre-solder layer)106可以是共晶焊料材料(eutectic solder material)，其包括锡(tin)、铅(lead)、银(silver)、铜(copper)、镍(nickel)、铋(bismuth)或上述组合的合金。使用一系列耦合工艺(couplingprocess)，包括助焊剂应用(flux application)、芯片置换(chip replacement)、焊料接点的回焊(reflowing ofmelting solderjoints)与残余助焊剂的清洁(cleaningof flux residue)等，使接合焊料结构(joint-solder structure)108形成于基材10与基材100之间。于组合工艺之后，接合焊料结构(joint-solder structure)108包含混合前-焊料层(pre-solder layer)106的无铅焊料，其中接合焊料结构108的银含量小于3.0重量百分比。基材10、接合焊料层(joint-solder layer)108与另一基材100合称为封装组合(packaging assembly)，或于本实施例中称为倒装芯片组合(flip-chip assembly)。
对于晶片级芯片尺寸封装(wafer level chip scale packaging，WLCSP)的应用，图4显示铜柱结构位于保护层后内连线(post pasivation interconnect line，PPI line)26之上的示范实施例的剖面图，其中与图1～图3相同或类似的部分在此不再赘述。
图1中铜柱18与凸块底层金属层(UBM layer)16形成于焊盘区域12之上，与图1相比，晶片级芯片尺寸封装(WLCSP)工艺形成一保护层后内连线(PPI line)26位于凸块底层金属层16与保护层14之下，与位于另一保护层24之上。保护层后内连线(PPI line)26的一末端电性连接至焊盘区域12(未显示于图4中)，而另一末端电性连接至凸块底层金属层16与铜柱18。于一实施例中，于保护层14中暴露保护层后内连线(PPI line)26，而凸块底层金属层16直接形成于暴露的位置上。保护层24可由非有机材料所组成，包括未掺杂的硅酸盐玻璃(un-doped silicate glass，USG)、氮化硅(silicon nitride)、氮氧化硅(silicon oxynitride)、氧化硅(silicon oxide)或上述的组合。另外，保护层24也可由高分子层所组成，例如环氧树脂(epoxy)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzoxazole，PBO)或类似材料。也可使用其他相对较软的材料，通常是有机或介电材料。保护层后内连线(PPI line)26可包括，但不限于，例如铜、铝、铜合金或其他可通信导电材料(mobile conductive material)。保护层后内连线(PPI line)26尚可包括一含镍层(图中未显示)于一顶部含铜层上。保护层后内连线(PPI line)26形成的方法包括电镀(electro plating)、无电镀(electroless plating)、溅镀(sputtering)、化学气相沉积法(chemical vapor deposition，CVD)或类似的方法。保护层后内连线(PPI line)26也可作为电源线(power lines)、重新分布线(re-distribution lines，RDL)、电感(inductors)、电容(capacitors)或任何无源元件。保护层后内连线(PPIline)26的厚度为小于约30μm，例如为约2μm～25μm。
图5显示一焊料凸块结构的实施例的剖面图，其中与图1～图3相同或类似的部分在此不再赘述。
与图1相比，铜柱18被薄铜层18a所取代，于焊料凸块工艺中接着形成盖层20a与无铅焊料层22a。薄铜层18a的厚度相对小于铜柱18。薄铜层18a的厚度为小于10μm。于一实施例中，薄铜层18a的厚度为约1～10μm，例如为约4～6μm，其厚度也可以更大或更小。薄铜层18a的形成方法包括溅镀(sputtering)、印刷(printing)、电镀(electro plating)、无电镀(electrolessplating)、与一般常使用的化学气相沉积法(chemical vapor deposition，CVD)。无铅焊料层22a被回焊作为焊料球。因此，无铅焊料层22a、盖层20a与铜层18a合称为一焊料凸块结构25a。焊料层22a是锡银合金(SnAg alloy)，其中银含量控制在低于1.6重量百分比，其熔点为约240℃～280℃。于一实施例中，无铅焊料层22a的银含量为约1.2重量百分比-约1.6重量百分比。于另一实施例中，无铅焊料层22a的银含量为约1.5重量百分比。
图6显示图5半导体元件的封装组件的实施例的剖面图，其中与图1～图3相同或类似的部分在此不再赘述。于组合工艺之后，基材10、接合焊料层108与另一基材100可合称为一封装组件，或于本实施例中，称为倒装芯片组件(flip-chip assembly)。接合焊料层108包括混合前焊料的无铅焊料，其中接合焊料层108的银含量小于3.0重量百分比。
对于晶片级芯片尺寸封装(wafer level chip scale packaging，WLCSP)的应用，图7显示焊料凸块结构位于铜制保护层后内连线(Cu PPI)之上的示范实施例的剖面图，其中与图1～图6相同或类似的部分在此不再赘述。与图5相比，晶片级芯片尺寸封装(WLCSP)工艺形成一保护层后内连线(PPI line)26位于凸块底层金属层16与保护层14之下，与位于另一保护层24之上。保护层后内连线(PPI line)26的一末端电性连接至焊盘区域12(未显示于图7中)，而另一末端电性连接至凸块底层金属层16。于一实施例中，于保护层14中暴露保护层后内连线(PPI line)26，而凸块底层金属层16直接形成于暴露的位置上。
图8A～图8C显示使用无铅焊料制作垂直堆叠元件的实施例的剖面图。长期以来(long-awaited goal)，三维(3D)晶片对晶片(wafer-to-wafer)、裸片对晶片(die-to-wafer)、或裸片对裸片(die-to-die)垂直堆叠技术的目标在于，垂直堆叠很多层有源元件(例如处理器(processors)、可编程元件(programmabledevices)与存储器元件(memory devices))，以缩短平均线长(average wirelengths)，进而减少内连线RC延迟(RC delay)并增加系统的性能表现。三维(3D)内连线于单一晶片或于裸片对晶片垂直堆叠的主要挑战在于，如何制造好的硅导通孔(through-silicon via，TSV)，此硅导通孔提供一信号路径，使高阻抗信号从晶片的一侧穿过另一侧。一般制备硅导通孔(through-silicon via，TSV)的目的在于，使填满导电材料的硅导通孔能完全地穿过所在的该层，并连接与接触另一接合层的硅导通孔与导体。
请参见图8A，提供一晶片200，其包括一基材210。基材210的实施例可包括应用于半导体集成电路工艺的一半导体基材与形成于其中及/或之上的集成电路。基材210具有第一表面210a与相对于第一表面210a的第二表面210b。第一表面210a可以作为前侧(frontside)，且位于集成电路之上，其中集成电路包括形成有源与无源元件(例如晶体管、电阻器、电容、二极管、电感或类似的元件)，这些元件用以连接接合焊盘(bond pads)及/或其他内连线结构(interconnection structures)。电路可以是任何适用于特殊应用的电路。功能可包括存储器结构(memory structures)、工艺结构(process structures)、传感器(sensors)、放大器(amplifiers)、配电系统(power distribution)、输入/输出电路(input/output circuitry)或类似的结构。第二表面210b作为后侧(backside)，其将会被薄化与工艺化以形成接合焊盘及/或其他内连线结构于其中。
第一介电层214形成于第一表面210a，其中形成接触插塞(contacts)以电性连接至各自的元件。一般而言，第一介电材料214可由，例如低介电常数(loW-k)介电材料、氧化硅(silicon oxide)、硅磷酸盐玻璃(phosphosilicate glass，PSG)、硼磷酸盐玻璃(borophosphosilicate glass，BPSG)、氟酸化硅酸盐玻璃(fluorinated silicate glass，FSG)、或类似的材料所组成，由本领域所熟知的适合的方法所形成。也可使用其他材料或其他工艺。
多个导通孔(through vias)216穿过至少一部分基材210。导通孔216是一种填充导体的插塞(conductor-filled plug)，其从第一表面210a延伸到第二表面210b，且达到预定的深度(intended depth)。此外，一绝缘层形成于导通孔216的侧壁与底部，且导通孔216与基材210绝缘。导通孔216可由任何合适的导电材料所组成，优选由高导电、低电阻金属、元素金属、过渡金属(transition metal)或类似的材料所组成。于一实施例中，导通孔216为沟槽填充由铜(Cu)、钨(W)、铜合金(Cu alloy)或类似的材料所组成的导电层。由钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或上述的组合所组成的导电阻挡层(conductive barrier layer)形成于沟槽中且围绕导电层。绝缘层由一般使用的介电材料所组成，例如氮化硅、氧化硅(例如四乙氧基硅酸盐(tetra-ethyl-ortho-silicate oxide，TEOS))或类似的材料。
第一内连线结构218包括金属间介电层、位于集成电路上的金属层(metallization structure)、第一介电层214与导通孔216。位于金属层之中的金属间介电层包括低介电常数(low-k)介电材料、未掺杂的硅酸盐玻璃(un-doped silicate glass，USG)、氮化硅(silicon nitride)、氮氧化硅(siliconoxynitride)或其他一般常使用的材料。低介电常数(low-k)介电材料的介电常数值(k)可小于约3.9，或小于约2.8。金属层包括金属线与导通孔，其可由铜或铜合金所组成，且可利用已知的镶嵌工艺(damascene processes)形成。本领域普通技术人员应能了解金属层的形成细节。
保护层220形成于第一内连线结构218之上。保护层220由例如氧化硅、氮化硅、未掺杂的硅酸盐玻璃(un-doped silicate glass，USG)、聚亚酰胺(polyimide)、及/或上述的多层结构所组成。金属焊盘(metal pad)222形成于保护层220之上。金属焊盘222可由铝(aluminum)、铜(copper)、银(silver)、金(gold)、镍(nickel)、钨(tungsten)、上述合金、及/或上述的多层所组成。金属焊盘可电性连接至元件与导通孔216，例如穿过底下的第一内连线结构218。介电缓冲层(dielectric buffer layer)224形成于金属焊盘之上，且被图案化以提供凸块形成窗口(bump formation window)。介电缓冲层(dielectric bufferlayer)224可由高分子组成，例如环氧树脂(epoxy)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzoxazole，PBO)或类似材料。也可使用其他相对较软的材料，通常是有机或介电材料。凸块结构226接着形成于金属焊盘222之上且电性连接至金属焊盘222。凸块结构224请参见图1、图4、图5与图7的结构25、25a，因此细节在此不再赘述。
请参见图8B，晶片200通过一粘着层(adhesive layer)302粘着至载板(carrier)300且接着翻转(flip)此接合结构(bonded structure)。既然接合结构被翻转，因此之后对第二表面210b进行薄化工艺(thinning process)，例如研磨及/或蚀刻(grinding and/or etching)，以移除大部分的基材210，以达到最后所需的厚度，得到薄化基材210”，其中薄化基材210”的预定厚度视所选择的半导体封装的目的而定。本领域普通技术人员应能了解的是，也可使用其他薄化工艺，例如研磨工艺(包括湿式研磨(化学机械研磨(CMP))与干式研磨)、等离子体蚀刻工艺、湿式蚀刻工艺或类似的工艺。于一实施例中，暴露导通孔216的末端216a，且于薄化工艺之后，导通孔216的末端216a从薄化基材210”的第二表面210b”延伸突出。接着，处理薄化基材210”的第二表面210b”，以形成一第二内连线结构228电性连接至导通孔216。例如，第二内连线结构228包括电性连接及/或其他形成于薄化基材210”表面210b”上的其他结构(例如重新分布层、接合焊盘、焊料凸块或铜凸块)。后侧研磨与内连线结构的形成方法详述于美国专利申请案12/332,934中，发明名称为“后侧连线至具有重新分布线的导通孔”(Backside Connection to TSVs havingRedistribution Lines)，与美国专利申请案12/347,742，发明名称为“接合焊盘连接至具有渐尖轮廓的重新分布线”(Bond pad Connection to RedistributionLines Having Tapered Profiles)，这些申请案在此作为参考案，因此，不再详述制作的细节。
接着，裸片400接合至薄化基材210”。裸片400可以是存储器芯片(memory chips)、无线射频(radio frequency，RF)、逻辑芯片(logic chips)或其他芯片。每一个裸片400包括凸块结构402用以电性连接至薄化晶片210”的第二内连线结构228。凸块结构402包括一铜层404、于铜层404之上视需要而设的盖层406、与于铜层404上的一无铅焊料层408。铜层404可以是厚度为约0.5～1.0μm的薄铜层，或者是厚度为约40～70μm的厚铜层。视需要而设的盖层406可包括镍(nickel)、金(gold，Au)、银(silver)、钯(palladium，Pd)、铟(indium，In)、镍-钯-金合金(nickel-palladium-gold，NiPdAu)、镍金合金(NiAu)或类似的材料或合金。无铅焊料层408可以是电镀层或回焊后作为焊料球。无铅焊料层408为锡银合金，其中银含量控制在小于1.6重量百分比(wt％)。于回焊工艺中，无铅焊料层408的熔化温度可调整控制在温度240℃～280℃间。于一实施例中，无铅焊料层408的银含量介于约1.2重量百分比～1.6重量百分比。于其他实施例中，无铅焊料层408的银含量为约1.5重量百分比。
请参见图8C，裸片400经由凸块结构402接合至第二内连线结构228，形成裸片对晶片堆叠(die-to-wafer)500。使用一系列耦合工艺(couplingprocess)，包括助焊剂应用(flux application)、芯片置换(chip replacement)、焊料接点的回焊(reflowing ofmelting solderjoints)与残余助焊剂的清洁(cleaningof flux residue)等，使接合结构(joint structure)502形成于晶片210”与裸片400之间。接合结构502包括凸块结构402、第二内连线结构228、与接合于其中的无铅焊料层408。因此，载板300从薄化晶片210”中脱附(detached from)，接着，使用常用的方法沿着切割线(cutting lines)切割裸片对晶片堆叠500，以将裸片对晶片堆叠分离成独立的集成电路堆叠(IC stacks)，且之后封装至一封装基材上，其中封装基材具有焊料凸块或铜凸块镶嵌于封装基材的接合焊盘(pad)上。于一些实施例中，封装基材被其他裸片所取代。
虽然本发明已以数个优选实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (14)

1.一种半导体元件，包括：
一半导体基材；
一焊盘区域，位于该半导体基材上；以及
一凸块结构，位于该焊盘区域之上且电性连接该焊盘区域，其中该凸块结构包括一铜层与位于该铜层之上的一锡银合金层，且该锡银合金层中的银含量小于1.6重量百分比。
2.如权利要求1所述的半导体元件，其中该锡银合金层中的银含量大于1.2重量百分比。
3.如权利要求1所述的半导体元件，其中该锡银合金层中的银含量大于1.5重量百分比。
4.如权利要求1所述的半导体元件，其中该铜层为厚度大于40微米的一铜柱。
5.如权利要求1所述的半导体元件，其中该铜层的厚度小于10微米。
6.如权利要求1所述的半导体元件，还包括：
一镍层介于该铜层与该锡银合金层之间。
7.如权利要求1所述的半导体元件，还包括：
一导通孔穿过该半导体基材且电性连接该焊盘区域，其中该导通孔包括铜。
8.一种半导体组件，包括：
一第一基材；
一第二基材；以及
一接合结构，设置于该第一基材与该第二基材之间；
其中该接合结构包括介于该第一基材与该第二基材之间的一凸块结构，与介于该凸块结构与该第二基材之间的一焊料层；以及
其中该焊料层包括银，且该焊料层中的银含量小于3.0重量百分比。
9.如权利要求8所述的半导体组件，其中该凸块结构包括厚度大于40微米的一铜柱。
10.如权利要求8所述的半导体组件，其中该凸块结构包括一铜层以及一含镍层位于该铜层之上。
11.如权利要求8所述的半导体组件，其中该凸块结构包括厚度小于10微米的一铜层。
12.如权利要求8所述的半导体组件，其中该第一基材与该第二基材至少之一为一半导体基材，且该半导体基材包括一导通孔穿过该半导体基材且电性连接该凸块结构。
13.一种半导体元件的制法，包括以下步骤：
提供一半导体基材；
形成一焊盘区域位于该半导体基材之上；
形成一铜柱位于该焊盘区域之上；
形成一无铅焊料层位于该铜柱之上，其中该无铅焊料层包括银，且银含量小于1.6重量百分比；以及
于温度240℃-280℃之间回焊该无铅焊料层。
14.如权利要求13所述的半导体元件的制法，其中该无铅焊料层的银含量大于1.2重量百分比。
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US20110193219A1 (en) 2011-08-11
US8952534B2 (en) 2015-02-10

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