CN1823410A - 具有侧壁绝缘层的金属凸起和制造具有该金属凸起的芯片的方法 - Google Patents

具有侧壁绝缘层的金属凸起和制造具有该金属凸起的芯片的方法 Download PDF

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CN1823410A
CN1823410A CNA2004800203814A CN200480020381A CN1823410A CN 1823410 A CN1823410 A CN 1823410A CN A2004800203814 A CNA2004800203814 A CN A2004800203814A CN 200480020381 A CN200480020381 A CN 200480020381A CN 1823410 A CN1823410 A CN 1823410A
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metal
chip
insulating barrier
conductive bumps
metal bump
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J·索洛德扎迪瓦
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

一种具有至少两个金属凸起(6a、6b)的芯片，金属凸起(6a、6b)相对的侧壁具有在等离子活性气体中沉积的绝缘层。绝缘层(7)的预定部分通过活性离子蚀刻消除。金属凸起可由贵金属形成，绝缘层可由比如SiO2、Si3N4的介电材料形成。

Description

具有侧壁绝缘层的金属凸起和制造具有该金属凸起的芯片的方法
本发明涉及一种集成电路上的金属凸起，其具有侧壁绝缘层。本发明尤其涉及一种用于固定在玻璃板上的液晶显示器(LCD)的驱动集成电路。本发明还涉及一种制造包括该凸起的芯片的方法。此外，本发明涉及一种连接芯片基底和玻璃板或箔的连接器。
各向异性接触膜(ACF)是一种常见的用来将芯片固定在玻璃板上的材料。它是一种粘合膜，由分散的、直径为3-15μm的微小导电颗粒和厚度为15-35μm的粘合剂构成。ACF装配工艺的局限性在于这样一个事实，即，通过减小相邻凸起之间的间隙，相邻凸起之间短路的可能性就急剧增加。接触两相邻凸起侧壁的导电球链的形成会使它们一起短路。ACF装配工艺专用于玻璃上的芯片(COG)和箔上的芯片(COF)的高级包装应用场合。
美国专利申请US2002/0048924A1披露了这样的多个金属凸起，其包括至少一个具有第一侧壁的第一金属凸起，该第一侧壁包括第一预定区；至少一个具有第二侧壁的第二金属凸起，该第二侧壁包括紧邻第一预定区的第二预定区，其中，至少第一预定区覆盖有一绝缘层。该绝缘层可覆盖第一和第二金属凸起的整个侧壁。第一金属凸起的预定部分可覆盖有一绝缘层。这么一来就防止了由导电颗粒引起的电路短路。在US2002/0048924A1中，披露了将二氧化硅(SiO2)或氮化硅(Si3N4)用作侧壁上绝缘层材料的内容。
美国专利US6232563B1涉及一种连接器结构，其采用一种包括若干导电元件的粘合材料将一半导体装置连接到外端子上。该连接器结构包括一个半导体装置基底上的垫；一个垫上的导电凸起，其采用一种包括若干导电元件的导电粘合材料与外端子的垫连接；以及一个在导电凸起侧面上的绝缘层，该绝缘层基本上覆盖了导电凸起的整个侧面以防止侧面短路。所披露的制造该连接器结构的方法包括的步骤有：
i.在其上形成有驱动装置的基底上形成导电材料比如铝的垫，
ii.在包括垫的基底的整个表面上形成钝化层比如二氧化硅层或氮化硅层，
iii.选择性地蚀刻钝化层以露出垫的一部分，这样钝化层的一部分就覆盖垫的边缘，
iv.在垫露出的部分和钝化层上沉积阻挡层(例如，TiW/Au，Ti/PtAu)，
v.在阻挡金属层上选择性地形成光致抗蚀剂图形，以露出垫上阻挡金属层的一部分，
vi.通过采用光致抗蚀剂图形进行电镀而在阻挡金属层上形成金(Au)凸起，
vii.消除光致抗蚀剂图形，
viii.选择性地蚀刻阻挡金属层以形成扩散抑制部分，
ix.执行热处理，
x.例如通过化学气相沉积(CVD)、物理气相沉积(PVD)或涂布在凸起、钝化层和扩散抑制部分的露出部分上形成一绝缘层比如聚合物层、光敏聚合物层或氮化硅层，
xi.在绝缘层上涂布光致抗蚀剂，
xii.选择性地消除光致抗蚀剂以形成限定凸起上接触区的光致抗蚀剂图形，
xiii.通过将光致抗蚀剂图形用作掩模或通过光学处理(在光敏材料的情况下)蚀刻绝缘层，
xiv.消除光敏抗蚀剂图案以完成凸起电极。
US6232563B1中倡导的方法需要一个掩蔽措施，其中，将光致抗蚀剂涂布在绝缘层上并选择性地消除以形成限定凸起上接触区(绝缘层被部分蚀刻)的光致抗蚀剂图形。随后，消除光致抗蚀剂图形。
本发明的一个目的在于，进一步改进根据一般介绍所述的制造凸起的方法。本发明的另一个目的在于，提供一种制造方式得以改进的连接器。本发明的又一个目的在于，提供能容易制造的金属凸起。
就方法而言，发明目的是通过如权利要求1所述的一种方法实现的。将覆盖芯片钝化层和金属垫的沉积金属层用作绝缘层等离子蚀刻期间的蚀刻抑制件(etch stop)。绝缘层在低压等离子体激活的气体中沉积，此时分子分裂成离子和电子，促进了反应，提高了沉积率。随后采用一种专门的方法，其基于RIE(活性离子蚀刻)来消除绝缘层的预定(集成电路表面上的水平区)部分，简化了制造芯片的方法，利于减少成本和加工时间，因为省略了包括下列步骤的那些掩蔽措施，即(xi)在绝缘层上涂布光致抗蚀剂，(xii)选择性地消除光致抗蚀剂以形成限定凸起上接触区的光致抗蚀剂图形，(xiv)消除光致抗蚀剂图形以完成凸起电极。
就连接器而言，发明目的是通过如独立权利要求2所述的连接器实现的。低压化学气相沉积(LPCVD)是一种动态控制反应速度的工艺，其意味着反应速度随温度而变。该工艺能形成这样的层，即，其在集成电路表面构形的水平区和垂直壁上的层厚均一。绝缘层可由二氧化硅(SiO2)形成，其通过硅烷(SiH4)或二氯甲硅烷(SiH2Cl2)与比如NO或N2O4的氧化剂起反应而形成。反应是在压力约为1毫巴的430-633℃的温度范围内发生的。与N2O4起反应的活化能为0.91电子伏/分子，其与87.4kJ/mol相对应。该温度范围使得该方法适用于将二氧化硅层施加在玻璃、铝以及许多金属硅化物上。
就金属凸起而言，发明目的的实现，是因为通过LPCVD工艺在低于大气压下提供至少两金属凸起的两相对侧壁的绝缘层。压力的减小有助于减少不期望的气相反应，并提高晶片上的薄膜均匀性。
根据一个实施例，绝缘层是一介电层，其通过等离子沉积形成并在各向异性等离子蚀刻机中部分地深腐蚀。各向异性等离子蚀刻机可直接使用而不用执行掩蔽步骤。
根据一个实施例，形成绝缘层的介电材料是包括SiO2或Si3N4的组合的一部分。这些介电材料在LPCVD工艺中被证实是可靠的。
根据另一个实施例，金属凸起由贵金属或抗氧化材料如金(Au)或铂系元素的金属形成。凸起采用贵金属的话，就会在电阻小的ACF聚合物中产生一个与导电元件(或颗粒)接触的表面。
所发明的凸起尤其可用于玻璃上芯片或箔上芯片的封装应用场合。
现在将参照附图对本发明的一个示范性实施例进行详细描述。
图1在横剖图中示出了加工步骤；
图2示出了连接器的横剖图。
图1在横剖图中示出了加工步骤。图1(a)示出了加到芯片基底2上的金属垫1a、1b。钝化层3沉积在芯片基底2上未被任何金属垫1a、1b覆盖但覆盖了这些金属垫1a、1b边缘的部分上。下凸起金属层4覆盖钝化层3和那些未被钝化层3覆盖的金属垫1a、1b的部分。
图1(1b)示出了下一个步骤，其中光致抗蚀剂被涂布在阻挡金属层4上并被选择性地消除以形成光致抗蚀剂图形5，从而在垫1a、1b上露出阻挡金属层4的一部分。
图(1c)示出了形成在利用光致抗蚀剂图形5沉积的阻挡金属层4的露出部分上的凸起6a、6b。
在图(1d)中，消除光致抗蚀剂图形，并在凸起6a、6b的顶面和侧面以及下凸起阻挡金属层4上沉积绝缘层7。绝缘层7在分子分裂成离子和电子的聚集等离子态下沉积。
图(1e)示出了进行活性等离子蚀刻之后的状态。随后消除那些金属层4在侧壁之间露出的部分。因为RIE工艺的各向异性特征，覆盖凸起6a、6b垂直壁的绝缘层予以保留。金属层4的剩留部分形成如图2所示的扩散抑制阻挡层4′。
图2示意性地示出了本发明连接器10的横剖图。连接器10将芯片基底2和与之相对的比如玻璃板或箔的基底9连接起来。电子连接是经由芯片基底2上的金属垫1a、1b、扩散抑制阻挡层4′、凸起6a和6b、导电颗粒11以及电极垫8a和8b形成的。在两凸起6a、6b之间存在间隙。如果间隙足够小，导电颗粒11的链就可接触两凸起6a、6b的侧壁。虽然如此，却防止了电路短路，因为凸起6a、6b的侧壁被绝缘层7盖着。

Claims (7)

1.一种制造具有金属凸起(6a、6b)侧壁的绝缘层(7)的芯片的方法，芯片包括：
不导电的芯片基底(2)，
沉积在不导电芯片基底(2)上的金属垫(1a、1b)，
覆盖不导电芯片基底(2)和金属垫(1a、1b)边缘的钝化层(3)，
覆盖一部分芯片钝化层(3)和金属垫(1a、1b)的金属扩散抑制阻挡层(4)，
金属层(4)上的光致抗蚀剂图形(5)，露出垫(1a、1b)上金属层(4)的部分，使用之后被消除，
至少一个位于垫(1a、1b)的露出部分和金属层(4)边缘上的凸起(6a、6b)，
其特征在于，包括的步骤有：
沉积覆盖芯片钝化层(3)和金属垫(1a、1b)的金属层(4)，
在等离子激活反应器中沉积绝缘层(7)，
通过活性离子蚀刻消除绝缘层(7)预定的部分，
部分地消除金属层(4)，这样就使剩留的金属材料形成凸起扩散抑制阻挡层(4′)。
2.一种用来连接芯片基底(2)和相对基底(9)的连接器(10)，包括：
若干位于相对基底(9)上的电极垫(8a、8b)；
若干位于芯片基底(2)上的导电凸起(6a、6b)，每一个导电凸起(6a、6b)都与相对基底(9)上若干电极垫(8a、8b)中对应的一个电连接；
若干位于导电凸起(6a、6b)对应顶面上的导电颗粒(11)，使得相应的导电凸起(6a、6b)与若干电极垫(8a、8b)电连接；
位于若干导电凸起(6a、6b)中每一个的侧壁表面上由硝酸盐或氧化物形成的绝缘层(7)，防止在两凸起之间发生电路短路，
其特征在于，通过LPCVD工艺提供绝缘层(7)。
3.一种金属凸起(6a、6b)，包括多个侧壁，其在至少两个相互面对的相对侧壁上覆盖有一绝缘层(7)，其特征在于，绝缘层(7)是一介电层，其通过等离子沉积形成并在各向异性等离子蚀刻机中部分地深腐蚀。
4.如权利要求3所述的金属凸起，其特征在于，介电材料选自由SiO2和Si3N4构成的组合。
5.如权利要求3或4所述的金属凸起，其特征在于，金属凸起(6a、6b)由贵金属或抗氧化材料如金形成。
6.玻璃上芯片或箔上芯片封装应用场合中的金属凸起(6a、6b)的应用，金属凸起(6a、6b)部分地覆盖有一绝缘层(7)，绝缘层(7)是通过LPCVD工艺沉积的。
7.一种具有芯片基底(2)和相对基底(9)的装置，包括：
若干位于相对基底(9)上的电极垫(8a、8b)；
若干位于芯片基底(2)上的导电凸起(6a、6b)，每一个导电凸起(6a、6b)都与相对基底(9)上若干电极垫(8a、8b)中对应的一个电连接；
若干位于导电凸起(6a、6b)对应顶面上的导电颗粒(11)，使得相应的导电凸起(6a、6b)与若干电极垫(8a、8b)电连接；
位于若干导电凸起(6a、6b)中每一个的侧壁表面上由硝酸盐或氧化物形成的绝缘层(7)，防止在两凸起之间发生电路短路，
其特征在于，通过LPCVD工艺提供绝缘层(7)。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237329A (zh) * 2010-04-27 2011-11-09 瑞鼎科技股份有限公司 芯片结构及其芯片接合结构与制造方法
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CN106560915A (zh) * 2015-10-01 2017-04-12 松下知识产权经营株式会社 元件芯片的制造方法和电子部件安装结构体的制造方法
US20230014450A1 (en) * 2021-07-16 2023-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176583B2 (en) * 2004-07-21 2007-02-13 International Business Machines Corporation Damascene patterning of barrier layer metal for C4 solder bumps
CN100416875C (zh) * 2005-03-30 2008-09-03 南茂科技股份有限公司 使用凸块进行封装的结构及其形成方法
JP4654790B2 (ja) * 2005-06-20 2011-03-23 セイコーエプソン株式会社 半導体装置及びその製造方法
JP4768491B2 (ja) * 2006-03-30 2011-09-07 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
CN100447973C (zh) * 2006-05-12 2008-12-31 联咏科技股份有限公司 芯片结构及其制造工艺
US9093322B2 (en) * 2007-07-13 2015-07-28 Intel Mobile Communications GmbH Semiconductor device
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8377816B2 (en) 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
TW201121006A (en) * 2009-12-03 2011-06-16 Hannstar Display Corp Connection structure for chip-on-glass driver IC and connection method therefor
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
TWI600129B (zh) * 2013-05-06 2017-09-21 奇景光電股份有限公司 玻璃覆晶接合結構
US9613921B2 (en) * 2013-10-18 2017-04-04 Globalfoundries Inc. Structure to prevent solder extrusion
JP6436531B2 (ja) * 2015-01-30 2018-12-12 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP7332304B2 (ja) * 2019-02-14 2023-08-23 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6381948A (ja) * 1986-09-26 1988-04-12 Toshiba Corp 多層配線半導体装置
US5358902A (en) * 1989-06-26 1994-10-25 U.S. Philips Corporation Method of producing conductive pillars in semiconductor device
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
TW464927B (en) * 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof

Cited By (6)

* Cited by examiner, † Cited by third party
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US20230014450A1 (en) * 2021-07-16 2023-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same

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