CN1565053A - 允许具有带接触焊盘的面的电器件的电和机械连接的工艺 - Google Patents
允许具有带接触焊盘的面的电器件的电和机械连接的工艺 Download PDFInfo
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- CN1565053A CN1565053A CNA028195388A CN02819538A CN1565053A CN 1565053 A CN1565053 A CN 1565053A CN A028195388 A CNA028195388 A CN A028195388A CN 02819538 A CN02819538 A CN 02819538A CN 1565053 A CN1565053 A CN 1565053A
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Abstract
一种可与另一电器件电学和机械连接的电器件的制造方法,该电器件具有配置有接触焊盘的面,该方法的特征在于包括:层涂敷步骤,其中在配置有接触焊盘的该面上涂敷粘合层,该粘合层由具有粘合性的物质构成;开口形成步骤,其中在接触焊盘层上穿过粘合层形成开口;开口填充步骤,其中用导电材料填充开口,使得导电材料基本上填满开口,以形成由开口限定其体积的导电通路。
Description
技术领域
本发明涉及一种电器件和另一电器件的电学和机械连接。二电器件皆可以是例如晶片、集成电路,甚至仅是元件。本发明特别适用于集成电路保护领域,尤其是存储卡领域。
背景技术
一种连接工艺以称为ACF(各向异性导体膜)的膜的使用为基础。这种类型的膜包括在膜厚度上延伸的导电单元。按照第一步,膜单独形成在一中间支撑上。按照第二步,使用次雕刻(sub-engraving)精细修复该膜。按照第三步,该膜在每一面上涂胶以把它施加到第一元件。最后一步是把第二元件连接到膜仍未被覆盖的部分上。最终,两个元件通过涂敷在膜两面上的胶被机械固定,并利用包含在膜中的金属单元而电连接。
US6256874介绍了一种在电子电路封装中连接两导电层的方法,该方法包括步骤:在第一导电层的选定区上形成树突(dentrite);在第二导电层的选定区上形成树突。通过在第一表面金属区形成光致抗蚀剂材料,然后通过光刻技术曝光并显影该光致抗蚀剂以制备其上将形成树突的曝光区,从而形成树突。接着去除光致抗蚀剂。该方法还包括步骤:在第一导电层上涂敷环氧树脂粘合材料,把第二导电层加压粘接到第一导电层上,以使第一导电层上的树突与第二导电层上的树突接触。
发明内容
本发明的目的是降低成本。
按照发明的一个方面,一种可与另一电器件电和机械连接的电器件的制造方法,该电器件具有配置有接触焊盘(contact pad)的面,该方法的特征在于其包括:
-层涂敷步骤(1ayer-application step),其中在配置有接触焊盘的该面上涂敷粘合层,该粘合层由具有粘合性的物质构成;
-开口形成步骤,其中在接触焊盘层上穿过该粘合层形成开口;
-开口填充步骤,其中用导电材料填充该开口,使得开口基本被导电材料填充,以形成由开口限定其体积的导电通路。
该粘合层如同用作形成导电通路的模具。因此,无需如US6256874中的特定光致抗蚀剂层。由此,本发明允许降低成本。
附图说明
在阅读参照附图所述的以下非限定性说明后,将会更好地理解本发明,其中:
-图1以剖面图示出作为本发明工艺起始点的板;
-图2以剖面图示出按照本发明工艺主题中的第一步涂敷于该板上的固定有机层;
-图3以剖面图示出按照本发明工艺主题中的第二步已构造好的固定有机层;
-图4示出按照本发明的工艺中给该固定层(fixing layer)配置小的金属棒的步骤;
-图5以水平投影图和剖面图示出部分板;
-图6示出按照本发明工艺的固定步骤的开始;
-图7以剖面图示出热压固定的步骤之后的板;
-图8以剖面图示出第一板变薄。
具体实施方式
图1示出根据本发明的工艺中的起始点。它示出包括硅芯片1的板0,在硅芯片1上布置有电路2。钝化层3叠置在包括电路2的层上。在该钝化层3中嵌入有接触焊盘4,其目的是布置与其它电路的互连。
图2示出工艺中的第一步,事实上是布置具有粘合特性的有机层5的步骤。该有机层叠置在包括接触焊盘4的钝化层3上。例如,该有机层以通过离心法获得的溶液的形式铺设。
在干燥步骤之后,如图3所示,部分或全部去除有机物5,这尤其是在接触焊盘4的层面上。例如通过蚀刻可以实现该物质的去除。如果有机物是光敏的,那么在使用掩模之后,还可以将它曝光于射线(ray),尤其是UV射线下。有机物的曝过光的部分最后使用化学浴(chemical bath)溶解。如此修饰的有机层5被称为形成了一结构。
图4示出随后的步骤,该步骤是在已经去除有机物的区域中生长小的金属棒7的步骤。例如,使用无电镀或电化学法在化学浴中实现该金属棒的生长。小金属棒7优选地垂直于接触焊盘表面4取向,且通过层5中的有机物彼此绝缘。虽然图4示出在接触焊盘4的层上存在小金属棒7,但这并不排除在其它区域也生长一些小金属棒的可能。
如图6所示,随后的步骤是把与板0相同类型的第二板0’排列在第一板0上,使得接触焊盘4和4’彼此面对的步骤。该第二板可以包括电路2工作所须的电路2’。
如图7所示,在后面的步骤中,板0和0’两者例如使用热压(thermo-compression)固定。还可以有利地使用超声技术。
板0’包括介质8,以允许电接触4借助例如图7中可见的布线电缆(wiring cable)9引出到外部。
图8示出为了例如能把可能滑动的片插入到卡体或为了防伪增加分离电路的困难,可接着继续进行板0在其底面1”的层面上的减薄。
当然,如上给出的发明实施例的说明不是对本发明的限制,本发明应被广泛地理解。
特别是,本发明的主题不仅可以用于元件或集成电路层次的机械和电连接领域,而且还可用于具有配置有接触焊盘的面的任何其它电器件层次。这可以尤其涉及任意尺寸的晶片,例如具有150mm直径且包括约1000个元件的晶片。
至于有机层5,可以使用优选具有粘着特性的任意材料。尤其可以是聚酰亚胺、光敏树脂或热塑性塑料。这些材料还有促进金属化合物生长的优点。
热塑性塑料的使用是令人感兴趣的,因为它可以无损伤地分隔两个电单元。另一方面,使用聚酰亚胺具有一优点,即无论何时它都力图使得难以无物理损伤地分离两个元件。这在涉及物理防伪的存储卡领域尤其令人感兴趣。
小金属棒7更一般地可以是金属化合物,例如具有镍、钯或铜的化合物。
优选地,如图5中可看到的那样,每个接触区4可生长有几个小金属棒7,一般为约10个。这允许较好质量的电接触。例如,该小金属棒的直径在10μm到30μm之间。
按照本发明的金属接触结构(4、7、4’)避免了所谓的接触修复(contactrecovery)。这是因为在市场上的晶片上,在通常为铝的接触焊盘上常常存在局部的氧化斑。接触修复在于清洗这些接触焊盘以去除氧化物,以具有好质量的电连接。但是,特别是由于小金属棒7相对于氧化斑尺寸的数量和减小的截面尺寸,按照本发明的接触结构(4、7、4’)使得能够免除被称为接触修复的此步骤。
例如,假定在某接触焊盘层面上存在25个小金属棒。还假定存在氧化斑,其阻止这25个小金属棒中的10个与接触焊盘接触。在这种情况下,有15个金属小棒保持接触并仍确保电器件之间的相当好的电连接。
尤其在通过热压固定的情况中,更好的是如果图7所示的导电通路7具有比有机层5厚度更大的长度,使得在固定时,在第二板0’的接触焊盘4’的金属中具有这些通路的良好互相贯通。一般地,这些焊盘是铝的并且大约1μm厚。
实施例的其它模式也可以给出特别令人感兴趣的结果。
在界面固定层(5、7),可以使用几层复合材料。可以使用中间层在界面(5、7)上重新布置接触区4。接续构造第一有机层,可以通过沉积形成金属线路。可以再次使用第二结构化的有机层以用于金属化合物的生长。
可以以这种方式使用类似于有机层5的若干个层,以形成导电介质或形成金属线路。最后步骤仍然是与第二电器件电和机械连接的步骤。
还可以使用与有机层5类似的若干层来提高界面的安全性和复杂性。多层结构也可以借助电路表面的更好的平坦化或寻求更好的化学反应性来提高固定质量。
当在用作固定层的有机层5中生长金属小棒之后,板可以被分为更小的电个体,例如集成电路或元件。于是可以使用所谓倒装芯片的技术安装这些电个体。有机层中的材料用作支撑上的粘着剂。于是使用倒装芯片技术可以获得约10μm的连接,而不是40μm至60μm。连接尺寸的这种减小在高频领域中尤其有利。
Claims (7)
1.一种制造一可与另一电器件电和机械地连接的电器件的方法,该电器件具有配置有接触焊盘的面,该方法的特征在于其包括:
-层涂敷步骤,其中在配置有接触焊盘的该面上涂敷粘合层,该粘合层由具有粘合性的物质构成;
-开口形成步骤,其中在接触焊盘上方穿过该粘合层形成开口;
-开口填充步骤,其中用导电材料填充所述开口,使得所述开口基本被该导电材料填充,以形成其体积由所述开口限定的导电通路。
2.根据权利要求1的方法,其特征在于,所述固定层是聚酰亚胺。
3.根据权利要求1的方法,其特征在于,在所述接触焊盘上方穿过该固定层形成若干开口,且所述导电材料加入所述开口中,使得每个开口基本上被该导电材料填充,以形成其体积由所述开口限定的导电通路。
4.一种电和机械地连接第一电器件和第二电器件的方法,每个器件具有配置有接触焊盘的面,该方法的特征在于其包括:
-层涂敷步骤,其中在该第一电器件的配置有接触焊盘的该面上涂敷粘合层,该粘合层由具有粘合性的物质构成;
-开口形成步骤,其中在接触焊盘上方穿过该粘合层形成开口;
-开口填充步骤,其中用导电材料填充所述开口,使得所述开口基本上被该导电材料填充,以形成其体积由所述开口限定的导电通路;
-器件连接步骤,其中使所述固定层与该第二电器件的所述面接触,导电通路在该第一电器件的接触焊盘和该第二电器件的接触焊盘之间形成电连接。
5.一种电和机械地连接第一晶片和第二晶片的方法,每个晶片具有配置有接触焊盘的面,该方法的特征在于其包括:
-层涂敷步骤,其中在该第一晶片的配置有接触焊盘的该面上涂敷粘合层,该粘合层由具有粘合性的物质构成;
-开口形成步骤,其中在接触焊盘上方穿过该粘合层形成开口;
-开口填充步骤,其中用导电材料填充所述开口,使得所述开口基本上被该导电材料填充,以形成其体积由所述开口限定的导电通路;
-器件连接步骤,其中将所述固定层放置成与该第二晶片的所述面接触,导电通路在该第一晶片的接触焊盘和该第二晶片的接触焊盘之间形成电连接;
-切割步骤,其中如此连接的该两个晶片被切割成更小的电个体。
6.一种电器件,其可电和机械地连接于另一电器件,该电器件具有配置有接触焊盘的面,其特征在于,该电器件包括涂敷于所述面上的连接层,该连接层具有粘合性并包括导电通路,该导电通路由该连接层中贯穿该连接层延伸并用导电材料填充的开口形成。
7.一种电装置,包括第一电器件和第二电器件,借助具有粘合性的物质构成的连接层该第一器件和第二器件彼此电连接,该装置的特征在于,该连接层包括由穿过该连接层延伸并用导电材料填充的开口形成的导电通路。
Applications Claiming Priority (3)
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FR0110483A FR2828334A1 (fr) | 2001-08-03 | 2001-08-03 | Procede pour rendre connectable electriquement et mecaniquement un dispositif electrique ayant une face munie de plots de contacts |
FR01/10483 | 2001-08-03 | ||
PCT/IB2002/003041 WO2003015153A2 (en) | 2001-08-03 | 2002-08-02 | Process to allow electrical and mechanical connection of an electrical device with a face equipped with contact pads |
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CN200910205384XA Division CN101872753B (zh) | 2001-08-03 | 2002-08-02 | 具有带接触焊盘的面的电器件及其构成的电装置 |
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CN200910205384XA Expired - Fee Related CN101872753B (zh) | 2001-08-03 | 2002-08-02 | 具有带接触焊盘的面的电器件及其构成的电装置 |
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EP (1) | EP1421614B1 (zh) |
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KR (1) | KR100934862B1 (zh) |
CN (2) | CN1565053B (zh) |
AU (1) | AU2002355496A1 (zh) |
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FR2866753B1 (fr) * | 2004-02-25 | 2006-06-09 | Commissariat Energie Atomique | Dispositif microelectronique d'interconnexion a tiges conductrices localisees |
FR3078823B1 (fr) | 2018-03-12 | 2020-02-21 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Empilement 3d de puces electroniques |
US20220084884A1 (en) | 2020-09-15 | 2022-03-17 | Nanya Technology Corporation | Semiconductor structure and method of forming the same |
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JPS6468935A (en) * | 1987-09-09 | 1989-03-15 | Ricoh Kk | Face-down bonding of semiconductor integrated circuit device |
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US5543585A (en) * | 1994-02-02 | 1996-08-06 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
US5501755A (en) * | 1994-02-18 | 1996-03-26 | Minnesota Mining And Manufacturing Company | Large area multi-electrode radiation detector substrate |
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
KR0138295B1 (ko) * | 1994-11-30 | 1998-06-01 | 김광호 | 도전선 형성방법 |
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JPH10321667A (ja) | 1997-05-16 | 1998-12-04 | Ricoh Co Ltd | 半導体装置 |
US6300575B1 (en) * | 1997-08-25 | 2001-10-09 | International Business Machines Corporation | Conductor interconnect with dendrites through film |
DE19800566A1 (de) * | 1998-01-09 | 1999-07-15 | Siemens Ag | Verfahren zum Herstellen eines Halbleiterbauelementes und ein derart hergestelltes Halbleiterbauelement |
US6025638A (en) * | 1998-06-01 | 2000-02-15 | International Business Machines Corporation | Structure for precision multichip assembly |
JP3413120B2 (ja) * | 1999-02-23 | 2003-06-03 | ローム株式会社 | チップ・オン・チップ構造の半導体装置 |
JP2000286549A (ja) * | 1999-03-24 | 2000-10-13 | Fujitsu Ltd | バイアコネクションを備えた基板の製造方法 |
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US20050034303A1 (en) | 2005-02-17 |
CN1565053B (zh) | 2010-05-26 |
HK1068730A1 (en) | 2005-04-29 |
US20100157555A1 (en) | 2010-06-24 |
KR20040030921A (ko) | 2004-04-09 |
US8508952B2 (en) | 2013-08-13 |
AU2002355496A1 (en) | 2003-02-24 |
US8429813B2 (en) | 2013-04-30 |
EP1421614B1 (en) | 2015-02-25 |
CN101872753B (zh) | 2013-01-30 |
EP1421614A2 (en) | 2004-05-26 |
KR100934862B1 (ko) | 2009-12-31 |
CN101872753A (zh) | 2010-10-27 |
JP2005526374A (ja) | 2005-09-02 |
FR2828334A1 (fr) | 2003-02-07 |
WO2003015153A2 (en) | 2003-02-20 |
WO2003015153A3 (en) | 2004-03-11 |
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