JP2005526374A - 電気装置と接触パッドを装備した面との電子および機械接続を可能にする方法 - Google Patents

電気装置と接触パッドを装備した面との電子および機械接続を可能にする方法 Download PDF

Info

Publication number
JP2005526374A
JP2005526374A JP2003519986A JP2003519986A JP2005526374A JP 2005526374 A JP2005526374 A JP 2005526374A JP 2003519986 A JP2003519986 A JP 2003519986A JP 2003519986 A JP2003519986 A JP 2003519986A JP 2005526374 A JP2005526374 A JP 2005526374A
Authority
JP
Japan
Prior art keywords
opening
layer
electrical device
contact pad
conductive path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003519986A
Other languages
English (en)
Inventor
ベアトリス ボンヴァロ
Original Assignee
シュラムバーガー システムズ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シュラムバーガー システムズ filed Critical シュラムバーガー システムズ
Publication of JP2005526374A publication Critical patent/JP2005526374A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/0807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/08112—Disposition the bonding area being at least partially embedded in the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08123—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting directly to at least two bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08148—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area protruding from the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92127—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Multi-Conductor Connections (AREA)

Abstract

【課題】 コスト削減を図る。
【解決方法】 別の電気装置と電気的および機械的に接続可能な電気装置を製造する方法であって、前記電気装置接触パッドを装備した面を備えており、前記方法が、- 層付加段階を備え、前記層付加段階において、接触パッドを装備した面に接着層を付加しており、前記接着層が接着特性を有する物質で構成されており、- 開口部作成段階をさらに備え、前記開口部作成段階において、接触パッドのレベルにおいて、接着層を貫通して開口部が作成され、- 開口部充填段階をさらに備え、前記開口部充填段階において、前記開口部が導電性材料で充填され、これにより、前記開口部が実質的に導電性材料で満たされることで導電路が形成され、前記導電路の容量が該開口部によって画定されることを特徴とする。

Description

本発明は、電気装置と別の電気装置との電気および機械接続に関する。両装置は、例えばウェーハ、集積回路、または単に１つの構成部品であってよい。本発明は特に集積回路保護の分野、および、特にメモリカードの分野に適用される。
接続方法は、ＡＣＦ（異方性導電膜）と呼ばれる膜の使用に基づいている。このタイプの膜は、膜の厚み全体にかけて広がる導電要素を含んでいる。第１段階によれば、膜は中性支持部上に別個に作成される。第２段階によれば、膜は、サブ・エングレイビングを使用して精密に回復される。第３段階によれば、膜の両面に接着剤を塗布し、第１構成部分に接着される。最終段階は、第２構成部分を、膜の未被覆部分に接続することで構成されている。最後に、両方の構成部分が、膜の両面に塗布した接着剤によって機械的に、また、膜で封入した金属要素を使用して電気的に固定される。
米国特許第６，２５６，８７４号は、第１導電層の選択された範囲にデントライトを形成し、第２導電層の選択された範囲にデントライトを形成する段階を備えた、電子回路パッケージ内で２枚の導電層を接続する方法を説明している。デントライトは、フォトレジスト材料の手段によって、第１面金属の範囲に形成され、その後、写真平板技術によって抵抗が出現および増加し、デントライトを形成する範囲が露呈する。さらに、この方法は、第１導電層にエポキシ接着材料を塗布し、第２導電層を第１導電層に圧縮的に取り付けて、第１導電層上のデントライトを第２導電層上のデントライトと接触させる段階を備えている。
本発明の目的は、コストを削減することである。
本発明の１つの態様によれば、別の電気装置と電気的および機械的に接続可能な電気装置を製造する方法であって、前記電気装置接触パッドを装備した面を備えており、前記方法が、
層付加段階を備え、前記層付加段階において、接触パッドを装備した面に接着層を付加しており、前記接着層が接着特性を有する物質で構成されており、
開口部作成段階をさらに備え、前記開口部作成段階において、接触パッドのレベルにおいて、接着層を貫通して開口部が作成され、
開口部充填段階をさらに備え、前記開口部充填段階において、前記開口部が導電性材料で充填され、これにより、前記開口部が実質的に導電性材料で満たされることで導電路が形成され、前記導電路の容量が該開口部によって画定されることを特徴とする。
接着層は、言わば導電路を形成するための鋳型として使用される。そのため、米国特許第６，２５６，８７４号に記載されているフォトレジスト層を特別に設ける必要がなくなる。したがって、本発明によりコストの削減が可能となる。
本発明は、以降に示す、添付の図面を参照して書かれた非限定的な記述を読解することでさらに把握される。
接着層が導電路を形成するための鋳型として使用されるため、フォトレジスト層を特別に設ける必要がなくなる。
図１は、本発明による方法の開始点を示す。同図中では、プレート０がシリコンチップ１を備え、シリコンチップ１の上に回路２が配置されている状態を示している。回路２を備えた層の上に不活性層３が積層される。この不活性層３には、追加の回路と相互接続を設ける目的で、接触パッド４が挿入されている。
図２は、該方法における第１段階、実際には、粘性特性を備えた有機層５を配置する段階を示している。この有機層は、接触パッド４を備えた不活性層３上に積層される。この有機層は、例えば遠心によって得た溶液の形態で配置される。
乾燥段階の後に、また図３に示すように、有機層５が部分的または完全に除去されるが、これは特に接触パッド４のレベルにおいて実施される。この材料の除去は、例えばエッチングによって達成される。さらに、有機材料が感光性である場合には、遮光部材を被覆した後に、これを光線、特に紫外線に露光することができる。有機材料の露出した部分は、最終的に化学薬品槽で溶解される。このように変形させた有機層５は構造物に形成される。
図４は、次の段階、つまり、有機材料を除去した部分内への小型の金属棒７の成長段階を示す。この金属棒の成長は、例えば、無電解または電気化学を用いた化学薬品槽内で実施される。小型の金属棒７は、接触パッド面４に対して垂直方向に向かい、また、層５内の有機材料によって各々から絶縁されることが好ましい。図４は、接触パッド４のレベルにおける小型の金属棒７の存在を指示しているが、これは、他の範囲内へも多少成長する可能性を除外するものではない。
図６に示す次の段階は、接触パッド４、４'が相互に対向するように、プレート０と同タイプの第２プレート０'を第１プレート０上に整列させる段階である。この第２プレートは、回路２の動作に必要な回路２'を備えることができる。
図７に示すこの後の段階では、両プレート０、０'が、例えば熱圧縮を用いて固定される。超音波技術を有益に使用することも可能である。
図７に見られるように、プレート０'は媒質８を含んでおり、この媒質８は、例えば配線ケーブル９の手段によって、電気接触部４を外部に出せるようにするべく設けられている。
図８は、次に、例えば使用可能なスリップシートをカード本体内に挿入するため、または、安全性の目的で回路を離れ難くするために、下方面１”のレベルにおいて先細りしたプレート０へ進むことができることを示している
当然ながら、上述した本発明の実施形態の記述は、幅広く理解されるべき本発明を限定するものではない。
特に、本発明の目的は、構成部品または集積回路のレベルにおける機械および電気接続の分野のみだけでなく、これ以外の、１表面に接触パッドが装備されたあらゆる電気装置のレベルにおいても適用できる。これは特に、任意サイズ、例えば直径１５０ｍｍであり、約１，０００個の構成部品を具備したウェーハの問題である。
有機層５に関しては、好ましくは粘性特性を備えた任意の材料を使用できる。これは、特にポリイミド、感光性樹脂、または熱可塑性物質であってよい。これらの材料は、金属化合物の成長を刺激する利点をさらに備えている。
熱可塑性物質の使用は、２つの電気要素を損傷することなく分離させることが可能な点が関心を引く。その一方で、２つの構成部品の分離を物理的損傷なく困難にする場合には、常にポリイミドを使用することが有益である。これは、物理的安全性に関連したメモリカードの分野において特に関心を引くものである。
小型の金属棒７は、より一般的には金属化合物、例えばニッケル、パラジウムまたは銅との化合物であってよい。
図５に見られるように、１つの接触範囲４について数本、一般には約１０本の小型金属棒７を成長させることができることが好ましい。これにより、比較的良質の電気接触が得られる。小型金属棒の直径は、例えば１０〜３０μｍである。
本発明による金属接触構造（４、７、４'）は、いわゆる接触回復を回避する。これは、市販のウェーハでは、アルミニウムの酸化斑点が接触パッド上に集中して存在する場合が多いためである。接触回復は、優れた電気接触を得るために、接触パッドを洗浄して酸化部分を除去することから成る。しかし、本発明による接触構造（４、７、４'）は、特に小型金属棒７の本数と、酸化斑点の大きさに関連して縮小した断面のために、この接触回復と呼ばれる段階の省略が可能になる。
例えば、特定の接触パッドのレベルにおいて、金属小型棒を２５本設けていると仮定する。さらに、２５本のうち１０本の小型棒が接触パッドと接触することを妨害する酸化斑点が１個存在するとも仮定する。この場合、接触状態にある金属小型棒は１５本であるが、しかし、電気装置との間には比較的優れた電気接続が得られる。
特に、熱圧縮によって固定する場合には、固定時に、導電路７が第２プレート０'の接触パッド４'の金属部分内に十分に貫通するように、図７に示す導電路７の長さを有機層の厚み５よりも長く設けたほうが良い。一般に、これらの導電路はアルミニウム製であり、厚みが約１μｍである。
さらに、本発明の別の方法によっても、特に興味深い結果が得られる。
インターフェース固定レベル（５、７）では、数層の化合物材料を使用できる。中間層は、インターフェース（５、７）上での接触範囲４の再配置使用できる。さらに、第１有機層を構成するために、付着によって金属トラックを作成することができる。第２に構成した有機層を、やはり金属化合物の成長に使用してもよい。
導電媒質を作成するため、または金属トラックを作成するために、この方法で有機層５と類似の数層を使用することが可能である。残る最終段階は、第２電気装置との電気的および機械的接触段階である。
有機層５と類似の数層を、さらに、インターフェースの安全性および複雑性を増加させるために使用することが可能である。回路表面の平滑性を高めることで、またはより優れた化学反作用を探求することで、マルチ層によって固定の質を改善することができる。
固定層として機能する有機層５内で金属小型棒が成長すると、プレートをより小型の電気要素、例えば集積回路または構成部品に分割することができる。その後、フリップチップと呼ばれる技術を使用して、これらの電気要素を取り付ける。これにより、フリップチップ技術を用いた４０〜６０μｍの接続の代わりに、約１０μｍの接続を得ることが可能となる。この接続サイズの縮小は、高周波数の分野において特に有利である。
有機層に粘性特性を備えた任意の材料を使用でき、これにより金属化合物の成長が刺激される。フォトレジスト層を特別に設ける必要がないため、コストの削減が可能である。
本発明の方法の開始地点であるプレートの断面図を示す。 本発明の方法の第１段階に従って、プレートに付加した固定有機層の断面図を示す。 本発明の方法の第２段階に従って構成した固定有機層の断面図を示す。 本発明の方法における、固定層に小型の金属棒を装備する段階を示す。 プレートの一部分を水平投影図および断面図として示す。 本発明の方法による固定段階の初期を示す。 熱圧縮による固定段階後のプレートの断面図を示す。 第１プレートの先細りの断面図を示す。
符号の説明
０、０' プレート
１ シリコンチップ
２、２' 回路
３ 不活性層
４、４' 接触パッド
５ 有機層
６ 整列段階
７ 小型の金属棒
８ 媒質
９ 配線ケーブル

Claims (7)

  1. 別の電気装置と電気的および機械的に接続可能な電気装置を製造する方法であって、前記電気装置が接触パッドを装備した面を備えており、前記方法が、
    層付加段階を備え、前記層付加段階において、接触パッドを装備した面に接着層を付加しており、前記接着層が接着特性を有する物質で構成されており、
    開口部作成段階をさらに備え、前記開口部作成段階において、接触パッドのレベルにおいて、接着層を貫通して開口部が作成され、
    開口部充填段階をさらに備え、前記開口部充填段階において、前記開口部が導電性材料で充填され、これにより、前記開口部が実質的に導電性材料で満たされることで導電路が形成され、前記導電路の容量が該開口部によって画定されることを特徴とする方法。
  2. 前記固定層がポリイミドであることを特徴とする請求項１に記載の方法。
  3. 前記接触パッドのレベルにおいて、前記固定層を貫通して数個の開口部が作成され、前記導電性材料が該開口部内に供給されて、各開口部が前記導電性材料によって実質的に充填されることで、導電路が形成され、前記導電路の容量が前記開口部によって画定されることを特徴とする請求項１に記載の方法。
  4. 第１電気装置および第２電気装置と電気的および機械的に接触する方法であって、各々の装置が接触パッドを装備した面を備えており、前記方法が、
    層付加段階を備え、前記層付着段階において、接着層が接着特性を有する物質で構成されており、
    開口部作成段階をさらに備え、前記開口部作成段階において、接触パッドのレベルにおいて、前記接着層を貫通して開口部が作成され、
    開口部充填段階をさらに備え、前記開口部充填段階において、前記開口部が導電性材料で充填され、これにより、前記開口部が実質的に導電性材料で満たされることで導電路が形成され、前記導電路の容量が該開口部によって画定され、
    装置接続段階をさらに備え、前記装置接続段階において、前記固定層が該第２電気装置の前記面と接触せしめられ、この際、導電路が、前記第１電気装置の接触パッドと前記第２電気装置の接触パッドとの間に電気接続を形成することを特徴とする方法。
  5. 第１ウェーハと第２ウェーハを電気的および機械的に接続する方法であって、各ウェーハが接触パッドを装備した面を備え、前記方法が、
    層付加段階を備え、前記層付加段階において、前記第１ウェーハの接触パッドを装備した前記面に接着層が付加され、前記接着層が接着特性を有する物質で構成されており、
    開口部作成段階をさらに備え、前記開口部作成段階において、接触パッドのレベルにおいて、該接着層を貫通して開口部が作成され、
    開口部充填段階をさらに備え、前記開口部充填段階において、該開口部が導電性材料によって充填され、これにより、開口部が該導電性材料で実質的に満たされることで導電路が形成され、該導電路の容量が該開口部によって画定され、
    装置接続段階をさらに備え、前記装置接続段階において、前記固定層が該第２ウェーハの前記層と接触せしめられ、この際、導電路が、前記第１ウェーハの接触パッドと前記第２ウェーハの接触パッドの間に電気接続を形成し、
    切断段階をさらに備え、前記切断段階において、前記２個のウェーハが、より小型の電気要素に切断されるように接続されていることを特徴とする方法。
  6. 別の電気装置に電気的および機械的に接続可能な電気装置であって、前記電気装置が接触パッドを装備した面を備えており、
    前記電気装置が、前記面に付加された接続層を備えており、前記接続層が接着特性を有し、該接続層に設けた開口部によって形成された導電路を備えており、前記開口部が、該接続層を貫通しており、導電性材料で充填されていることを特徴とする電気装置。
  7. 第１電気装置と第２電気装置を備えた電気組立体であって、前記第１装置および第２装置が、接着特性を有する物質から成る接続層の手段により、相互に対して電気的に接続しており、前記組立体が、
    前記接続層が開口部によって形成された導電路を備え、前記開口部が前記接続層を貫通し、導電性材料で充填されていることを特徴とする電気組立体。
JP2003519986A 2001-08-03 2002-08-02 電気装置と接触パッドを装備した面との電子および機械接続を可能にする方法 Pending JP2005526374A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0110483A FR2828334A1 (fr) 2001-08-03 2001-08-03 Procede pour rendre connectable electriquement et mecaniquement un dispositif electrique ayant une face munie de plots de contacts
PCT/IB2002/003041 WO2003015153A2 (en) 2001-08-03 2002-08-02 Process to allow electrical and mechanical connection of an electrical device with a face equipped with contact pads

Publications (1)

Publication Number Publication Date
JP2005526374A true JP2005526374A (ja) 2005-09-02

Family

ID=8866302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003519986A Pending JP2005526374A (ja) 2001-08-03 2002-08-02 電気装置と接触パッドを装備した面との電子および機械接続を可能にする方法

Country Status (9)

Country Link
US (2) US8429813B2 (ja)
EP (1) EP1421614B1 (ja)
JP (1) JP2005526374A (ja)
KR (1) KR100934862B1 (ja)
CN (2) CN1565053B (ja)
AU (1) AU2002355496A1 (ja)
FR (1) FR2828334A1 (ja)
HK (1) HK1068730A1 (ja)
WO (1) WO2003015153A2 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2866753B1 (fr) * 2004-02-25 2006-06-09 Commissariat Energie Atomique Dispositif microelectronique d'interconnexion a tiges conductrices localisees
FR3078823B1 (fr) 2018-03-12 2020-02-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Empilement 3d de puces electroniques
US20220084884A1 (en) 2020-09-15 2022-03-17 Nanya Technology Corporation Semiconductor structure and method of forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468935A (en) * 1987-09-09 1989-03-15 Ricoh Kk Face-down bonding of semiconductor integrated circuit device
JPH07231011A (ja) * 1994-02-02 1995-08-29 Internatl Business Mach Corp <Ibm> 導電性接着剤による直接チップ付着
JP2000243904A (ja) * 1999-02-23 2000-09-08 Rohm Co Ltd チップ・オン・チップ構造の半導体装置
JP2001015556A (ja) * 1999-07-02 2001-01-19 Casio Comput Co Ltd 半導体装置及びその製造方法並びにその実装構造

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4008300A (en) * 1974-10-15 1977-02-15 A & P Products Incorporated Multi-conductor element and method of making same
US4574095A (en) * 1984-11-19 1986-03-04 International Business Machines Corporation Selective deposition of copper
US4897338A (en) * 1987-08-03 1990-01-30 Allied-Signal Inc. Method for the manufacture of multilayer printed circuit boards
US4941255A (en) * 1989-11-15 1990-07-17 Eastman Kodak Company Method for precision multichip assembly
US5151168A (en) * 1990-09-24 1992-09-29 Micron Technology, Inc. Process for metallizing integrated circuits with electrolytically-deposited copper
US5501755A (en) * 1994-02-18 1996-03-26 Minnesota Mining And Manufacturing Company Large area multi-electrode radiation detector substrate
US5659952A (en) * 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
KR0138295B1 (ko) * 1994-11-30 1998-06-01 김광호 도전선 형성방법
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5717475A (en) * 1996-01-30 1998-02-10 Canon Kabushiki Kaisha Electrode substrate, process for producing the substrate, liquid crystal device and process for producing the device
JPH10321667A (ja) 1997-05-16 1998-12-04 Ricoh Co Ltd 半導体装置
US6300575B1 (en) * 1997-08-25 2001-10-09 International Business Machines Corporation Conductor interconnect with dendrites through film
DE19800566A1 (de) * 1998-01-09 1999-07-15 Siemens Ag Verfahren zum Herstellen eines Halbleiterbauelementes und ein derart hergestelltes Halbleiterbauelement
US6025638A (en) * 1998-06-01 2000-02-15 International Business Machines Corporation Structure for precision multichip assembly
JP2000286549A (ja) * 1999-03-24 2000-10-13 Fujitsu Ltd バイアコネクションを備えた基板の製造方法
FR2792440B1 (fr) * 1999-04-19 2001-06-08 Schlumberger Systems & Service Dispositif a circuit integre securise contre des attaques procedant par destruction controlee d'une couche complementaire
US6350664B1 (en) * 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US7211512B1 (en) * 2000-01-18 2007-05-01 Micron Technology, Inc. Selective electroless-plated copper metallization
US6834426B1 (en) * 2000-07-25 2004-12-28 International Business Machines Corporation Method of fabricating a laminate circuit structure
US6627477B1 (en) * 2000-09-07 2003-09-30 International Business Machines Corporation Method of assembling a plurality of semiconductor devices having different thickness

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468935A (en) * 1987-09-09 1989-03-15 Ricoh Kk Face-down bonding of semiconductor integrated circuit device
JPH07231011A (ja) * 1994-02-02 1995-08-29 Internatl Business Mach Corp <Ibm> 導電性接着剤による直接チップ付着
JP2000243904A (ja) * 1999-02-23 2000-09-08 Rohm Co Ltd チップ・オン・チップ構造の半導体装置
JP2001015556A (ja) * 1999-07-02 2001-01-19 Casio Comput Co Ltd 半導体装置及びその製造方法並びにその実装構造

Also Published As

Publication number Publication date
US20050034303A1 (en) 2005-02-17
CN1565053B (zh) 2010-05-26
CN1565053A (zh) 2005-01-12
HK1068730A1 (en) 2005-04-29
US20100157555A1 (en) 2010-06-24
KR20040030921A (ko) 2004-04-09
US8508952B2 (en) 2013-08-13
AU2002355496A1 (en) 2003-02-24
US8429813B2 (en) 2013-04-30
EP1421614B1 (en) 2015-02-25
CN101872753B (zh) 2013-01-30
EP1421614A2 (en) 2004-05-26
KR100934862B1 (ko) 2009-12-31
CN101872753A (zh) 2010-10-27
FR2828334A1 (fr) 2003-02-07
WO2003015153A2 (en) 2003-02-20
WO2003015153A3 (en) 2004-03-11

Similar Documents

Publication Publication Date Title
JP3736607B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
US5637536A (en) Method for interconnecting semiconductor chips in three dimensions, and component resulting therefrom
JP4271590B2 (ja) 半導体装置及びその製造方法
CN100481402C (zh) 半导体器件和半导体器件的制造方法
JP2007305955A (ja) 半導体装置及びその製造方法
JP3971500B2 (ja) 半導体素子実装用配線基板の製造方法
JP2004259988A (ja) キャパシタ素子及びこの製造方法、半導体装置用基板、並びに半導体装置
JP3003624B2 (ja) 半導体装置
US9706663B2 (en) Printed wiring board, method for manufacturing the same and semiconductor device
JP2006270009A (ja) 電子装置の製造方法
JP2002314257A (ja) 多層回路基板、その製造方法および電気アセンブリ
TW200929475A (en) Interposer and method for manufacturing interposer
JP2004103665A (ja) 電子デバイスモジュール
JP2004047931A (ja) 回路素子の電極形成方法、それを用いたチップパッケージ及び多層基板
US20110248408A1 (en) Package substrate and fabricating method thereof
JP2007103840A (ja) 電子回路装置の製造方法
JP3855320B2 (ja) 半導体装置用基板の製造方法及び半導体装置の製造方法
US8508952B2 (en) Electrical assembly
EP0511218A4 (en) Fabricating eletronic circuitry unit containing stacked ic layers having lead rerouting
US10424541B2 (en) Component carrier and method for manufacturing the same
JP2007103816A (ja) 配線基板および電子回路装置
US6210746B1 (en) Method of fabricating a solder resist mask
JPH06231818A (ja) 弾性を有する異方導電コネクター
CN108305864A (zh) 新型端子
JP2003258196A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050608

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080526

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080602

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080827

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100312

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110307