CN101530012B - 使用介电层封装器件的方法 - Google Patents
使用介电层封装器件的方法 Download PDFInfo
- Publication number
- CN101530012B CN101530012B CN2007800395574A CN200780039557A CN101530012B CN 101530012 B CN101530012 B CN 101530012B CN 2007800395574 A CN2007800395574 A CN 2007800395574A CN 200780039557 A CN200780039557 A CN 200780039557A CN 101530012 B CN101530012 B CN 101530012B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- sealant
- type surface
- side surfaces
- contact site
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000565 sealant Substances 0.000 claims description 58
- 239000004020 conductor Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 239000004593 Epoxy Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000008393 encapsulating agent Substances 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 68
- 238000005516 engineering process Methods 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000007306 turnover Effects 0.000 description 2
- 206010009866 Cold sweat Diseases 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000012812 sealant material Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/24011—Deposited, e.g. MCM-D type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Semiconductor Integrated Circuits (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
- Packaging Frangible Articles (AREA)
Abstract
一种用于封装第一器件(14,46)的方法,所述第一器件具有第一主表面和第二主表面。在第一器件(14,46)的第二主表面上方以及围绕第一器件的侧面形成密封剂(18)。这保留第一器件的第一主表面被暴露。在第一器件(14)的第一主表面上方形成第一介电层(20)。形成侧面接触接口(36,16;48,56,46;48,56,70,72),该侧面接触接口至少有一部分在第一介电层(20)上方。切割该密封剂(18)从而形成密封剂的多个侧面(62,64)。沿着该多个侧面的第一侧面(64)去除该密封剂(18)的一部分从而沿着该多个侧面的第一侧面暴露该侧面接触接口的一部分(72,46,16)。
Description
技术领域
本发明一般涉及封装器件,并且更具体地涉及使用介电层封装器件。
背景技术
典型地,出于在运行期间保护的目的而封装了器件。这些被封装的器件被放置在带有其它器件的印刷电路板(PCB)上。带有器件的PCB用于产品,例如电脑或者蜂窝式电话。由于期望减少产品(例如电脑和蜂窝式电话)的尺寸,因此需要减少PCB和封装器件的尺寸而不损失其功能。在很多情况下,期望有附加的功能。例如,可能期望在一个封装体中具有多于一个器件。另外,所关心的是成本。因此,存在对于一种能增加功能的成本有效的封装方法的需要。
发明内容
根据本公开的一个方面,提供一种封装器件的方法,包含以下步骤:在第一器件的第二主表面上方以及围绕第一器件的侧面形成密封剂,并且保留第一器件的第一主表面被暴露;在第一器件的第一主表面上方形成第一介电层;形成侧面接触接口,侧面接触接口至少有一部分在第一介电层上方;切割密封剂从而形成密封剂的多个侧面;以及沿着多个侧面中的第一侧面去除密封剂的一部分从而沿着多个侧面的第一侧面暴露侧面接触接口的一部分。
根据本公开的另一个方面,提供一种封装器件的方法,包含以下步骤:将带敷设到第一器件的第一主表面;形成密封剂以提供处理第一器件的物理支撑,密封剂在第一器件的第二主表面上方并且围绕第一器件的侧面;在形成密封剂之后从第一主表面上去除带;在第一器件的第一主表面上方淀积第一介电层,第一介电层是聚合物电介质;形成侧面接触接口,侧面接触接口至少有一部分在第一介电层上方;切割密封剂从而形成密封剂的多个侧面;以及沿着多个侧面中的第一侧面去除密封剂的一部分从而沿着多个侧面的第一侧面暴露侧面接触接口的一部分。
根据本公开的再一个方面,提供一种封装器件的方法,包含以下步骤:将具有粘性的带敷设到第一器件的第一主表面和第二器件的第一主表面,其中第一器件沿着第一主表面具有第一接触部,并且第二器件具有第一接触部和第二接触部;在第一器件的第二主表面和第二器件的第二主表面上方以及沿着第一和第二器件的侧面形成密封剂,其中密封剂具有在第一和第二器件的第二主表面上方的第一主表面以及与第一主表面相对的第二主表面;去除带;在第一器件的第一主表面和第二器件的第一主表面上方形成第一介电层;在第一介电层中形成第一通孔和第二通孔;形成第一导体,第一导体从第一器件的第一接触部穿过第一和第二通孔到第二器件的第一接触部;切割密封剂从而在密封剂的第一和第二主表面之间形成密封剂的多个侧面;以及沿着多个侧面中的第一侧面去除密封剂的一部分从而沿着多个侧面的第一侧面暴露第二器件的第二接触部。
根据本公开的实施例,由于在一个或多个层之中将互连布线或者再分布从而使封装体的面积最小化,因此由此产生的封装体可以是再分布的芯片封装体(RCP)。不需要引线接合(wirebonding)或者传统的基底(引线框或者封装基底)来形成RCP。这增大了产量并且减少成本。
附图说明
本发明通过附图作为实例来示出,并且不受附图的限制,在附图中相似的附图标记表示类似的元件。本领域技术人员明白图中的元件为简单和清楚起见来示出,并且没有必要按比例绘制。
图1示出了根据本发明实施例的聚集部位(aggregatedsite)的截面,该聚集部位包括第一器件、第二器件和粘合剂的一部分。
图2示出了根据一个实施例的在管芯(die)和第二器件上方形成密封剂之后图1的聚集部位。
图3示出了根据一个实施例的在去除粘合剂之后图2的聚集部位。
图4示出了根据一个实施例的在形成第一介电层之后图3的聚集部位。
图5示出了根据一个实施例的在形成通孔(via-hole)之后图4的聚集部位。
图6示出了根据一个实施例的在形成通路(via)和互连(interconnect)之后图5的聚集部位。
图7示出了根据一个实施例的在形成第二介电层之后图6的聚集部位。
图8示出了根据一个实施例的在第二介电层中形成通孔之后图7的聚集部位。
图9示出了根据一个实施例的在第二介电层上方形成第三器件之后图8的聚集部位。
图10示出了根据一个实施例的在形成互连之后图9的聚集部位。
图11示出了根据一个实施例的在形成一个层之后图10的聚集部位。
图12示出了根据一个实施例的带有单片分割(singulation)线的图11的聚集部位。
图13示出了根据一个实施例的在沿着单片分割线切割以形成辅表面(minor surface)之后的图12的聚集部位。
图14示出了根据一个实施例的在沿着多个侧面中的一个去除层和密封剂的一部分之后图13的聚集部位,该多个侧面在切割以暴露侧面接触接口的一部分时形成。
图15示出了根据一个实施例的在暴露侧面接触接口之后的图14的聚集部位的辅表面。
图16示出了根据一个实施例的具有另一侧面接触接口的聚集部位。
图17示出了根据一个实施例的图16的聚集部位的辅表面。
具体实施方式
在一个封装体中形成侧面接触接口。该侧面接触接口可以包括暴露在侧面或者辅表面上的导电元件。该导电元件可以能够与其它连接器(例如插座或者类似的接口部件)对准。侧面接触接口可以包括例如电阻器或者电容器以增强该封装体的性能。例如,电容器或者电阻器可以用来改进静电放电(ESD)性能或者改变阻抗。在一些实施例中,导电元件是电阻器、电容器和互连的末端的导电部分、导电插塞等或者上述元件的组合。
图1示出了根据本发明实施例的聚集部位10的截面,该聚集部位10包括电阻器16、管芯14和粘合剂12的一部分。管芯14包括接触部(contact)(例如,焊盘)13,其暴露在管芯14的一侧(即,前侧)上。电阻器16包括接触部15,其从电阻器16的一侧延伸到另一侧。在一个实施例中,粘合剂12是带。聚集部位10是面板(panel)的一部分,该面板在一个实施例中包括多个相同的聚集部位10,而在另一实施例中包括不是彼此全部相同的多个聚集部位10。通过在粘合剂12上放置已经通过例如电的、机械的或者两者都有的测试要求的管芯(即,已知的好的管芯)、分立器件等或者上述器件的组合来形成面板。例如,可以以阵列的形式来放置管芯从而形成面板。可以使用管芯的任何布置。例如,可以在格栅中布置管芯从而形成圆形,很像在晶片(wafer)上的管芯的布置。基本上重建面板以带有已知的好的管芯。如由于进一步说明而将要理解的,聚集部位10将变成一个(单独的)封装体。因此,在图1所示的实施例中,封装体将包括管芯14和电阻器16。
图2示出了根据一个实施例的在管芯14和电阻器16上方形成密封剂18之后的聚集部位10。可以使用任何市场上可买到的密封剂。例如,密封剂可以是基于环氧的和热固性的。在一个实施例中,密封剂的厚度为大约300到大约500微米。由于粘合剂12与管芯14的一侧和电阻器16的一侧接触,因此密封剂18形成在管芯14和电阻器16的不与粘合剂12接触的(五个)侧面上。在所示出的实施例中,管芯14的与密封剂18接触的五个侧面包括管芯14的除使焊盘13暴露的侧面之外的所有侧面。因此,密封剂18形成在管芯14和电阻器16的侧面上方并且紧挨着管芯14和电阻器16的侧面。因此,密封剂18形成在管芯14和电阻器16之间。
图3示出了根据一个实施例的在去除粘合剂12之后的聚集部位10。一旦形成了密封剂18,管芯14和电阻器16就通过密封剂18而物理地耦接在一起,并且因此不再需要粘合剂12。可以使用任何工艺(例如,加热(例如UV(紫外)光和IR(红外)光)、溶剂等或者上述工艺的组合)来去除粘合剂12。在去除粘合剂12之后,将聚集部位10翻转过来使得管芯14的焊盘13在上边并且被暴露。在将聚集部位10翻转过来之后,现在图中的电阻器16在管芯14的相对侧上从而示出先前示出的管芯14和电阻器16的相同侧面。
图4示出了根据一个实施例的在管芯14和电阻器16上方形成第一介电层20之后的聚集部位10。第一介电层20可以是传统的旋涂(spun-on)聚合物或者由任何合适工艺形成的任何其它合适的材料。在一个实施例中,第一介电层20可以是大约20微米厚的旋涂聚合物。
图5示出了根据一个实施例的在形成电阻器通孔22和管芯通孔24之后的聚集部位10。通过图形化和刻蚀第一介电层20以便暴露一个接触部15的至少一部分和每一焊盘13的至少一部分,来形成电阻器通孔22和管芯通孔24。在所示出的实施例中,电阻器通孔22在最接近管芯14的接触部15(即,内部接触部15)上方形成。如在进一步讨论之后将更好理解的,在所示出的实施例中不将电阻器通孔形成到另一个接触部15(即,外部接触部15)上,因为该接触部15在后续处理期间将要暴露从而形成连接器以将电阻器耦接到外部设备。
图6示出了根据一个实施例的在形成到电阻器16的接触部15的通路28以及到管芯14的管芯通路30、32和34以及互连36、38和40之后的聚集部位10。(通路是形成在通孔内的导体。)用来填充电阻器通路28和管芯通路30、32和34以及形成互连36、38和40的材料可以是任何导电材料,例如铜。可以使用任何合适的工艺(例如,化学气相淀积(CVD)、原子层淀积(ALD)、镀敷等以及上述工艺的组合)来淀积该材料从而填充通孔22和24并且在第一介电层20上方形成足够厚的材料。可以将位于电阻器通路28和管芯通路30、32和34外面以及在第一介电层20上方的材料图形化从而形成互连36、38和40。互连36通过电阻器通路28和管芯通路30而将电阻器16耦接到管芯14。互连38在进出页面的方向上行进并且可以将管芯14耦接到其它器件(未示出)。互连40向管芯14右边行进且在进出页面的方向上行进,并且可以将管芯14耦接到其它器件(未示出)。互连28和40的长度不必是相同的。本领域技术人员认识到,图6所示出的互连36、38和40仅仅是可以形成的互连的实例。
图7示出了在形成第二介电层42之后的聚集部位10。第二介电层42可以是旋涂聚合物或者其它合适的材料。第二介电层42可以是与第一介电层20相同的材料或者不同的材料,并且可以或者可以不通过与第一介电层20相同的工艺来形成。第二介电层42形成在互连36、38和40上方。在一个实施例中,第二介电层42大约20微米厚。
图8示出了根据一个实施例的在第二介电层42中形成通孔44之后的聚集部位10。可以通过图形化和刻蚀第二介电层42来形成通孔44。在所示出的实施例中,通孔44暴露互连38的至少一部分。本领域技术人员理解,通孔44可以形成在例如互连40的其它互连上方。
图9示出了根据一个实施例的在第二介电层42上方形成电阻器46之后的聚集部位10。电阻器46包括与电阻器16的接触部15类似的接触部45。可以使用拾取和放置工具来将电阻器46放置在电阻器16上方并且近似与电阻器16对齐。在该实施例中,接触部45的末端和接触部15的末端彼此近似对齐。传统的拾取和放置工具可以在预定位置的大约10微米或更小范围内放置电阻器46并且因此电阻器46和16可以基本上彼此对齐。然而,电阻器46和16可以不彼此对齐。因此,电阻器46和16可以在任何方向上相对于彼此是交错的。优选地在第二介电层42没有完全干燥时放置电阻器46。因此,第二介电层42将是粘性的或者发粘的,并且电阻器46将在没有任何附加粘合层的情况下附着于第二介电层42。
图10示出了根据一个实施例的在形成互连50之后的聚集部位10。互连50可以是任何导电材料,例如铜。在一个实施例中,为了形成互连50,(例如,通过CVD、ALD、镀敷等或者上述工艺的组合来)淀积并且随后图形化材料。互连50将电阻器46(即,它的内部接触部45)通过通路48和32、接触部14和45以及互连38而耦接到管芯14。在一个实施例中,通过将第二介电层42图形化、在聚集部位10上方形成导电材料并且将该导电材料图形化以便形成通路48,来形成通路48。在一个实施例中通路48在放置电阻器46之前形成,而在另一实施例中它在放置电阻器46之后形成。在一个实施例中,例如厚膜类型的光致抗蚀剂层可以形成在聚集部位10上方以覆盖电阻器46但是暴露接触部45,接触部45将要耦接到后来形成的互连50。光致抗蚀剂可以限定聚集部位10的轨迹线路(trace routing)。接下来,形成导电材料,例如铜。如果电阻器46例如具有陶瓷体的话,即使光致抗蚀剂层不覆盖电阻器46,该导电材料也可能不会附着于它。接下来,可以去除光致抗蚀剂以形成互连50。
图11示出了根据一个实施例的在形成层52之后的聚集部位10。层52可以通过与第二介电层42或者第一介电层20相同的工艺来形成并且具有与第二介电层42或者第一介电层20相同的材料。在一个实施例中,第三介电层20是密封剂材料。
图12示出了根据一个实施例的具有单片分割线54和56的聚集部位10。在所示出的实施例中,单片分割线54在电阻器16和46附近将聚集部位10分割成单片(singulate),但是不暴露电阻器16和46。在一个实施例中,当单片分割线54在电阻器16和46附近将聚集部位10分割成单片时,单片分割线54在电阻器16和46的最靠近边缘的0.025英寸范围内将聚集部位分割成单片。在一个实施例中,当单片分割线54在电阻器16和46附近将聚集部位10分割成单片时,该单片分割在单片分割和放置工艺的精度限制范围之内。可以由任何工艺(例如用锯、激光或者其它装置)来进行该单片分割。在所示出的实施例中,单片分割线56在管芯14附近切割聚集部位10,但是不暴露管芯14。因此,切割密封剂18(和第三介电层20(如果它是密封剂的话))以形成密封剂18(和第三介电层20(如果它是密封剂的话))的多个侧面。
图13示出了根据实施例的在沿着单片分割线54和56切割以形成辅表面64和62之后的聚集部位10。聚集部位10具有主表面58和60以及辅表面62和64。主表面58和60是彼此相对的,并且辅表面62和64是彼此相对的。在一个实施例中,主表面58是聚集部位10的顶面而主表面60是聚集部位10的底面。辅表面62和64是聚集部位10的边缘。
图14示出了根据一个实施例的在沿着多个侧面中的一个去除层52和密封剂18的一部分之后的聚集部位10,当切割以暴露侧面接触接口的一部分时形成该多个侧面。可以由各种工艺(例如用激光或者通过刻蚀去掉密封剂18和介电层52的一部分)来进行该去除步骤。在所示出的实施例中,存在两个侧面接触接口。第一侧面接触接口包括互连36、电阻器通路28和电阻器16。沿着聚集部位10的辅表面64暴露第一侧面接触接口,该聚集部位10现在是一个封装体,并且第一侧面接触接口通过管芯通路30耦接到管芯14,管芯14在五个侧面上由密封剂包围。第二侧面接触接口包括互连38、通路48、互连50和电阻器46。第二侧面接触接口通过管芯通路32耦接到管芯14。在所示出的实施例中,该侧面接触接口沿着辅表面64暴露并且通过通路耦接到器件,例如管芯14;用于耦接的任何附加的通路或者互连是该侧面接触接口的一部分。
图15示出了在暴露侧面接触接口之后的聚集部位10的辅表面64。在所示出的实施例中,在该聚集部位10(或者封装体)中存在多个电阻器46和16。因此,存在多个接触部15和45。多个接触部15和45共同形成一个连接器(或者多个连接器),该连接器可用于将封装体10耦接到其它器件。例如,封装体10可以经由该连接器耦接到蜂窝电话、电脑或者其它器件。
图16示出了根据另一实施例的具有外部互连72的聚集部位10,该聚集部位10目前是一个封装体。聚集部位10不包括电阻器16。因此,在聚集部位10中互连36没有耦接到电阻器16而是改为可以耦接到另一设备(未示出)。可替代地,互连36可能不存在。聚集部位10包括耦接到电阻器46的外部互连72。在所示出的实施例中,外部互连72通过电阻器通路70耦接到最接近聚集部位10边缘的接触部45(即,外部接触部45)。可以通过将层52图形化以形成电阻器通孔并且随后用例如铜的导电材料填充该通孔,来形成电阻器通路70和外部互连72。该导电材料形成在层52上方。然后可以将层52上方的导电材料图形化以形成外部互连72。在形成外部互连72之后,形成层74,该层74可以是任何介电层或者密封剂。在所示出的实施例中,侧面接触接口包括互连50、电阻器46(具有其接触部45)、通路70和外部互连72。在形成层74之后,与图12中一样地切割聚集部位10。如图16所示,可以切割聚集部位10以暴露外部互连72。在一个实施例中,在切割工艺期间去除外部互连72的一部分。优选的是,该切割步骤不去除电阻器46的一部分。因此,如图16所示,电阻器46和外部互连72可以是交错的。在切割聚集部位10以形成封装体之后,电介质或密封剂的部分可以不被去除。换句话说,可以不暴露电阻器46。主要部分58现在在层74(而不是层52)的上方。
图17示出了根据一个实施例的在暴露该外部互连72之后的聚集部位10的辅表面64。在该实施例中,不暴露电阻器46。(但是,在另一实施例中,电阻器46与外部互连72一起暴露。)多个外部互连72被用作连接器接口。由于电阻器46没有暴露因此该电阻器46不是连接器接口的一部分。然而,在所示出的实施例中,由于电阻器46耦接到外部互连,因此该电阻器46是连接器接口的一部分。在一个实施例中,电阻器46不存在,由此该外部互连在没有电阻器的情况下耦接到互连50。
对上述实施例的各种修改是可能的。例如,电阻器16和46可以是其它元件,例如电容器、电感器、导电插塞等或者上述元件的组合。另外,用作连接器或者连接器一部分的侧面接触接口的暴露部分可以是互连的一部分(例如,端部)。虽然图9-图15示出了两个电阻器(电阻器16和46),但是可以使用任意数目的电阻器。例如,可以仅存在一个电阻器。虽然在图9-图15中,电阻器16处于与管芯14相同的水平面或者层中,但是电阻器16也可以处于与管芯14不同的层中。例如,电阻器16可以处于在管芯14上方的层中或者管芯14可以处于在电阻器16上方的层中。类似地,虽然在图9-图15中,电阻器16和46处于不同的层中,但是它们可以处于彼此相同的层中。在图12中,选择单片分割线54使得在切割工艺之后没有暴露电阻器16和46。然而,可以选择单片分割线54使得在切割工艺之后暴露电阻器16和46。在一个实施例中,在切割工艺期间可以去除接触部15和45的一部分。在图14中,去除密封剂18和层52的一部分。在另一实施例中,去除介电层20和42的一部分以及层52和密封剂18的附加的部分。这可以使用研磨或者磨削工艺来进行从而暴露电阻器16和46的接触部15和45。虽然未示出,但是焊球或者其它外部连接可以形成在该封装体的主表面58和60或者辅表面62和64上。在一个实施例中,由于侧面接触接口在封装体外是比焊球短的电路径,因此焊球形成在主表面60上并且侧面接触接口耦接到天线。另外,可以在该封装体中形成任意数目的管芯、分立器件(例如,电阻器等)、导电插塞等或者上述器件的组合。在图中示出的电阻器和管芯的数目仅仅出于示例的目的。因此,在该封装体中可以仅仅形成一个管芯并且该管芯具有侧面接触接口,该侧面接触接口可以或者可以不包括分立器件,例如电阻器。此外,应当理解,侧面接触接口相对于辅表面64或62可以是齐平的或者凹进去的。另外,如果存在多于一个的侧面接触接口,则每一个都可以是齐平的或者凹进去任何距离的,并且它们不必全部都是齐平的或者凹进去相同距离的。此外,虽然仅仅示出了侧面接触接口暴露在辅表面62上,但是侧面接触接口也可以可替代地暴露在辅表面64上,或者除暴露在辅表面62上的那些之外还暴露在辅表面64上。
本领域技术人员认识到,所示出的侧面接触接口仅仅是各种侧面接触接口的实例。通常,侧面接触接口暴露在该封装体的辅表面上。侧面接触接口可以用互连、电阻器、电容器、电感器、插塞等等终止。侧面接触接口供在封装体的边缘的电连接用。侧面接触接口耦接到在封装体内的器件并且能够耦接到外部器件。例如,用户可以将外部器件插到侧面接触接口中。
至此应当明白,已经提供了一种使用建造封装体的构建(build-up)技术在封装体内制造和嵌入连接器或者电接口的低成本方法。由于在一个或多个层之中将互连布线或者再分布从而使封装体的面积最小化,因此由此产生的封装体可以是再分布的芯片封装体(RCP)。不需要引线接合(wirebonding)或者传统的基底(引线框或者封装基底)来形成RCP。这增大了产量并且减少成本。
在前述说明书中,已经参考具体实施例而描述了本发明。然而,本领域技术人员明白,在不脱离如下面权利要求中所述的本发明范围的情况下可以进行各种修改和变化。因此,说明书和附图要被当作是示例性的而不是限制性的,并且所有这样的修改意图包括在本发明范围内。
好处、优点、问题的解决方案和任何可以促使任何好处、优点或解决方案出现或变得更显著的要素不要被看作是任何或全部权利要求的关键的、必需的或者本质的特征或要素。如在此使用的术语“一”或者“一个”定义为一个或多于一个,即使在权利要求或者说明书中清楚地陈述了其它元件为一个或多个。如在此使用的术语“多个”定义为两个或多于两个。如在此使用的术语“另一个”定义为至少第二个或者更多个。如在此使用的术语“耦接”定义为连接,然而不一定是直接地连接并且不一定是机械地连接。此外,在描述中和在权利要求中的术语“前面”、“后面”、“顶面”、“底面”、“在......上方”、“在......下面”等等,如果有的话,是用于描述的目的的而不一定用于描述固定不变的相对位置。应当理解,这样使用的术语在适当的情况下是可互换的,使得在此所述的本发明实施例例如能够在除在此所示出或所描述的那些方向之外的其它方向上运行。
Claims (19)
1.一种封装器件的方法,包含以下步骤:
在第一器件的第二主表面上方以及围绕第一器件的侧面形成密封剂,并且保留第一器件的第一主表面被暴露;
在第一器件的第一主表面上方形成第一介电层;
形成侧面接触接口,所述侧面接触接口至少有一部分在第一介电层上方;
切割所述密封剂从而形成所述密封剂的多个侧面;以及
沿着所述多个侧面中的第一侧面去除所述密封剂的一部分从而沿着所述多个侧面的所述第一侧面暴露所述侧面接触接口的一部分。
2.根据权利要求1的方法,进一步包含以下步骤:
在形成密封剂的步骤之前将带敷设到第一主表面;以及
在形成第一介电层的步骤之前去除所述带。
3.根据权利要求1的方法,进一步包含以下步骤:
在形成第一介电层的步骤之后,在第一介电层中形成到第一器件的第一接触部的第一通路;
其中形成侧面接触接口的步骤的特征进一步在于:所述侧面接触接口在第一通路和所述多个侧面的第一侧面之间包含第一互连。
4.根据权利要求3的方法,其中形成侧面接触接口的步骤的特征进一步在于:所述侧面接触接口还在所述互连和所述多个侧面的第一侧面之间包含第二器件。
5.根据权利要求4的方法,其中形成侧面接触接口的步骤的特征进一步在于:
形成在第二器件的第一接触部和所述第一互连之间穿过第一介 电层的第二通路。
6.根据权利要求4的方法,其中形成侧面接触接口的步骤的特征进一步在于:第二器件形成在第一介电层上方。
7.根据权利要求4的方法,其中形成第一介电层的步骤的特征进一步在于:所述第一介电层形成在第二器件上方。
8.根据权利要求1的方法,其中形成密封剂的步骤的特征进一步在于:所述密封剂是基于环氧的和热固性的。
9.根据权利要求1的方法,其中形成第一介电层的步骤的特征进一步在于:所述第一介电层是聚合物电介质。
10.一种封装器件的方法,包含以下步骤:
将带敷设到第一器件的第一主表面;
形成密封剂以提供处理第一器件的物理支撑,所述密封剂在第一器件的第二主表面上方并且围绕第一器件的侧面;
在形成所述密封剂之后从第一主表面上去除所述带;
在第一器件的第一主表面上方淀积第一介电层,所述第一介电层是聚合物电介质;
形成侧面接触接口,所述侧面接触接口至少有一部分在第一介电层上方;
切割所述密封剂从而形成所述密封剂的多个侧面;以及
沿着所述多个侧面中的第一侧面去除所述密封剂的一部分从而沿着所述多个侧面的所述第一侧面暴露所述侧面接触接口的一部分。
11.根据权利要求10的方法,其中敷设带的步骤的特征进一步在于:第一器件具有接触部,该方法进一步包含以下步骤:
刻蚀穿过第一介电层的通孔;以及
在所述通孔中形成导体作为通路,其中所述通路接触所述侧面接触接口和第一器件的所述接触部。
12.根据权利要求11的方法,其中形成侧面接触接口的步骤的特征进一步在于:所述侧面接触接口包含连接在所述通路和所述多个侧面的第一侧面之间的第二器件。
13.根据权利要求12的方法,其中去除所述密封剂的一部分的步骤的特征进一步在于:暴露第二器件的接触部。
14.根据权利要求10的方法,其中:
形成侧面接触接口的步骤的特征进一步在于:所述侧面接触接口包含延伸到第一侧面的互连层;以及
去除所述密封剂的一部分的步骤的特征进一步在于:暴露所述互连层的端部。
15.根据权利要求10的方法,进一步包含:在所述侧面接触接口上方形成第二介电层。
16.根据权利要求10的方法,其中将带敷设到第一器件的第一主表面的步骤的特征进一步在于:第一器件是半导体管芯。
17.一种封装器件的方法,包含以下步骤:
将具有粘性的带敷设到第一器件的第一主表面和第二器件的第一主表面,其中第一器件沿着第一主表面具有第一接触部,并且第二器件具有第一接触部和第二接触部;
在第一器件的第二主表面和第二器件的第二主表面上方以及沿着第一和第二器件的侧面形成密封剂,其中所述密封剂具有在第一和 第二器件的第二主表面上方的第一主表面以及与所述第一主表面相对的第二主表面;
去除所述带;
在第一器件的第一主表面和第二器件的第一主表面上方形成第一介电层;
在第一介电层中形成第一通孔和第二通孔;
形成 第一导体,所述第一导体从第一器件的第一接触部穿过第一和第二通孔到第二器件的第一接触部;
切割所述密封剂从而在所述密封剂的第一和第二主表面之间形成密封剂的多个侧面;以及
沿着所述多个侧面中的第一侧面去除所述密封剂的一部分从而沿着所述多个侧面的所述第一侧面暴露第二器件的第二接触部。
18.根据权利要求17的方法,其中第一器件是半导体管芯并且第二器件包含电阻器。
19.根据权利要求17的方法,其中第一器件具有第二接触部,该方法进一步包含以下步骤:
在第一介电层上方形成第三器件,其中所述第三器件具有第一接触部和第二接触部;
在第一介电层和第三器件上方形成第二介电层;
形成穿过第一介电层的第三通路;
形成穿过第二介电层的第四通路;以及
形成第二导体,所述第二导体从第一器件的第二接触部穿过第三和第四通路到达第三器件的第一接触部;
其中去除所述密封剂的一部分的步骤的特征进一步在于:沿着所述密封剂的第一侧面暴露第三器件的第二接触部。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/561,241 | 2006-11-17 | ||
US11/561,241 US7476563B2 (en) | 2006-11-17 | 2006-11-17 | Method of packaging a device using a dielectric layer |
PCT/US2007/080523 WO2008063761A2 (en) | 2006-11-17 | 2007-10-05 | Method of packaging a device using a dielectric layer |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101530012A CN101530012A (zh) | 2009-09-09 |
CN101530012B true CN101530012B (zh) | 2012-07-04 |
Family
ID=39417421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007800395574A Active CN101530012B (zh) | 2006-11-17 | 2007-10-05 | 使用介电层封装器件的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7476563B2 (zh) |
JP (1) | JP2010510665A (zh) |
CN (1) | CN101530012B (zh) |
TW (1) | TWI415240B (zh) |
WO (1) | WO2008063761A2 (zh) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
US8035216B2 (en) * | 2008-02-22 | 2011-10-11 | Intel Corporation | Integrated circuit package and method of manufacturing same |
US20100148357A1 (en) * | 2008-12-16 | 2010-06-17 | Freescale Semiconductor, Inc. | Method of packaging integrated circuit dies with thermal dissipation capability |
JP2010219489A (ja) * | 2009-02-20 | 2010-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | 晶片封裝結構及其製造方法 |
TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
TWI405306B (zh) * | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體 |
US8053898B2 (en) * | 2009-10-05 | 2011-11-08 | Samsung Electronics Co., Ltd. | Connection for off-chip electrostatic discharge protection |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US20110108999A1 (en) * | 2009-11-06 | 2011-05-12 | Nalla Ravi K | Microelectronic package and method of manufacturing same |
US8378466B2 (en) * | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8327532B2 (en) * | 2009-11-23 | 2012-12-11 | Freescale Semiconductor, Inc. | Method for releasing a microelectronic assembly from a carrier substrate |
TWI497679B (zh) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8901724B2 (en) | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
US8742561B2 (en) | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8372689B2 (en) * | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
US8320134B2 (en) * | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
TWI411075B (zh) * | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8319318B2 (en) | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US8618652B2 (en) | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
US8939347B2 (en) | 2010-04-28 | 2015-01-27 | Intel Corporation | Magnetic intermetallic compound interconnect |
US9847308B2 (en) | 2010-04-28 | 2017-12-19 | Intel Corporation | Magnetic intermetallic compound interconnect |
US8434668B2 (en) | 2010-05-12 | 2013-05-07 | Intel Corporation | Magnetic attachment structure |
US8313958B2 (en) | 2010-05-12 | 2012-11-20 | Intel Corporation | Magnetic microelectronic device attachment |
US8609532B2 (en) | 2010-05-26 | 2013-12-17 | Intel Corporation | Magnetically sintered conductive via |
US20120001339A1 (en) | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8372666B2 (en) | 2010-07-06 | 2013-02-12 | Intel Corporation | Misalignment correction for embedded microelectronic die applications |
US8754516B2 (en) | 2010-08-26 | 2014-06-17 | Intel Corporation | Bumpless build-up layer package with pre-stacked microelectronic devices |
US8304913B2 (en) | 2010-09-24 | 2012-11-06 | Intel Corporation | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US8937382B2 (en) | 2011-06-27 | 2015-01-20 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
US8848380B2 (en) | 2011-06-30 | 2014-09-30 | Intel Corporation | Bumpless build-up layer package warpage reduction |
WO2013089754A1 (en) * | 2011-12-15 | 2013-06-20 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (bbul) packages |
US9257368B2 (en) | 2012-05-14 | 2016-02-09 | Intel Corporation | Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias |
CN104321864B (zh) | 2012-06-08 | 2017-06-20 | 英特尔公司 | 具有非共面的、包封的微电子器件和无焊内建层的微电子封装 |
US8822268B1 (en) * | 2013-07-17 | 2014-09-02 | Freescale Semiconductor, Inc. | Redistributed chip packages containing multiple components and methods for the fabrication thereof |
US9134366B2 (en) | 2013-08-27 | 2015-09-15 | Freescale Semiconductor, Inc. | Method for forming a packaged semiconductor device |
JP6249578B2 (ja) * | 2014-07-28 | 2017-12-20 | インテル・コーポレーション | 密なパッケージ配線を有するマルチチップモジュールの半導体チップパッケージ |
US10217724B2 (en) | 2015-03-30 | 2019-02-26 | Mediatek Inc. | Semiconductor package assembly with embedded IPD |
US20170040266A1 (en) | 2015-05-05 | 2017-02-09 | Mediatek Inc. | Fan-out package structure including antenna |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6407929B1 (en) * | 2000-06-29 | 2002-06-18 | Intel Corporation | Electronic package having embedded capacitors and method of fabrication therefor |
US6628526B1 (en) * | 1999-07-13 | 2003-09-30 | Taiyo Yuden Co., Ltd. | Electronic device manufacturing method, electronic device and resin filling method |
CN1856878A (zh) * | 2003-09-25 | 2006-11-01 | 飞思卡尔半导体公司 | 形成半导体封装的方法及其结构 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4088546A (en) | 1977-03-01 | 1978-05-09 | Westinghouse Electric Corp. | Method of electroplating interconnections |
US5829128A (en) | 1993-11-16 | 1998-11-03 | Formfactor, Inc. | Method of mounting resilient contact structures to semiconductor devices |
US5250843A (en) | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US6400573B1 (en) | 1993-02-09 | 2002-06-04 | Texas Instruments Incorporated | Multi-chip integrated circuit module |
US6153929A (en) | 1998-08-21 | 2000-11-28 | Micron Technology, Inc. | Low profile multi-IC package connector |
US6271060B1 (en) | 1999-09-13 | 2001-08-07 | Vishay Intertechnology, Inc. | Process of fabricating a chip scale surface mount package for semiconductor device |
KR100462980B1 (ko) | 1999-09-13 | 2004-12-23 | 비쉐이 메저먼츠 그룹, 인코포레이티드 | 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정 |
US6316287B1 (en) | 1999-09-13 | 2001-11-13 | Vishay Intertechnology, Inc. | Chip scale surface mount packages for semiconductor device and process of fabricating the same |
US6586836B1 (en) | 2000-03-01 | 2003-07-01 | Intel Corporation | Process for forming microelectronic packages and intermediate structures formed therewith |
US6890829B2 (en) * | 2000-10-24 | 2005-05-10 | Intel Corporation | Fabrication of on-package and on-chip structure using build-up layer process |
US6825552B2 (en) | 2001-05-09 | 2004-11-30 | Tessera, Inc. | Connection components with anisotropic conductive material interconnection |
JP2004039897A (ja) | 2002-07-04 | 2004-02-05 | Toshiba Corp | 電子デバイスの接続方法 |
US6921860B2 (en) | 2003-03-18 | 2005-07-26 | Micron Technology, Inc. | Microelectronic component assemblies having exposed contacts |
US6921975B2 (en) | 2003-04-18 | 2005-07-26 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging, exposed active surface and a voltage reference plane |
US6838776B2 (en) | 2003-04-18 | 2005-01-04 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging and method for forming |
US7015075B2 (en) | 2004-02-09 | 2006-03-21 | Freescale Semiconuctor, Inc. | Die encapsulation using a porous carrier |
US7345359B2 (en) | 2004-03-05 | 2008-03-18 | Intel Corporation | Integrated circuit package with chip-side signal connections |
US20050242425A1 (en) | 2004-04-30 | 2005-11-03 | Leal George R | Semiconductor device with a protected active die region and method therefor |
-
2006
- 2006-11-17 US US11/561,241 patent/US7476563B2/en active Active
-
2007
- 2007-10-05 JP JP2009537256A patent/JP2010510665A/ja not_active Withdrawn
- 2007-10-05 WO PCT/US2007/080523 patent/WO2008063761A2/en active Application Filing
- 2007-10-05 CN CN2007800395574A patent/CN101530012B/zh active Active
- 2007-10-22 TW TW096139517A patent/TWI415240B/zh active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6628526B1 (en) * | 1999-07-13 | 2003-09-30 | Taiyo Yuden Co., Ltd. | Electronic device manufacturing method, electronic device and resin filling method |
US6407929B1 (en) * | 2000-06-29 | 2002-06-18 | Intel Corporation | Electronic package having embedded capacitors and method of fabrication therefor |
CN1856878A (zh) * | 2003-09-25 | 2006-11-01 | 飞思卡尔半导体公司 | 形成半导体封装的方法及其结构 |
Also Published As
Publication number | Publication date |
---|---|
TWI415240B (zh) | 2013-11-11 |
WO2008063761A2 (en) | 2008-05-29 |
CN101530012A (zh) | 2009-09-09 |
TW200832665A (en) | 2008-08-01 |
US20080119013A1 (en) | 2008-05-22 |
US7476563B2 (en) | 2009-01-13 |
JP2010510665A (ja) | 2010-04-02 |
WO2008063761A3 (en) | 2008-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101530012B (zh) | 使用介电层封装器件的方法 | |
CN103681367B (zh) | 封装方法和封装器件 | |
US7245021B2 (en) | Micropede stacked die component assembly | |
CN103383923B (zh) | 用于应用处理器和存储器集成的薄3d扇出嵌入式晶片级封装(ewlb) | |
US7884486B2 (en) | Chip-stacked package structure and method for manufacturing the same | |
JP5615936B2 (ja) | パネルベースのリードフレームパッケージング方法及び装置 | |
CN106549004A (zh) | 具有对准标记的集成电路管芯及其形成方法 | |
KR101801137B1 (ko) | 반도체 장치 및 그 제조 방법 | |
CN102969252A (zh) | 利用具有附接的信号管道的引线框架的具有包封前穿通通孔形成的半导体装置封装 | |
CN103779235A (zh) | 扇出晶圆级封装结构 | |
CN1947247A (zh) | 通用互连芯片 | |
CN103579204A (zh) | 包括电容器的封装结构及其形成方法 | |
CN109003963B (zh) | 半导体封装及制造其的方法 | |
TW201631701A (zh) | 以聚合物部件爲主的互連體 | |
CN103681533A (zh) | 包括块体金属的扇出封装件 | |
CN112864138A (zh) | 半导体封装结构、半导体设备封装和其制造方法 | |
CN105097720A (zh) | 封装结构的形成方法 | |
US10020284B2 (en) | Functional spacer for SIP and methods for forming the same | |
US10818616B2 (en) | Semiconductor package structure and method for forming the same | |
CN104659019A (zh) | 扇出式封装结构及其形成方法 | |
CN102945840A (zh) | 半导体芯片封装结构及封装方法 | |
CN110739292A (zh) | 一种3d封装结构及其制作方法 | |
US8685860B2 (en) | Semiconductor structure and manufacturing method thereof | |
CN115250569B (zh) | 一种高频线路板及其制备方法 | |
CN102254840A (zh) | 半导体结构及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: NXP America Co Ltd Address before: Texas in the United States Patentee before: Fisical Semiconductor Inc. |
|
CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180129 Address after: Delaware Patentee after: VLSI Technology Co., Ltd. Address before: Texas in the United States Patentee before: NXP America Co Ltd |
|
TR01 | Transfer of patent right |