CN100397645C - 具有增强钝化层之集成电路 - Google Patents
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract
一种具有增强钝化层之集成电路，在一实施例中，集成电路具有半导体基板，多层内连线结构形成于基板之上，以及多层钝化层结构覆盖多层内连线结构。多层内连线结构中至少有一个金属线具有渐缩之轮廓。
Description
技术领域
本发明涉及一种微电子元件及其制造方法，且特别涉及一种微电子元件以COG技术包装。
背景技术
玻璃上有芯片(Chip On Glass，COG)运用异向导电薄膜(AnisotropicConductive Film，ACF)以固定集成电路(Integrated Circuit，IC)芯片于玻璃之上。例如，COG已经广泛的使用在液晶驱动集成电路(Liquid Crystal Driving IC，LDI)上已将LDI直接黏结于液晶显示器的玻璃基板之上。
然而，在ACF中的酸性物质会通过覆盖在顶端金属线之上的钝化层的缺陷侵蚀金属导线而导致集成电路的失效，特别是在质量和可靠度测试的温度周期之后。
据此，本技术领域需要提供一种集成电路元件及其制造方法来解决上述的问题。
发明内容
本发明的目的是提供一种具有增强钝化层之集成电路，在一实施例中，集成电路具有半导体基板，多层内连线结构形成于基板之上，以及多层钝化层结构覆盖多层内连线结构。多层内连线结构中至少有一个金属线具有渐缩之轮廓。
因此，本发明即通过以下之披露来提供许多不同的实施例，例如，在不同实施例中置入不同特征。下述元件及安排的特别例子可用来简化披露，因此，仅数个例子当不应被视为限制。另外，在披露中不同的例子会使用相同的标号和文字，重复使用标号和文字仅为了简化和清晰的目的，而非规定了在不同实施例且/或讨论轮廓间的关系。
附图说明
为让本发明之上述和其它目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合附图，作详细说明如下。必须强调的是，根据行业习惯，不同结构并未依尺寸表示。事实上，各特征的尺寸可为了讨论的清晰而任意增减。
图1为实施例的示范集成电路100的剖面示意图。
图2为LCD元件20的实施例的剖面示意图。
图3为实施例中IC芯片故障率的表300。
元件标记说明
100：集成电路
110：半导体基板
120：顶端金属层
122：侧外缘
140：钝化结构
142、144、146：钝化层
200：LCD元件
210：IC芯片
214：凸起形状
220：LCD玻璃基板
222、224：玻璃电极
225、226：导垫结构
230：上玻璃
235：传导层跨接结构
300：表
310：故障率
320：测试形态
330：传统IC芯片
340：具有渐缩轮廓顶端金属线之IC芯片
350：同时具有渐缩轮廓顶端金属线及三层钝化层之IC芯片
360：ACF固定之前且未经过温度周期
370：ACF固定之前且经过温度周期
380：ACF固定之后且经过温度周期
具体实施方式
图1为一实施例的示范集成电路100的剖面示意图。集成电路100包括半导体基板110。半导体基板110能使用元素态之半导体，如结晶硅、多晶硅、非晶硅、锗和钻石；也能使用半导体化合物，如碳化硅或是砷化镓；或是半导体合金，如硅锗化物、磷砷化镓、砷化铟铝、砷化铟镓、磷化铟镓或其任意组合。
半导体基板110还包括以半导体制造工艺技术形成电子元件于半导体基板之上。这些位于基板上之电子元件可通过不同的技术，例如绝缘隔离(例如硅的区域氧化LOCOS和浅沟渠隔离STI)、接面隔离和区域隔离，来进行逐一的隔离。电子元件可以包括，但不仅限于此；无源元件，例如电阻、电容和电感；有源元件，例如金氧半导体场效晶体管(MOSFETs)、二极管、高压晶体管、高频晶体管、存储单元或其任意之组合。所涵盖的半导体制造技术包括互补式金氧半导体(CMOS)技术、二极和互补式金氧半导体(BiCMOS)技术，或是二极管，互补式金氧半导体及双扩散金氧半导体(DMOS)技术，这称之为BSD，或是其它适当的制造工艺技术。
半导体基板110可更进一步包括多层内连线来连结电子元件以形成功能电路。如此形成的功能集成电路可以有不同的用途。例如，集成电路可当液晶显示器的驱动IC，这称之为LDI。集成电路可用于具有COG包装之应用。多层内连线可包括应用在0.18微米或较大尺寸技术之铝、铝硅铜合金、钛、氮化钛、钨、多晶硅、金属硅化物或其任意组合。铝金属内连线可通过溅镀、化学气相沉积或其任意组合而形成。其它制造工艺，包括微影和蚀刻也可用来图案化金属材质而形成垂直(界层窗和接触窗)和水平(金属导线)连结。另有其它制造工艺例如淬火可用来形成金属硅化物。铜多层内连线可包括应用在0.18微米或较小尺寸技术之铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物或其任意组合。铜多层内连线可通过双金属镶嵌制造工艺来形成。适用于金属内联机内连线的金属硅化物包括硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯、或其任意组合。多层内联机内连线可通过内层介电层夹层电介质(Interlevel Dielectric，ILD)来进行彼此的隔离。内层介电层夹层电介质可包括二氧化硅、掺氟硅酸玻璃(FSG)、聚酰胺、旋涂玻璃(SOG)、黑钻石(Black
加州圣塔克拉拉应用材料公司的产品)、静电胶(Xerogel)、游离胶(Aerogel)、非晶硅氟化碳、二甲苯塑料(Parylene)、BCB、Flare、SiLK、且/或其它材料。而这些材料可由化学气相沉积、原子层沉积、物理气相沉积、旋涂或其它制造工艺所制得。
集成电路100还包括顶端金属层120。顶端金属层120可视为多层内连线的一部份。制造顶端金属层的方法和所使用的材料实质上和前述形成多层内连线的方法和材料相似。例如，顶端金属层120可包括由溅镀形成之铝/铜/硅合金。顶端金属层可进一步包括钛和氮化钛覆盖在铝金属层之上作为黏着层和扩散阻障层。氮化钛具有抗反射膜层的功能，亦可在后续图案化顶端金属层的微影制造工艺中提升分辨率。
顶端金属层120的导线具有渐缩的剖面轮廓。顶端金属层120的导线具有顶宽L1及底宽L2，其中顶宽L1小于底宽L2。在一实施例中，顶宽L1约小于等于底宽L2的90％。在另一实施例中，渐缩的轮廓由顶端金属层120的导线之一侧外缘122的倾斜角度所定义。侧外缘122的底部具有大于3度自垂直线向内倾斜的角度。渐缩顶端金属线通过前述之方法形成。例如，铝金属线可通过调整蚀刻制造工艺参数来制造成具有渐缩之轮廓，蚀刻制造工艺参数可以为湿式蚀刻之内容物及溶液蚀刻选择率或是干式蚀刻中的蚀刻气体。在另一实施例中则是使用双金属镶嵌制造工艺，在夹层电介质中以蚀刻形成渐缩之沟渠，然后以铜回填。夹层电介质是先进行湿式蚀刻，再以干式蚀刻以变化蚀刻方法和调整蚀刻参数的方式进行蚀刻。
集成电路100还可包括钝化结构140，其中钝化结构140具有三层钝化层，分别为第一钝化层142、第二钝化层144和第三钝化层146。第一钝化层142和顶端金属层120直接接触。第二钝化层144覆盖于第一钝化层142的上方。第三钝化层146覆盖于第二钝化层144的上方。钝化结构140可以保护位于其下方的元件，包括多层内连线，避免污染和湿气。
一实施例披露了以下的例子。第一钝化层142可以包括氧化硅。氧化硅例如可以为化学气相沉积之磷掺杂玻璃。第二钝化层144可以包括氮化硅。氮化硅可以由化学气相沉积，例如等离子体增强化学气相沉积所形成。在另一实施例中，第二钝化层可以包括氮氧化硅。第三钝化层146可以包括氧化硅。第三钝化层的氧化硅和第一钝化层的氧化硅在沉积制造工艺和材料上实质相似。第三钝化层可以使用低应力且具有好的密封功能的物质。在本实施例中，金属线间沟渠的宽度在转弯之转角处是一般沟渠宽度的1.4倍。三层钝化层的厚度总和约为相邻两顶端金属线之沟渠宽度的0.7倍。这个厚度能确保填入沟渠且具有实质平坦的钝化层表面。
钝化结构140可以具有多个开口以暴露出一组特定的金属图案，例如接触垫。对于这些应用例如COG、凸起下金属化(Under-Bump-Metallization，UBM)可进一步形成在接触垫之上。
公知钝化结构只有两层，例如氧化硅作为底钝化层而氮化硅作为顶钝化层。氮化硅层具有高应力而会导致裂开，更进一步而言，公知顶端金属线在沟渠的底部会有底切的特征。底切金属轮廓会导致钝化层的阶梯覆盖较差。较差的阶梯覆盖力再加上氮化硅的本质高应力会导致钝化结构的失效而丧失钝化层密封的功能。这样常在严苛的环境下和质量/可性度测试例如温度周期，而被加速。这样失效的一个例子就是LDI芯片运用COG技术中之ACF来附着于玻璃基板之上。来自ACF的酸性物质会穿透钝化层的缺陷而损伤LDI芯片，因而导致功能失效。
在本实施例中披露，渐缩轮廓之顶端金属线可增强钝化结构对两顶端金属线间之沟渠底部转角之阶梯覆盖能力，减少钝化结构缺陷及强化钝化结构。进一步而言，第三钝化层在前两钝化层形成之后填入两金属线间的沟渠，可以提供实质上平坦的表面以及较强的密封效果以保护位于其下的金属结构避免湿气、污染和酸。因为第三钝化层有足够的厚度填入两金属线间的沟渠且应力较氮化硅低，钝化结构实质上被强化了。渐缩金属轮廓和三层钝化结构可根据应用上之质量和可性度的需求分别或一起被引入。
图2为LCD元件200的实施例的剖面示意图，图1中的集成电路100亦可存在。LCD元件200仅为运用具有增强钝化结构之集成电路100的一个例子。LCD元件200包括具有类似图1所示之集成电路100的IC芯片210。IC芯片210可具有渐缩顶端金属线、三层钝化结构或两者均有。IC芯片210可以为LCD驱动IC。IC芯片210还可以包括凸起形状214。凸起形状214可具有不同金属的多层，例如黏着层、扩散阻障层、可焊接层和氧化阻障层。凸起形状可包括钛、铬、铝、铜、镍、钒、金或其任意组合。
LCD元件200包括LCD玻璃基板220和上玻璃230。LCD玻璃基板220可具有两个玻璃电极222和224形成于玻璃基板之上以控制液晶单元。液晶物质填充并密封于LCD玻璃基板220和上玻璃230之间。LCD玻璃基板220和上玻璃230包括透明或半透明之玻璃，以及每一个可进一步包括偏极化层和配向层(未标示于图上)。玻璃电极经过图案化后和每一个液晶单元连结以控制液晶单元的显示功能。玻璃电极222和224可包括透明导电物质，例如氧化铟锡。位于上玻璃230的玻璃电极可通过传导层跨接结构23 5或多个传导跨接结构电性导接到LCD玻璃基板220。玻璃电极可包括导垫结构226的设置以作为IV芯片的接合。
IC芯片210可使用ACF240通过凸起214和导垫结构226固定于LCD玻璃基板220之上。ACF为热设定环氧树酯系统，包括导电颗粒均匀分布在非导电黏着层之内。
LCD元件200可进一步包括柔性电路板(Flexible Printed Circuit，FPC)250通过另一导垫结构225连结在玻璃基板220的玻璃电极224的一端，而连结装置例如显示控制器在玻璃电极224的另一端。
可了解的是LCD元件200显现了集成电路100(也包括IC芯片210)各种应用可能性其中之一。具有增强钝化结构之集成电路100可用于其它包括ACF且/或COG技术的元件且/或系统。集成电路100更能延伸适用到需要增强钝化结构的应用环境。
图3为实施例中IC芯片故障率的表300。表300显示由实验数据中所撷取的一组故障率。故障率310由失效样品数与总样品数的比值所定义。是否失效则由功能测试所定义。测试形态320包括温度周期。IC芯片的实验样品包括三组：传统IC芯片330、具有渐缩轮廓顶端金属线之IC芯片340和同时具有渐缩轮廓顶端金属线及三层钝化层之IC芯片350。故障率是收集自每一组样品在组装或测试的不同阶段，包括ACF固定之前且未经过温度周期360、ACF固定之前且经过温度周期370以及ACF固定之后且经过温度周期380。如实验数据所示，所有的失效均发生在ACF固定之后。由于热应力周期使温度周期加速芯片的失效。传统IC芯片330有30％的故障率。具有渐缩轮廓顶端金属线之IC芯片340有12％的故障率。同时具有渐缩轮廓顶端金属线及三层钝化层之IC芯片350的故障率为0。据此，同时具有渐缩轮廓顶端金属线及三层钝化层可最小化或使故障率为0。
虽然本发明已以较佳实施例披露如上，然其并非用以限定本发明，任何所属本技术领域的技术人员，在不脱离本发明之精神和范围内，当可作各种更动、取代与改进，因此本发明之保护范围当以后附之权利要求所界定为准。
Claims (8)
1.一种集成电路，其特征在于至少包含：
半导体基板；
多层内连线结构形成于上述基板之上，且该多层内连线结构具有至少两个相临之顶端金属线，其中该两个顶端金属线分别呈渐缩轮廓，并以沟渠相隔；以及
多层钝化层结构覆盖该两个顶端金属线，该多层钝化层结构包括：
第一氧化硅层与该两个顶端金属线直接接触；
一钝化层位于该第一氧化硅层之上，该钝化层为氧化硅层或氮氧化硅层；以及
第二氧化硅层位于该钝化层之上，其中该第二氧化硅层填满该沟渠。
2.根据权利要求1所述之集成电路，其特征在于上述渐缩轮廓由上述顶端金属线之上宽与下宽之比小于90％所界定。
3.根据权利要求1项所述之集成电路，其特征在于上述顶端金属线包括铝合金、钛、氮化钛、铜、铜合金、钽、氮化钽及其任意组合。
4.根据权利要求1项所述之集成电路，其特征在于上述第一氧化硅层、该钝化层及该第二氧化硅层的厚度大于上述顶端金属线间沟渠宽度的0.7倍。
5.根据权利要求1所述之集成电路，其特征在于上述集成电路是采用玻璃上有芯片技术所包装。
6.根据权利要求5所述之集成电路，其特征在于上述玻璃上有芯片技术采用异向导电薄膜结合集成电路至玻璃上。
7.根据权利要求1所述之集成电路，其特征在于上述集成电路还包括液晶显示驱动模块。
8.根据权利要求1所述之集成电路，其特征在于形成上述半导体基板的材质选自于硅、锗、钻石、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、硅锗化物、磷砷化镓、砷化铟铝、砷化铟镓、磷化铟镓和磷砷化铟镓所组成之族群。
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| US7960835B2 (en) * | 2009-05-04 | 2011-06-14 | Macronix International Co., Ltd. | Fabrication of metal film stacks having improved bottom critical dimension |
| US9209102B2 (en) | 2012-06-29 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation structure and method of making the same |
| US20140069696A1 (en) * | 2012-09-11 | 2014-03-13 | Apple Inc. | Methods and apparatus for attaching multi-layer flex circuits to substrates |
| CN104103590B (zh) * | 2013-04-15 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
| CN108227268B (zh) * | 2018-01-31 | 2020-12-22 | 武汉华星光电技术有限公司 | 液晶显示装置的制作方法及液晶显示装置 |
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| US6017614A (en) * | 1997-07-14 | 2000-01-25 | Vanguard International Semiconductor Corporation | Plasma-enhanced chemical vapor deposited SIO2 /SI3 N4 multilayer passivation layer for semiconductor applications |
| US6657299B2 (en) * | 2001-11-28 | 2003-12-02 | Dongbu Electronics Co., Ltd. | Semiconductor with a stress reduction layer and manufacturing method therefor |
| CN1476072A (zh) * | 2002-08-12 | 2004-02-18 | ������������ʽ���� | 半导体器件 |
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| US6017614A (en) * | 1997-07-14 | 2000-01-25 | Vanguard International Semiconductor Corporation | Plasma-enhanced chemical vapor deposited SIO2 /SI3 N4 multilayer passivation layer for semiconductor applications |
| US6657299B2 (en) * | 2001-11-28 | 2003-12-02 | Dongbu Electronics Co., Ltd. | Semiconductor with a stress reduction layer and manufacturing method therefor |
| CN1476072A (zh) * | 2002-08-12 | 2004-02-18 | ������������ʽ���� | 半导体器件 |
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