CN100530582C - 半导体装置及其形成方法 - Google Patents

半导体装置及其形成方法 Download PDF

Info

Publication number
CN100530582C
CN100530582C CNB2007101081858A CN200710108185A CN100530582C CN 100530582 C CN100530582 C CN 100530582C CN B2007101081858 A CNB2007101081858 A CN B2007101081858A CN 200710108185 A CN200710108185 A CN 200710108185A CN 100530582 C CN100530582 C CN 100530582C
Authority
CN
China
Prior art keywords
connector
layer
intensity
internal connection
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2007101081858A
Other languages
English (en)
Other versions
CN101097875A (zh
Inventor
黄泰钧
姚志翔
夏劲秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101097875A publication Critical patent/CN101097875A/zh
Application granted granted Critical
Publication of CN100530582C publication Critical patent/CN100530582C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种半导体装置及其形成方法，该形成方法包括：提供基底，该基底上方具有介电层；在该介电层中形成多个内连线结构，所述多个内连线结构堆叠而成，各个内连线结构包括导电层及插塞层，该导电层连接该插塞层；在所述多个内连线结构上方形成连接垫结构，该连接垫结构具有凸块预定区；以及在至少一插塞层中形成裂缝停止物，该裂缝停止物沿着该凸块预定区的投影区域的边缘形成。本发明可克服现有技术的连接垫结构中易产生裂缝等缺点，且可改善制造工艺。

Description

半导体装置及其形成方法
技术领域
本发明涉及一种半导体装置，特别涉及一种具有连接垫(bonding pad)结构的半导体装置。
背景技术
随着电子元件的制作日益缩小，目前已发展出各种减少芯片与印刷电路板之间的连接空间的方法，其中芯片包含集成电路装置，且芯片固定(mounted)于印刷电路板上。一般而言，芯片上的集成电路与印刷电路板之间的电性连接可通过位于芯片周围的连接垫实现。
连接垫是半导体芯片中的集成电路与芯片封装(package)之间的接口(interface)。大量的连接垫用以传送电力、接地(ground)及输入/输出信号。因此，高的连接垫产量可确保高的芯片产量。
公知的连接垫具有分层的结构或包括彼此分离的数层以抵抗外力，例如用以连接焊线至接合垫的焊线接合(wire bonding)工艺对连接垫所施加的外力的作用。
一般的连接垫是由多个金属层构成，金属层由芯片装置的末端所延伸，各个金属层通过金属层间介电(IMD)层隔离，IMD层通常为氧化硅。金属介电层插塞(via)一般为钨，通过IMD层且与金属层连接。焊线分别连接至连接金属图案(bonding metal pattern)及芯片封装，以在芯片及封装之间形成电性连接。除了连接位置之外，在芯片表面覆盖保护层以将芯片与污染物隔离并防止芯片受损。
一种连接垫的损坏(failure)为焊线从金属图案剥离(peeling)，这样的剥离现象由外力引起，特别是在焊线连接工艺中。公知技术揭示一种可增加剥离抗性的连接垫结构，以及一种确保无污染连接工艺的清洁方法。另一种连接垫的损坏为连接垫回剥(peel back)，这是由于焊线连接过程中的外力使底下的一层或数层发生分层(delaminating)现象。目前也有一些解决方案针对防止连接垫发生剥离。
焊线连接工艺会引起连接垫剥离或造成底下的一至数层的回剥(分层)，如此，使连接垫结构减弱且损害芯片的焊线的其他部分。这样的回剥现象减少或阻碍了连接垫与芯片上的集成电路装置之间的电性连接，进而降低可靠度(reliability)及减少芯片的寿命。
当制造工艺中有应力存在于某层时，一旦产生了小裂缝，此裂缝即将广泛地生长。减少IMD层产生这类裂缝的主要方法是采用具有低残余应力的IMD层。通常利用复合氧化硅层实现此目的，例如高密度等离子体(highdensity plasma，HDP)氧化硅层加上等离子体增强的以四乙基硅酸盐(plasma-enhanced tetraethylorthosilicate，PETEOS)为反应气体所形成的氧化硅层。然而，即便利用复合氧化硅层来减少应力，IMD层还是禁不起芯片封装过程中遭遇的应力。因此，IMD层仍会产生裂缝。
有鉴于此，目前需要一种增加耐久性的连接垫结构及其制造方法，其中连接垫与底下的层具有良好的粘着性(adhesion)，因此，这种连接垫结构可适用于芯片直焊基板(chip on board)技术。
发明内容
本发明的目的之一在于提供一种改善半导体装置可靠度的连接垫结构。
本发明提供一种半导体装置的形成方法，包括：提供基底，该基底上方具有介电层；在该介电层中形成多个内连线结构，所述多个内连线结构堆叠而成，各个内连线结构包括导电层及插塞层，该导电层连接该插塞层；在所述多个内连线结构上方形成连接垫结构，该连接垫结构具有凸块预定区；以及在至少一插塞层中形成裂缝停止物，该裂缝停止物沿着该凸块预定区的投影区域的边缘形成，其中该导电层介于该插塞层与该连接垫结构之间。
如上所述的半导体装置的形成方法，其中该裂缝停止物包括至少一具有强度的插塞，该具有强度的插塞的尺寸约大于1μm×1μm且约不大于10μm×10μm。
如上所述的半导体装置的形成方法，其中该裂缝停止物包括多个具有强度的插塞，且所述多个具有强度的插塞形成在该凸块预定区的投影区域之内。
如上所述的半导体装置的形成方法，其中该裂缝停止物包括具有强度的插塞，该具有强度的插塞占据该凸块预定区的全部投影区域。
本发明又提供一种半导体装置，包括：基底，其上方具有介电层；多个内连线结构，在该介电层中，所述多个内连线结构堆叠而成，各个内连线结构包括导电层及插塞层，该插塞层连接该导电层，其中至少一插塞层包括裂缝停止物；以及连接垫结构，在所述多个内连线结构上方，该连接垫结构具有凸块预定区；其中该裂缝停止物沿着该凸块预定区的投影区域的边缘形成，其中该导电层介于该插塞层与该连接垫结构之间。
如上所述的半导体装置，其中所述多个内连线结构包括最高内连线结构，包括该裂缝停止物的该插塞层位于该最高内连线结构下方。
如上所述的半导体装置，该最高内连线结构下方的三个连续的插塞层分别包括该裂缝停止物。
如上所述的半导体装置，其中该裂缝停止物包括至少一具有强度的插塞，该具有强度的插塞的尺寸约大于1μm×1μm且约不大于10μm×10μm。
如上所述的半导体装置，其中该裂缝停止物包括多个具有强度的插塞，且所述多个具有强度的插塞形成在该凸块预定区的投影区域之内。
如上所述的半导体装置，其中该裂缝停止物包括具有强度的插塞，且该具有强度的插塞占据该凸块预定区的全部投影区域。
如上所述的半导体装置，其中该具有强度的插塞包括正方形或长方形。
如上所述的半导体装置，其中该连接垫结构包括：保护层，具有开口，该保护层位于所述多个内连线结构上方；以及连接垫层，具有凸块区，该凸块区在该开口中。
如上所述的半导体装置，其中该连接垫结构还包括：接触垫，位于所述多个内连线结构与该连接垫层之间。
本发明再提供一种半导体装置的形成方法，包括：提供基底，该基底上方具有第一介电层；在该第一介电层中形成多个较低内连线结构，各个内连线结构包括第一导电层及第一插塞层，该第一插塞层连接该第一导电层，其中至少一该第一插塞层包括至少一具有强度的插塞以作为裂缝停止物；在第二介电层中及所述多个较低内连线结构上方形成最高内连线结构，该最高内连线结构包括第二导电层及第二插塞层，该第二插塞层连接该第二导电层；以及在该最高内连线结构上方形成连接垫结构，该连接垫结构具有凸块预定区；其中该具有强度的插塞沿着该凸块预定区的投影区域的边缘形成，且该具有强度的插塞的尺寸约大于1μm×1μm且约不大于10μm×10μm。
本发明可克服现有技术的连接垫结构中易产生裂缝等缺点，且制造工艺获得良好的改善。
附图说明
图1显示本发明实施例的连接垫结构的制造方法；
图2显示本发明实施例的具有连接垫结构的半导体装置的剖面图；
图3至图5显示本发明其他实施例的具有连接垫结构的半导体装置的剖面图；
图6至图8显示本发明实施例的介电层中具有裂缝停止物的插塞层。
其中，附图标记说明如下：
10、12、14、16～步骤；100～半导体装置；
105～金属层；         110基底；
120～介电层；         130～导电层；
140～插塞层；         150～裂缝停止物；
160～凸块预定区；     170～边缘；
180～保护层；         190～开口；
210～内连线结构；     220～连接垫结构；
230～最高内连线结构； 240～连接垫层；
250～接触垫；         310～裂缝停止物；
410～裂缝停止物；     540、550、560～裂缝停止物；
570～最高内连线结构； 510、520、530～插塞层。
具体实施方式
本发明提供一种具有连接垫结构的半导体装置及其制造方法。以下实施例将伴随着附图说明本发明的概念，在附图或说明中，相似或相同的部分使用相似或相同的标号。以下实施例并非本发明唯一的应用，本实施例仅是说明实施本发明的特定方法，其并非用以限定本发明及专利范围。
在以下说明中，当叙述一层是位于基板或是另一层上时，是叙述此层与基板或另一层的相对的位置关系，此层可直接位于基板或是另一层上，或是其间也可有中间层。
图2显示本发明实施例的具有连接垫结构220的半导体装置100的剖面图。请参阅图2，在基底110上设置介电层120，之后，在介电层120中形成堆叠的内连线结构210以电性连接基底110上的电路或金属层105。内连线结构210包括导电层130及连接导电层130的插塞层140。特别的是，至少一插塞层140包括裂缝停止物150。堆叠的内连线结构210包括最高内连线结构230，并且具有裂缝停止物150的插塞层140位于最高内连线结构230下方。接着，在内连线结构210上方形成连接垫结构220，连接垫结构220具有凸块(bump)预定区160。具有裂缝停止物150的插塞层140可埋置于介电层120中。特别的是，裂缝停止物150沿着凸块预定区160的投影区域的边缘170形成。
本实施例的特征之一是，堆叠的内连线结构210包括至少一具有裂缝停止物150的插塞层140，其中裂缝停止物150形成在凸块预定区160的投影区域的边缘170。裂缝停止物150可包括至少一具有强度的插塞，其尺寸约大于1μm×1μm。在其他例子中，裂缝停止物150可包括至少一具有强度的插塞，其尺寸约不大于10μm×10μm。
图3至图5显示本发明其他实施例的具有连接垫结构的半导体装置的剖面图。在此，与图2相同或相似的部分不再赘述。
请参阅图3，在另一实施例中，裂缝停止物包括一个具有强度的插塞310，其中单一的插塞310占据凸块预定区160的全部投影区域。
请参阅图4，在另一实施例中，裂缝停止物包括多个具有强度的插塞410，这些插塞410形成在凸块预定区160的投影区域之中。这些具有强度的插塞410的尺寸约大于1μm×1μm。
请参阅图5，在另一实施例中，在最高内连线结构下方有多于一层的插塞层分别具有裂缝停止物。举例而言，在最高内连线结构570下方有三个连续的插塞层510、520及530分别包括裂缝停止物540、550及560。需注意的是，上述具有强度的插塞可为正方形或长方形。
请参阅图2，连接垫结构220可包括保护层180及连接垫层240，其中保护层180具有开口190，且位于堆叠的内连线结构210上方，而连接垫层240上方有凸块区160，且凸块区160在开口190之中。此外，连接垫结构220还包括接触垫250，接触垫250位于堆叠的内连线结构210与连接垫层240之间，接触垫250作为应力缓冲层。在一些例子中，电路可存在堆叠的内连线结构210及连接垫结构220下方。
另一实施例揭示具有连接垫结构的半导体装置的制造方法。请参阅图1，其显示本发明实施例的半导体装置100的制造方法。在步骤10中，在基底110上形成介电层120。之后，在步骤12中，在介电层120之内形成堆叠的内连线结构210，其中内连线结构210包括导电层130及连接导电层130的插塞层140。接着，在步骤14中，在堆叠的内连线结构210上方形成具有凸块预定区160的连接垫结构220。在步骤16中，在至少一插塞层140中形成裂缝停止物150，且裂缝停止物150沿着凸块预定区160的投影区域的边缘形成。
如上所述，裂缝停止物150可包括至少一具有强度的插塞，其尺寸约大于1μm×1μm。在具有连接垫结构的半导体装置的制造方法中，裂缝停止物包括多个具有强度的插塞，这些插塞形成在凸块预定区的投影区域之中。在一例子中，裂缝停止物包括一个具有强度的插塞，其中单一的插塞占据凸块预定区的全部投影区域。特别的是，上述具有强度的插塞的尺寸约不大于10μm×10μm，且上述具有强度的插塞可为正方形或长方形。
连接垫层240例如由Cu/TiN或AlCu/TiN等材料形成。导电层130例如由Cu/TiN等材料形成。插塞层140例如由铜或钨等材料形成。介电层120可包括氧化硅，例如利用PETEOS形成的氧化硅，或者，介电层120为低介电材料层。在一例子中，介电层120为可通过化学气相沉积法形成的堆叠介电层，内连线结构210可通过双镶嵌工艺形成。
图6至图8显示本发明实施例的介电层120中具有裂缝停止物的插塞层140。裂缝停止物150包括多个具有强度的插塞，这些具有强度的插塞形成在凸块预定区160的投影区域之中，裂缝停止物150为宽度约1至10μm的正方形。其他的插塞140可为宽度约0.19μm的正方形。在一些实施例中，位于凸块预定区160的投影区域之中，这些具有强度且宽度约1至10μm的插塞以环状排列(如图6所示)、钻石形排列(如图7所示)或全面地排列于平面(如图8所示)上。
这样的插塞排列方式可增进连接垫结构的强度及可靠度。因此，有效避免在连接垫结构中发生由于连接垫剥离引起的破坏。
为了降低芯片中的信号传播延迟现象，而在铜集成电路(IC)芯片中使用低介电常数(low-k)材料。因此，用以支撑铜连接垫及结构的介电层材料可具有低介电常数。在具有宽度约为0.19μm的介层插塞的连接垫结构中，裂缝可能会在低介电材料中形成，一些裂缝立即生长，一些裂缝则较慢地生长。这些裂缝可能对芯片中的电路产生立即的损害，或引起长期的可靠度问题。另外，低介电常数材料也具有不良的热传导性，进而导致半导体芯片的温度增加。本领域普通技术人员可知的是，半导体芯片裂缝问题的增加会引起以上讨论的各种问题。
本发明实施例的内连线结构可克服连接垫结构中的上述缺点。如前述的说明，在凸块区的投影区域中的裂缝停止物具有大于1μm的宽度且可支撑整个连接垫结构及半导体装置，其中半导体装置的基底可为硅或其他半导体。裂缝的问题可因此解决，且制造工艺获得良好的改善。
图2至图5的结构仅作为示例，图中显示四层金属层及堆叠于其上的插塞层，然而，具有连接垫及半导体装置的半导体芯片中可具有多于四层的金属层及插塞层。
虽然本发明已以数个较佳实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (14)

1.一种半导体装置的形成方法，包括：
提供基底，该基底上方具有介电层；
在该介电层中形成多个内连线结构，所述多个内连线结构堆叠而成，各个内连线结构包括导电层及插塞层，该导电层连接该插塞层；
在所述多个内连线结构上方形成连接垫结构，该连接垫结构具有凸块预定区；以及
在至少一插塞层中形成裂缝停止物，该裂缝停止物沿着该凸块预定区的投影区域的边缘形成，其中该导电层介于该插塞层与该连接垫结构之间。
2.如权利要求1所述的半导体装置的形成方法，其中该裂缝停止物包括至少一具有强度的插塞，该具有强度的插塞的尺寸大于1μm×1μm且不大于10μm×10μm。
3.如权利要求2所述的半导体装置的形成方法，其中该裂缝停止物包括多个具有强度的插塞，且所述多个具有强度的插塞形成在该凸块预定区的投影区域之内。
4.如权利要求2所述的半导体装置的形成方法，其中该裂缝停止物包括具有强度的插塞，该具有强度的插塞占据该凸块预定区的全部投影区域。
5.一种半导体装置，包括：
基底，其上方具有介电层；
多个内连线结构，在该介电层中，所述多个内连线结构堆叠而成，各个内连线结构包括导电层及插塞层，该插塞层连接该导电层，其中至少一插塞层包括裂缝停止物；以及
连接垫结构，在所述多个内连线结构上方，该连接垫结构具有凸块预定区；
其中该裂缝停止物沿着该凸块预定区的投影区域的边缘形成，且该导电层介于该插塞层与该连接垫结构之间。
6.如权利要求5所述的半导体装置，其中所述多个内连线结构包括最高内连线结构，包括该裂缝停止物的该插塞层位于该最高内连线结构下方。
7.如权利要求6所述的半导体装置，该最高内连线结构下方的三个连续的插塞层分别包括该裂缝停止物。
8.如权利要求5所述的半导体装置，其中该裂缝停止物包括至少一具有强度的插塞，该具有强度的插塞的尺寸大于1μm×1μm且不大于10μm×10μm。
9.如权利要求8所述的半导体装置，其中该裂缝停止物包括多个具有强度的插塞，且所述多个具有强度的插塞形成在该凸块预定区的投影区域之内。
10.如权利要求8所述的半导体装置，其中该裂缝停止物包括具有强度的插塞，且该具有强度的插塞占据该凸块预定区的全部投影区域。
11.如权利要求8所述的半导体装置，其中该具有强度的插塞包括正方形或长方形。
12.如权利要求5所述的半导体装置，其中该连接垫结构包括：
保护层，具有开口，该保护层位于所述多个内连线结构上方；以及
连接垫层，具有凸块区，该凸块区在该开口中。
13.如权利要求12所述的半导体装置，其中该连接垫结构还包括：
接触垫，位于所述多个内连线结构与该连接垫层之间。
14.一种半导体装置的形成方法，包括：
提供基底，该基底上方具有第一介电层；
在该第一介电层中形成多个较低内连线结构，各个内连线结构包括第一导电层及第一插塞层，该第一插塞层连接该第一导电层，其中至少一该第一插塞层包括至少一具有强度的插塞以作为裂缝停止物；
在第二介电层中及所述多个较低内连线结构上方形成最高内连线结构，该最高内连线结构包括第二导电层及第二插塞层，该第二插塞层连接该第二导电层；以及
在该最高内连线结构上方形成连接垫结构，该连接垫结构具有凸块预定区；
其中该具有强度的插塞沿着该凸块预定区的投影区域的边缘形成，且该具有强度的插塞的尺寸大于1μm×1μm且不大于10μm×10μm。
CNB2007101081858A 2006-06-30 2007-05-30 半导体装置及其形成方法 Expired - Fee Related CN100530582C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/477,940 US7470994B2 (en) 2006-06-30 2006-06-30 Bonding pad structure and method for making the same
US11/477,940 2006-06-30

Publications (2)

Publication Number Publication Date
CN101097875A CN101097875A (zh) 2008-01-02
CN100530582C true CN100530582C (zh) 2009-08-19

Family

ID=38877246

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2007101081858A Expired - Fee Related CN100530582C (zh) 2006-06-30 2007-05-30 半导体装置及其形成方法

Country Status (2)

Country Link
US (1) US7470994B2 (zh)
CN (1) CN100530582C (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI462249B (zh) * 2012-05-09 2014-11-21 A semiconductor device having a pad

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101003118B1 (ko) * 2008-10-10 2010-12-21 주식회사 하이닉스반도체 반도체 집적 회로 장치의 패드 구조체
US8643149B2 (en) * 2009-03-03 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Stress barrier structures for semiconductor chips
US20110067910A1 (en) * 2009-09-18 2011-03-24 International Business Machines Corporation Component securing system and associated method
US8476764B2 (en) * 2011-09-18 2013-07-02 Nanya Technology Corp. Bonding pad structure for semiconductor devices
CN108447837A (zh) * 2017-02-16 2018-08-24 中芯国际集成电路制造(上海)有限公司 一种半导体器件
CN109244034A (zh) * 2018-08-22 2019-01-18 安徽信息工程学院 避免芯片封装打线时导致金属介质层断裂的方法
CN111668121B (zh) * 2019-03-05 2022-05-27 台湾积体电路制造股份有限公司 晶圆接合结构及其形成方法
US10916510B1 (en) * 2019-11-19 2021-02-09 Nanya Technology Corporation Semiconductor device with stress-relieving features and method for fabricating the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001210744A (ja) * 2000-01-25 2001-08-03 Nec Corp 回路基板
US20030020163A1 (en) 2001-07-25 2003-01-30 Cheng-Yu Hung Bonding pad structure for copper/low-k dielectric material BEOL process
US7572738B2 (en) * 2005-05-23 2009-08-11 Sony Corporation Crack stop trenches in multi-layered low-k semiconductor devices
US7456507B2 (en) * 2006-01-12 2008-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Die seal structure for reducing stress induced during die saw process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI462249B (zh) * 2012-05-09 2014-11-21 A semiconductor device having a pad

Also Published As

Publication number Publication date
CN101097875A (zh) 2008-01-02
US7470994B2 (en) 2008-12-30
US20080003820A1 (en) 2008-01-03

Similar Documents

Publication Publication Date Title
CN100530582C (zh) 半导体装置及其形成方法
CN100539099C (zh) 焊盘结构及其形成方法
US7528467B2 (en) IC substrate with over voltage protection function
US7786572B2 (en) System in package (SIP) structure
US7629689B2 (en) Semiconductor integrated circuit having connection pads over active elements
CN102148203B (zh) 半导体芯片以及形成导体柱的方法
US20110156249A1 (en) Wafer-to-wafer stack with supporting pedestal
CN101097906A (zh) 具有垂直形成的热沉的层叠封装
CN101179057B (zh) 接合垫结构及其制作方法
US20070035038A1 (en) Novel bonding pad structure to minimize IMD cracking
CN101908595A (zh) 发光装置及其制造方法
CN2613046Y (zh) 芯片封装结构
CN100397645C (zh) 具有增强钝化层之集成电路
TW407299B (en) Semiconductor device and manufacture thereof
JPH031538A (ja) 半導体装置
TWI718812B (zh) 微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統
JP2004311832A (ja) 半導体装置
TW200828532A (en) Multiple chip package
US20060263934A1 (en) Chip-type micro-connector and method of packaging the same
CN102655132B (zh) 半导体结构及其制法
CN101601129B (zh) 安装基板和电子设备
US20070209835A1 (en) Semiconductor device having pad structure capable of reducing failures in mounting process
CN103779234A (zh) 一种半导体器件封装结构以及制备方法
CN100466236C (zh) 半导体元件的结构
KR100587042B1 (ko) 적층형 패키지 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090819