US8476764B2 - Bonding pad structure for semiconductor devices - Google Patents

Bonding pad structure for semiconductor devices Download PDF

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US8476764B2
US8476764B2 US13/235,491 US201113235491A US8476764B2 US 8476764 B2 US8476764 B2 US 8476764B2 US 201113235491 A US201113235491 A US 201113235491A US 8476764 B2 US8476764 B2 US 8476764B2
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layer
pad
bonding pad
structure according
imd
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US20130069235A1 (en
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Tse-Yao Huang
Yi-Nan Chen
Hsien-Wen Liu
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Nanya Technology Corp
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Nanya Technology Corp
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Assigned to NANYA TECHNOLOGY CORP. reassignment NANYA TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, YI-NAN, HUANG, TSE-YAO, LIU, HSIEN-WEN
Priority to TW100138614A priority patent/TWI443794B/en
Priority to CN201110340025.2A priority patent/CN103000611B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Definitions

  • the present invention relates generally to a semiconductor device, and more particularly, to a bonding pad structure of integrated circuits.
  • an integrated circuit chip is attached to a chip carrier such as a leadframe or a package substrate in an assembly process.
  • Wire bonding is then carried out after the integrated circuit chip is attached to the chip carrier.
  • bond wires are attached one at a time to respective bonding pads or input/output (I/O) pads on the integrated circuit chip, and the other end of the bond wire may be attached to a lead, a bonding pad, or a finger on the chip carrier.
  • a wire-bonding process includes the following steps. Firstly, an initial ball is formed at a tip end of a wire passing through a capillary of a wire bonder and the initial ball is pressure-bonded onto the bonding pad of the chip. Thereafter, the capillary is moved upward to a predetermined height away from the pressure-bonded ball, and then the capillary is moved toward a bonding site on the chip carrier, thereby the wire electrically and mechanically connects the bonding pad of the chip and the chip carrier.
  • Low-k and/or ultra low-k dielectric materials have been widely used for the inter-metal dielectric (IMD) layers to reduce RC delay and parasitic capacitances.
  • IMD inter-metal dielectric
  • the strength of the dielectric material decreases.
  • many low-k dielectric materials are highly susceptible to cracking or lack the strength needed to withstand the stress exerted on the pad during wire bonding. For example, pad lifting phenomenon has been observed during wire-bonding process due to bonding pad delamination and insufficient dielectric strength under the bonding pad.
  • a bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.
  • IMD inter-metal dielectric
  • FIG. 2 is a perspective top view of the bonding pad structure according to the embodiment of this invention.
  • FIG. 1 is a schematic, cross-sectional diagram showing a bonding pad structure 300 fabricated within a pad forming region 200 according to one embodiment of this invention.
  • FIG. 2 is a perspective top view of the bonding pad structure 300 according to the embodiment of this invention.
  • a semiconductor substrate 100 such as a silicon substrate is provided.
  • a plurality of inter-metal dielectric (IMD) layers 102 ⁇ 108 are laminated on a main surface of the semiconductor substrate 100 .
  • the IMD layers 102 ⁇ 108 may comprise silicon oxide, silicon nitride, silicon oxy-nitride, silicon carbide, BSG, BPSG, low-k or ultra low-k dielectrics known in the art.
  • no interconnection structure is formed in a three-dimensional space 150 (indicated with dashed line) directly under the bondable metal pad layer 30 within a central region 202 of the pad forming region 200 .
  • the bonding pad structure 300 comprises the bondable metal pad layer 30 on the IMD layer 108 , a plurality of via plugs 28 fabricated in the IMD layer 108 to couple the bondable metal pad layer 30 to an underlying second-level damascened copper structures 26 a and 26 b fabricated in the IMD layer 106 .
  • a silicon carbide cap layer 106 a may be provided in the IMD layer 106 .
  • the plurality of via plugs 28 are fabricated within an annular region 204 that surrounds the central region 202 of the pad forming region 200 .
  • the damascened copper structure 26 b may be an annular shaped or ring shaped copper layer, and the damascened copper structure 26 a may comprise a plurality of copper via plugs.
  • a Similar annular shaped or ring shaped damascened copper structure 24 may be formed in the IMD layer 104 .
  • a contact plug layer 22 may be provided in the IMD layer 102 . It is to be understood that, in some embodiments, the contact plug layer 22 may be omitted. It is to be understood that, in some embodiments, the damascened copper structure 24 may be in the IMD layer 104 may be omitted.
  • the present invention because no interconnection structure, particularly damascened copper structure, is formed in the three-dimensional space 150 directly under the bondable metal pad layer 30 within a central region 202 of the pad forming region 200 , whereby the pad lifting problem can be avoided.
  • the applicant has found that by excluding the via plugs 28 and the damascened copper structure from being formed within the three-dimensional space 150 directly under the bondable metal pad layer 30 within a central region 202 of the pad forming region 200 , the aluminum segregation at the copper-SiC cap interface can be avoided and the integrity of the IMD layers and the bonding strength therebetween, particularly between the silicon carbide cap layer 106 a and the rest part of the IMD layer 106 , can be greatly improved.

Abstract

A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a bonding pad structure of integrated circuits.
2. Description of the Prior Art
As known in the art, to form a chip package, an integrated circuit chip is attached to a chip carrier such as a leadframe or a package substrate in an assembly process. Wire bonding is then carried out after the integrated circuit chip is attached to the chip carrier. During a wire-bonding process, bond wires are attached one at a time to respective bonding pads or input/output (I/O) pads on the integrated circuit chip, and the other end of the bond wire may be attached to a lead, a bonding pad, or a finger on the chip carrier.
Typically, a wire-bonding process includes the following steps. Firstly, an initial ball is formed at a tip end of a wire passing through a capillary of a wire bonder and the initial ball is pressure-bonded onto the bonding pad of the chip. Thereafter, the capillary is moved upward to a predetermined height away from the pressure-bonded ball, and then the capillary is moved toward a bonding site on the chip carrier, thereby the wire electrically and mechanically connects the bonding pad of the chip and the chip carrier.
Low-k and/or ultra low-k dielectric materials have been widely used for the inter-metal dielectric (IMD) layers to reduce RC delay and parasitic capacitances. However, as the dielectric constant decreases, the strength of the dielectric material decreases. Hence, many low-k dielectric materials are highly susceptible to cracking or lack the strength needed to withstand the stress exerted on the pad during wire bonding. For example, pad lifting phenomenon has been observed during wire-bonding process due to bonding pad delamination and insufficient dielectric strength under the bonding pad.
Thus, a need exists for an improved bonding pad structure that can sustain the stress exerted on it by a wire bonding process, which is capable of solving the prior art pad lifting problem.
SUMMARY OF THE INVENTION
It is one objective of the present invention to provide an improved bonding pad structure in order to solve the above-mentioned prior art problems.
According to one embodiment of this invention, a bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
FIG. 1 is a schematic, cross-sectional diagram showing a bonding pad structure fabricated within a pad forming region according to one embodiment of this invention; and
FIG. 2 is a perspective top view of the bonding pad structure according to the embodiment of this invention.
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
DETAILED DESCRIPTION
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which the embodiments may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the described embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the included embodiments are defined by the appended claims.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic, cross-sectional diagram showing a bonding pad structure 300 fabricated within a pad forming region 200 according to one embodiment of this invention. FIG. 2 is a perspective top view of the bonding pad structure 300 according to the embodiment of this invention. As shown in FIG. 1 and FIG. 2, a semiconductor substrate 100 such as a silicon substrate is provided. A plurality of inter-metal dielectric (IMD) layers 102˜108 are laminated on a main surface of the semiconductor substrate 100. The IMD layers 102˜108 may comprise silicon oxide, silicon nitride, silicon oxy-nitride, silicon carbide, BSG, BPSG, low-k or ultra low-k dielectrics known in the art.
On a top surface of the IMD layer 108, as shown in FIG. 1, a bondable metal pad layer 30 such as an aluminum pad, which may be a part of a re-distributed layer (RDL) in some cases, is provided within the pad forming region 200. After the formation of the bondable metal pad layer 30, a passivation layer 110 such as a silicon nitride, polyimide or any suitable passivation material is employed to cover the bondable metal pad layer 30 and the top surface of the IMD layer 108. An opening 110 a is then formed in the passivation layer 110 to expose a portion of the bondable metal pad layer 30. Thereafter, a bond wire 40 is attached to the exposed surface of the bondable metal pad layer 30 through the opening 110 a.
As previously mentioned, during the wire-bonding process, the stress exerted on the bondable metal pad layer 30 may cause the pad lifting problem. The applicant has found that the aluminum segregation at the copper-SiC cap interface may play an important role in the pad lifting issue. To avoid this, according to one embodiment of this invention, no interconnection structure is formed in a three-dimensional space 150 (indicated with dashed line) directly under the bondable metal pad layer 30 within a central region 202 of the pad forming region 200.
As shown in FIG. 1 and FIG. 2, the bonding pad structure 300 comprises the bondable metal pad layer 30 on the IMD layer 108, a plurality of via plugs 28 fabricated in the IMD layer 108 to couple the bondable metal pad layer 30 to an underlying second-level damascened copper structures 26 a and 26 b fabricated in the IMD layer 106. A silicon carbide cap layer 106 a may be provided in the IMD layer 106. According to the embodiment of this invention, the plurality of via plugs 28 are fabricated within an annular region 204 that surrounds the central region 202 of the pad forming region 200. According to the embodiment of this invention, the damascened copper structure 26 b may be an annular shaped or ring shaped copper layer, and the damascened copper structure 26 a may comprise a plurality of copper via plugs. A Similar annular shaped or ring shaped damascened copper structure 24 may be formed in the IMD layer 104. A contact plug layer 22 may be provided in the IMD layer 102. It is to be understood that, in some embodiments, the contact plug layer 22 may be omitted. It is to be understood that, in some embodiments, the damascened copper structure 24 may be in the IMD layer 104 may be omitted.
It is advantageous to use the present invention because no interconnection structure, particularly damascened copper structure, is formed in the three-dimensional space 150 directly under the bondable metal pad layer 30 within a central region 202 of the pad forming region 200, whereby the pad lifting problem can be avoided. The applicant has found that by excluding the via plugs 28 and the damascened copper structure from being formed within the three-dimensional space 150 directly under the bondable metal pad layer 30 within a central region 202 of the pad forming region 200, the aluminum segregation at the copper-SiC cap interface can be avoided and the integrity of the IMD layers and the bonding strength therebetween, particularly between the silicon carbide cap layer 106 a and the rest part of the IMD layer 106, can be greatly improved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (9)

What is claimed is:
1. A bonding pad structure, comprising:
a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer;
a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region;
a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and
a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the plurality of via plugs are not formed in a central region of the pad forming region.
2. The bonding pad structure according to claim 1 wherein no interconnection structure is formed in a three-dimensional space directly under the bondable metal pad layer within the central region of the pad forming region.
3. The bonding pad structure according to claim 2 wherein the interconnection structure is damascened copper structure.
4. The bonding pad structure according to claim 3 wherein the topmost IMD layer is directly laminated on a silicon carbide cap layer.
5. The bonding pad structure according to claim 4 wherein by excluding the plurality of via plugs and the damascened copper structure from being formed within the three-dimensional space directly under the bondable metal pad layer within the central region of the pad forming region, aluminum segregation at copper-silicon carbide cap interface is avoided.
6. The bonding pad structure according to claim 1 wherein the IMD layers comprise silicon oxide, silicon nitride, silicon oxy-nitride, silicon carbide, BSG, BPSG, low-k or ultra low-k dielectrics.
7. The bonding pad structure according to claim 1 wherein the bondable metal pad layer comprises aluminum.
8. The bonding pad structure according to claim 1 wherein the bondable metal pad layer is a part of a re-distributed layer (RDL).
9. The bonding pad structure according to claim 1 wherein further comprising an annular shaped or ring shaped damascened copper structure.
US13/235,491 2011-09-18 2011-09-18 Bonding pad structure for semiconductor devices Active 2032-02-13 US8476764B2 (en)

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US13/235,491 US8476764B2 (en) 2011-09-18 2011-09-18 Bonding pad structure for semiconductor devices
TW100138614A TWI443794B (en) 2011-09-18 2011-10-25 Bonding pad structure for semiconductor devices
CN201110340025.2A CN103000611B (en) 2011-09-18 2011-11-01 Bonding pad structure for semiconductor devices

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9984987B2 (en) 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI569396B (en) 2014-12-08 2017-02-01 財團法人工業技術研究院 Chip structure having bonding wire
CN109698183A (en) * 2017-10-23 2019-04-30 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method, the electronic device of semiconductor devices and semiconductor devices
TWI641896B (en) * 2017-11-09 2018-11-21 友達光電股份有限公司 Flexible electronic device
US11469195B2 (en) * 2020-09-24 2022-10-11 Nanya Technology Corporation Semiconductor device with tilted insulating layers and method for fabricating the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291281B1 (en) * 1999-09-28 2001-09-18 United Microelectronics Corp. Method of fabricating protection structure
US6599578B2 (en) * 1998-12-29 2003-07-29 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US7880297B2 (en) * 2007-12-31 2011-02-01 Mediatek Inc. Semiconductor chip having conductive member for reducing localized voltage drop
US7986027B2 (en) * 2006-10-20 2011-07-26 Analog Devices, Inc. Encapsulated metal resistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW533508B (en) * 1999-05-05 2003-05-21 Taiwan Semiconductor Mfg Structure and method for preventing inter-metal dielectric layer of semiconductor from cracking
US20060244156A1 (en) * 2005-04-18 2006-11-02 Tao Cheng Bond pad structures and semiconductor devices using the same
US7646087B2 (en) * 2005-04-18 2010-01-12 Mediatek Inc. Multiple-dies semiconductor device with redistributed layer pads
US7470994B2 (en) * 2006-06-30 2008-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding pad structure and method for making the same
US20090079082A1 (en) * 2007-09-24 2009-03-26 Yong Liu Bonding pad structure allowing wire bonding over an active area in a semiconductor die and method of manufacturing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599578B2 (en) * 1998-12-29 2003-07-29 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
US6291281B1 (en) * 1999-09-28 2001-09-18 United Microelectronics Corp. Method of fabricating protection structure
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US7986027B2 (en) * 2006-10-20 2011-07-26 Analog Devices, Inc. Encapsulated metal resistor
US7880297B2 (en) * 2007-12-31 2011-02-01 Mediatek Inc. Semiconductor chip having conductive member for reducing localized voltage drop

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9984987B2 (en) 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US10141275B2 (en) 2016-08-05 2018-11-27 Nanya Technology Corporation Method for manufacturing a semiconductor structure

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CN103000611A (en) 2013-03-27
US20130069235A1 (en) 2013-03-21
TWI443794B (en) 2014-07-01
TW201314854A (en) 2013-04-01
CN103000611B (en) 2015-07-22

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