TWI641896B - Flexible electronic device - Google Patents

Abstract

A flexible electronic device includes a body, a pad protection structure and a pad layer. The body has a joint region. The pad protection structure is located in the bonding area, and includes a base layer, a first insulation layer, a second insulation layer, and a first stress relief layer. The first insulating layer is disposed on the base layer. The second insulating layer is disposed on the first insulating layer. The first stress relief layer is disposed on the base layer, the first insulation layer, or the second insulation layer. In addition, the pad layer is disposed on the pad protection structure, and the pad layer is not in contact with the first stress relief layer.

Description

Flexible electronic device

The invention relates to a flexible electronic device, and more particularly to a flexible electronic device with a pad protection structure.

In recent years, with the rapid development of network and communication technologies, the display panels of mobile electronic devices have developed toward flexible display technologies. Because the flexible display panel has the characteristics of being bendable and foldable, its volume is smaller, and it is convenient to carry, which has become the development focus of the new generation of display technology.

The manufacturing process of the flexible display panel is as follows. First, a flexible base layer is formed on a hard carrier. Then, in subsequent physical / chemical vapor deposition and heat treatment processes, thin film transistors, light emitting layers, circuit layers, and A film layer such as a pad layer is on the flexible base layer. After the display panel manufacturing process is completed, the flexible base layer is separated from the hard substrate by laser lift-off technology. However, between the flexible base layer after being removed and the film layer required to make the display element and the driving element, the pad pitch of the pad layer changes due to the existence of stress, so that the subsequent wafer and pad bonding Problems such as poor alignment and poor yield of the joint occurred during the process, which need to be further improved.

The invention relates to a flexible electronic device with a pad protection structure, which can reduce the stress existing between the flexible base layer and the film layer required for manufacturing the display element and the driving element, reduce the change in the pad pitch, and improve the chip and Yield and reliability of pad bonding.

According to an aspect of the present invention, a flexible electronic device is provided, which includes a body, a pad protection structure, and a pad layer. The body has a joint region. The pad protection structure is located in the bonding area and includes a base layer, a first insulation layer, a second insulation layer, and a first stress relief layer. The first insulating layer is disposed on the base layer. The second insulating layer is disposed on the first insulating layer. The first stress relief layer is disposed on the base layer, the first insulation layer, or the second insulation layer. The pad layer is disposed on the pad protection structure, and the pad layer is not in contact with the first stress relief layer.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

10, 10 ’, 10” ‧‧‧ Flexible electronic device

100‧‧‧ Ontology

100A‧‧‧display area

100B‧‧‧Joint Zone

101, 201‧‧‧ Grassroots

102, 106‧‧‧stress release layer

103‧‧‧ Film

107, 207‧‧‧ padding layer

108a ~ 108e‧‧‧stress release block

108f‧‧‧stress release unit

110‧‧‧Display element

200, 200’‧‧‧ pad protection structure

202‧‧‧First Stress Relief Layer

203‧‧‧first insulating layer

204‧‧‧Second insulation layer

205‧‧‧third insulating layer

206‧‧‧Second Stress Relief Layer

300‧‧‧ pad

301‧‧‧first conductive layer

302‧‧‧Second conductive layer

303‧‧‧third conductive layer

a‧‧‧ pitch

b‧‧‧side length

FIG. 1 is a plan view of a flexible electronic device.

Figures 2A to 2C are schematic cross-sectional views of a flexible electronic device according to different embodiments of the present invention along the section line 2-2 in Figure 1.

3A to 3E are top views of a flexible electronic device according to various embodiments of the present invention.

4A to 4B are schematic cross-sectional views of a flexible electronic device 10 'according to different embodiments of the present invention along section line 4-4 in FIG. 3E.

5A to 5E are schematic diagrams of laminating flexible electronic devices on a bonding area according to different embodiments of the present invention.

FIG. 6 is a top view of a flexible electronic device according to another embodiment of the present invention.

7A to 7C are schematic cross-sectional views of a flexible electronic device according to different embodiments of the present invention along section lines 7-7 in FIG. 6.

8A to 8E are schematic diagrams of lamination of flexible electronic devices according to different embodiments of the present invention along the cross-section line 8-8 of FIG. 6 in the bonding area.

The following is a detailed description of an embodiment. The embodiments are only used as examples and are not intended to limit the scope of the present invention. The following uses the same / similar symbols to indicate the same / similar components for explanation.

Referring to FIG. 1, the flexible electronic device 10 is, for example, a flexible display panel, which includes a body 100 having a display area 100A and a bonding area 100B, a pad protection structure 200, and a plurality of pads 300. The display area 100A includes a display element 110 and a driving element (not shown). The pad protection structure 200 is disposed in the bonding area 100B to protect the pad 300 and prevent the pad pitch from changing due to the stress generated by the force. The pads 300 are arranged at intervals in the bonding area 100B for bonding an electronic component, such as a chip (not shown).

Please refer to FIGS. 2A to 2C, which are schematic cross-sectional views of the flexible electronic device 10 according to different embodiments of the present invention along the section line 2-2 in the first figure. The flexible electronic device 10 of this embodiment is provided with at least stress relief in the bonding area 100B. The layer 102 and / or the stress release layer 106 are used to reduce the stress existing between any of the base layer 101, the film layer 103, and the pad layer 107, such as thermal stress that is easy to remain due to mismatched thermal expansion coefficients. The base layer 101 is, for example, a flexible base material of a polymer material, and the pad layer 107 is, for example, a single-layer or multi-layer metal and / or a conductive material such as a transparent conductive material. The film layer 103 is, for example, an insulating layer of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, or an insulating layer of an organic material, such as an acrylic polymer, which is required for manufacturing a display element and a driving element.

Referring to FIG. 2A, the stress release layer 106 may be disposed between the base layer 101 and the pad layer 107, and the stress release layer 106 may be a metal layer or a silicon layer in the film layer 103 required for manufacturing display elements and driving elements. Floor. In addition, referring to FIG. 2B, the stress release layer 102 may be disposed between the base layer 101 and the pad layer 107, and the stress release layer 102 may be a metal layer or a silicon layer formed directly on the base layer 101. In addition, referring to FIG. 2C, two stress relief layers 102 and 106 are disposed between the base layer 101 and the pad layer 107. The two stress relief layers 102 and 106 can be film layers 103 required for manufacturing display elements and driving elements. The two metal layers, two silicon layers, or a combination of a metal layer and a silicon layer, or a stress release layer 106 of the two stress release layers 102 and 106 is a film layer 103 required for manufacturing display elements and driving elements. A metal layer or a silicon layer, and the other stress relief layer 102 is a metal layer or a silicon layer formed directly on the base layer 101. In addition to the above-mentioned combinations, the stress release layers 102 and 106 have other feasible configuration modes or variations. The embodiments of the present invention are only examples, and are not intended to limit the present invention.

In the above embodiments, since at least one stress release layer 102 and 106 is provided between the base layer 101 and the pad layer 107 to reduce the stress existing between the base layer 101 and the insulating layer in the film layer 103, the residual stress can be reduced. It exists in the land 100B.

Please refer to FIGS. 3A to 3E at the same time. FIGS. 3A to 3E show top views of a flexible electronic device 10 ′ according to different embodiments of the present invention. The pad layer 107 includes a plurality of pads 300 and a stress relief block 108 a. 108d is disposed below the pad 300; that is, the stress relief blocks 108a to 108d are not on the same layer as the pad 300, and the stress relief block 108e may be disposed below the pad 300 or on the same layer as the pad 300. For ease of understanding, the stress relief blocks 108a to 108e are indicated by dashed lines. The stress relief blocks 108a to 108e may have different shapes or arrangements according to different embodiments, such as a block-like distribution, a bar-like distribution, a diagonal distribution, or a grid-like distribution. In FIG. 3A, the stress relief layer is a rectangular stress relief block 108a, which covers all areas where the pads 300 are located, and overlaps with the pads 300 in a vertical projection direction. In FIG. 3B, the stress relief layer includes a plurality of stress relief blocks 108b separated from each other. For example, the stress relief layer is arranged at three strips in the longitudinal direction of the pad 300, and is mutually perpendicular to the pad 300 in a vertical projection direction. overlapping. In FIG. 3C, the stress relief layer includes a plurality of stress relief blocks 108c separated from each other. For example, the stress relief layers are arranged at 3 × 3 array intervals in the long side direction and the short side direction of the pad 300, and are perpendicular to the pad 300 in a projection direction. On each other. In FIG. 3D, the stress relief layer includes a plurality of stress relief blocks 108d separated from each other, which are arranged at 3 × 3 array intervals, for example, and are inclined at an angle from the long side direction of the pad 300 and in a vertical projection direction with the pad 300. Overlap each other. In Figure 3E In the stress release layer, a plurality of stress release blocks 108e separated from each other are arranged in a 2 × 3 array in a staggered manner between four pads 300, and the stress release blocks 108e and the pads 300 do not overlap in a vertical projection direction.

In FIGS. 3A to 3D, at least one stress relief block 108a-108d may overlap with at least two pads 300 in a vertical projection direction, and when the stress relief blocks 108a-108d and the pad 300 are staggered into a grid shape, It is known from experiments that the higher the density of the grid, the smaller the amplitude of the change in pad pitch, and the better the effect of stress release. In addition, in FIG. 3E, when the stress relief block 108e and the pad 300 do not overlap in the vertical projection direction, the capacitive coupling between the stress relief block 108e and the pad 300 can also be reduced. In the above embodiments, in addition to the above-mentioned linear / slant / array arrangement of the stress relief block, there are still other feasible configuration modes or variations. The embodiments of the present invention are merely examples, and are not intended to limit the present invention.

Please refer to FIGS. 4A to 4B, which are schematic cross-sectional views of the flexible electronic device 10 'according to different embodiments of the present invention along the section line 4-4 in FIG. 3E. In the embodiment of the present invention, the pad may have a double-layer structure or a structure with more than three layers. 4A to 4B illustrate embodiments in which the pad layer has a three-layer structure, and may include a first conductive layer 301, a second conductive layer 302, and a third conductive layer 303. The first conductive layer and the second conductive layer are, for example, a metal, and the third conductive layer is, for example, a transparent conductive material such as indium tin oxide (ITO), but the present invention is not limited thereto. In other embodiments, different combinations and order. In addition, the stress relief block 108e may be in a different layer from the pad and not in contact.

Please refer to FIGS. 5A to 5E, which are schematic diagrams of laminating a flexible electronic device 10 'on a bonding area 100B according to different embodiments of the present invention. In Figure 5A In the above embodiment, the pad layer 207 is the same as the pad layer 107 with the pad 300 described above, which is located on the pad protection structure 200 having a stress relief layer. The pad protection structure 200 includes a base layer 201 and a first layer. The stress relief layer 202, a first insulating layer 203, and a second insulating layer 204. The base layer 201 is, for example, a flexible substrate. The first stress release layer 202 is disposed on the base layer 201, the first insulation layer 203 is disposed on the first stress release layer 202, and the second insulation layer 204 is disposed on the first insulation layer 203. The first stress relief layer 202 is the same as the stress relief layer 102 described above and is arranged in the same manner as the stress relief blocks 108 a to 108 e described above. The first stress relief layer 202 is not in contact with the pad layer 207 and is electrically insulated. In an embodiment, the first insulating layer 202 and the second insulating layer 203 are, for example, silicon oxide, silicon nitride, or silicon oxynitride, or other inorganic material layers in the film layer 103 required for manufacturing display elements and driving elements, or for example The insulating layer of an organic material such as an acrylic polymer is not limited in the present invention. According to the above embodiment, the first stress relief layer 202 can reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad layer 207.

Referring to FIG. 5B, according to the above embodiment, the pad protection structure 200 may include a base layer 201, a first insulating layer 203, a first stress relief layer 202, and a second insulating layer 204. This embodiment is different from FIG. 5A in that the first insulating layer 203 is disposed on the base layer 201, the first stress relief layer 202 is disposed on the first insulating layer 203, and is located on the first insulating layer 203 and the second insulating layer. Between 204. The first stress relief layer 202 is the same as the stress relief layer 106 described above and is arranged in the same manner as the stress relief blocks 108 a to 108 e described above. According to the above embodiment, the first stress relief layer 202 Similarly, the change in the pad pitch caused by the stress can be reduced, thereby improving the yield and reliability of the bonding between the chip and the pad layer 207.

Please refer to FIG. 5C. According to the above embodiment, the pad protection structure 200 may include a base layer 201, a first insulating layer 203, a second insulating layer 204, a first stress relief layer 202, and a third insulating layer 205. . This embodiment is different from FIG. 5A in that the first stress relief layer 202 is disposed on the second insulation layer 204 and is located between the second insulation layer 204 and the third insulation layer 205. The third insulating layer 205 is, for example, an inorganic material layer such as silicon oxide, silicon nitride, or silicon oxynitride in the film layer 103 required for manufacturing a display element and a driving element. The first stress relief layer 202 is the same as the stress relief layer 106 described above and is arranged in the same manner as the stress relief blocks 108 a to 108 e described above. According to the above embodiment, the first stress relief layer 202 can also reduce the change in the pad spacing caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad layer 207.

Please refer to FIG. 5D. According to the above embodiment, the pad protection structure 200 may include a base layer 201, a first stress release layer 202, a first insulation layer 203, a second stress release layer 206, and a second insulation layer. 204. This embodiment is different from FIG. 5A in that the second stress relief layer 206 is disposed on the first insulation layer 203 and is located between the first insulation layer 203 and the second insulation layer 204. Any of the first stress relief layer 202, the second stress relief layer 206, and the pad layer 207 is not in contact with each other. The first stress relief layer 202 is the same as the stress relief layer 102 described above and its arrangement is the same as the stress relief blocks 108a to 108e described above, and the second stress relief layer 206 is the same as the stress relief layer 106 described above and its arrangement is the same as the above stress relief Blocks 108a ~ 108e. According to the above embodiment, both the first stress relief layer 202 and the second stress relief layer 206 can reach In order to reduce the change in the pad pitch caused by the stress, the yield and reliability of the bonding between the chip and the pad layer 207 are improved.

Please refer to FIG. 5E. According to the above embodiment, the pad protection structure 200 may include a base layer 201, a first insulation layer 203, a first stress release layer 202, a second insulation layer 204, and a second stress release layer. 206 and a third insulating layer 205. This embodiment is different from FIG. 5A in that the first stress relief layer 202 is disposed on the first insulation layer 203, and the second stress relief layer 206 is disposed on the second insulation layer 204 and is located between the second insulation layer 204 and the first insulation layer 204. Between three insulating layers 205. Any of the first stress relief layer 202, the second stress relief layer 206, and the pad layer 207 is not in contact with each other. The first stress relief layer 202 is the same as the stress relief layer 102 described above and its arrangement is the same as the stress relief blocks 108a to 108e described above, and the second stress relief layer 206 is the same as the stress relief layer 106 described above and its arrangement is the same as the above stress relief Blocks 108a ~ 108e. According to the above embodiment, both the first stress release layer 202 and the second stress release layer 206 can reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad layer 207.

Please refer to FIG. 6, which illustrates a top view of a flexible electronic device 10 ″ according to another embodiment of the present invention. In this embodiment, in addition to providing at least one stress relief layer 102 as shown in FIGS. 2A to 2C, 106. Between the pad layer 107 and the base layer 101, the flexible electronic device 10 "may further include a plurality of stress relief portions 108f disposed on the same layer as the pad 300. As shown in FIG. 6, the plurality of stress relief portions 108 f are arranged between the five pads 300 at a 2 × 4 array interval, for example. The side length b of the stress relief portion 108f is smaller than the distance a between the two adjacent pads 300, where the ratio of the side length b to the distance a is, for example, greater than 0.1 so that the contact pads 300 are spaced apart from the stress relief portion 108f and are not in contact. The material of the stress relief portion 108f may be metal or silicon. The stress relief portion 108f can also reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad 300. In this embodiment, in addition to the stress relief portions 108f arranged in a block array, there are still other feasible configurations or variations. The embodiments of the present invention are merely examples, and are not intended to limit the present invention.

Please refer to FIGS. 7A to 7C, which are schematic cross-sectional views of a flexible electronic device 10 "according to different embodiments of the present invention along section lines 7-7 in FIG. 6. In the embodiment of the present invention, the pads may be A structure with two or more layers. In Figs. 7A to 7C, an embodiment in which the pad is a three-layer structure is shown. In Fig. 7A, the stress relief portion 108f may be the same layer as the third conductive layer 303 but not in contact. In FIG. 7B, the stress relief portion 108f may be on the same layer as the second conductive layer 302 but not in contact, and in FIG. 7C, the stress relief portion 108f may be on the same layer as the first conductive layer 301 but not in contact. The stress relief portion The material of 108f can be the same as that of the first, second, or third conductive layers 301 to 303 in the same layer and can be completed in the same process as the first, second, or third conductive layers 301 to 303 in the same layer; or The material of the stress relief portion 108f may be different from that of the first, second, or third conductive layers 301 to 303 in the same layer.

Please refer to FIGS. 6 and 8A to 8E, where FIGS. 8A to 8E show the stacking of the flexible electronic device 10 ”according to different embodiments of the present invention along the section line 8-8 of FIG. 6 in the bonding area 100B. 8A, the pad protection structure 200 'includes a base layer 201, a first stress release layer 202, a first insulation layer 203, a second insulation layer 204, and at least one stress release portion 108f. Stress relief layer 202 It is disposed on the base layer 201, as shown in FIG. 5A. For the same components, please refer to the above, and will not be described again here. In addition, the stress relief portion 108f is disposed on the second insulating layer 204 and is the same layer as the pad 300, as shown in FIGS. 7A to 7C. According to the above embodiment, both the first stress release layer 202 and the stress release portion 108f can reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad 300.

Referring to FIG. 8B, the pad protection structure 200 'may include a base layer 201, a first insulation layer 203, a first stress relief layer 202, a second insulation layer 204, and at least one stress relief portion 108f. This embodiment is different from FIG. 8A in that the first stress relief layer 202 is disposed on the first insulation layer 203 and is located between the first insulation layer 203 and the second insulation layer 204, as shown in FIG. 5B. Please refer to the above for the same components, and will not repeat them here. In addition, a stress relief portion 108f is provided on the second insulating layer 204. According to the above embodiment, the first stress release layer 202 and the stress release portion 108f can also reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad 300.

Referring to FIG. 8C, the pad protection structure 200 'may include a base layer 201, a first insulating layer 203, a second insulating layer 204, a first stress release layer 202, a third insulating layer 205, and at least one stress. Release section 108f. This embodiment is different from FIG. 6A in that the first stress relief layer 202 is disposed on the second insulation layer 204 and is located between the second insulation layer 204 and the third insulation layer 205, as shown in FIG. 5C. Please refer to the above for the same components, and will not repeat them here. In addition, a stress relief portion 108f is provided on the third insulating layer 205. According to the above embodiment, the first stress is released The layer 202 and the stress relief portion 108f can also reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad 300.

Referring to FIG. 8D, according to the above embodiment, the pad protection structure 200 'may include a base layer 201, a first stress release layer 202, a first insulation layer 203, a second stress release layer 206, and a second insulation. The layer 204 and at least one stress relief portion 108f. This embodiment is different from FIG. 6A in that the second stress relief layer 206 is disposed on the first insulation layer 203 and is located between the first insulation layer 203 and the second insulation layer 204. As shown in FIG. 5D, the same Please refer to the above components, and will not repeat them here. In addition, a stress relief portion 108f is provided on the second insulating layer 204. According to the above embodiment, the first stress relief layer 202, the second stress relief layer 206, and the stress relief portion 108f can all reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad 300.

Referring to FIG. 8E, according to the above embodiment, the pad protection structure 200 'may include a base layer 201, a first insulating layer 203, a first stress release layer 202, a second insulation layer 204, and a second stress release The layer 206, a third insulating layer 205, and at least one stress relief portion 108f. This embodiment is different from FIG. 8A in that the first stress relief layer 202 is disposed on the first insulation layer 203, and the second stress relief layer 206 is disposed on the second insulation layer 204 and is located between the second insulation layer 204 and the first Between the three insulating layers 205, as shown in FIG. 5E, please refer to the same components as above, and will not be repeated here. In addition, a stress relief portion 108f is provided on the third insulating layer 205. According to the above embodiment, the first stress relief layer 202, the second stress relief layer 206, and the stress relief The portion 108f can reduce the change in the pad pitch caused by the stress, thereby improving the yield and reliability of the bonding between the wafer and the pad 300.

In the flexible electronic device disclosed in the above embodiments of the present invention, at least one stress relief layer is provided in the bonding area to reduce the change in the pad pitch caused by the stress, and the flexible electronic device in this embodiment can be further provided with The pads are in the stress relief portion of the same layer to further reduce the change in pad pitch caused by the stress. The above stress relief layer may be a metal layer or a silicon layer in a film layer required for manufacturing a display element and a driving element, and the metal layer or the silicon layer is retained in the bonding area during the lithography process and does not need to be removed. In order to reduce the stress existing between the base layer of the polymer material and the inorganic material layer, the residual stress can be reduced in the bonding area, and the change in the pad pitch can be reduced, so as to improve the yield and reliability of the bonding between the wafer and the pad.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (19)

A flexible electronic device includes: a body having a bonding area; a pad protection structure located in the bonding area, including: a base layer; a first insulating layer disposed on the base layer; and a second insulating layer Is disposed on the first insulation layer; and a first stress release layer is disposed on the base layer, the first insulation layer or the second insulation layer; and a pad layer including a plurality of pads is disposed on On the pad protection structure, the pad layer is not in contact with the first stress relief layer, and the first insulating layer and the second insulating layer are both continuous structures within the setting range of the pad layer. The flexible electronic device according to item 1 of the scope of patent application, wherein the first stress relief layer is disposed on the second insulation layer, and the pad protection structure further includes a third insulation layer disposed on the pad. Between the layer and the first stress relief layer. The flexible electronic device according to item 1 of the scope of patent application, wherein the first stress relief layer includes a plurality of stress relief blocks separated from each other, and the pads and the stress relief blocks are in a vertical projection direction At least partially overlap. The flexible electronic device according to item 3 of the scope of patent application, wherein at least one of the stress relief blocks and at least two of the pads overlap in the vertical projection direction. The flexible electronic device according to item 1 of the patent application scope, wherein the pad layer and the first stress relief layer include a plurality of stress relief blocks separated from each other, and the pads and the stress relief blocks are in one Does not overlap in the vertical projection direction. The flexible electronic device according to item 1 of the patent application scope, wherein the pad layer includes a plurality of overlapping conductive layers, and the first stress relief layer is the same layer as one of the conductive layers. According to the flexible electronic device described in item 6 of the scope of patent application, the materials of the first stress relief layers are the same as the material of the conductive layer in the same layer. The flexible electronic device according to item 1 of the patent application scope, wherein the material of the first stress relief layer is metal or silicon. The flexible electronic device according to item 1 of the scope of patent application, wherein the first stress relief layer is disposed on the base layer, and the pad protection structure further includes a second stress relief layer disposed on the first insulation layer. And the second stress relief layer is not in contact with the pad layer. The flexible electronic device according to item 1 of the scope of patent application, wherein the first stress relief layer is disposed on the first insulation layer, and the pad bonding structure further includes a second stress relief layer and a third insulation Layer, the second stress release layer is disposed on the second insulation layer, and the third insulation layer is disposed between the pad layer and the second stress release layer. The flexible electronic device according to item 9 or 10 of the scope of patent application, wherein the second stress relief layer includes a plurality of stress relief blocks separated from each other, and the pads and the stress relief blocks are in a vertical projection direction At least partially overlap. The flexible electronic device according to item 11 of the scope of patent application, wherein at least one of the stress release blocks and at least two of the pads overlap in the vertical projection direction. The flexible electronic device according to item 9 or 10 of the scope of patent application, wherein the second stress relief layer includes a plurality of stress relief blocks separated from each other, and the pads and the stress relief blocks are in a vertical projection Do not overlap in directions. The flexible electronic device according to item 9 or 10 of the scope of patent application, wherein the material of the second stress relief layer is metal or silicon. The flexible electronic device according to item 1 of the scope of the patent application, wherein the materials of the first insulating layer and the second insulating layer are silicon oxide, silicon nitride, silicon oxynitride, or an organic material insulating layer, respectively. The organic material The insulating layer includes an acrylic polymer. The flexible electronic device according to item 2 or 10 of the scope of patent application, wherein the material of the third insulating layer is silicon oxide, silicon nitride or silicon oxynitride, or an organic material insulating layer, and the organic material insulating layer includes acrylic Polymer. The flexible electronic device according to item 1, 2, 9 or 10 of the scope of patent application, further comprising a plurality of stress relief portions, which are disposed on the same layer as the pad layer, wherein the pads and the stress release The interval is arranged in the junction area. The flexible electronic device according to item 17 of the scope of patent application, wherein the pad layer includes a plurality of overlapping conductive layers, and the stress relief portions are in the same layer as one of the conductive layers. The flexible electronic device according to item 18 of the scope of the patent application, wherein the material of the stress relief portions is the same as the material of the conductive layer in the same layer.