CN101179057B - 接合垫结构及其制作方法 - Google Patents
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Abstract
本发明提供一种接合垫结构及其制作方法。上述接合垫结构包含:第一导电材料层;介电材料层,设置于第一导电材料层上方;第二导电材料层;多个导通孔,设置于介电材料层之中,且导通孔电性连接第一与第二导电材料层;及导线,设置于导通孔的周边附近,且设置于介电材料层之中,相邻导通孔之间的距离约等于导线与其相邻的导通孔的最小间距。上述导线对包围导通孔的介电层中产生的龟裂提供阻障层。虽然龟裂会无法控制地散布于导通孔阵列的导通孔之间,但通过导线可阻隔上述龟裂,因此,龟裂不会散布至芯片或晶片的附近区域。导线可以具有各种不同形状及尺寸,以配合适当的应用。由于导线具有大体上连续的长度,因此导线也会对接合垫提供额外的强度。
Description
技术领域
本发明涉及半导体集成电路的制作,特别涉及一种可限制金属层间介电层龟裂的接合垫结构。
背景技术
接合垫是介于容纳在半导体芯片内的集成电路及芯片封装体之间的接口。一般来说,传送电力、接地及输入/输出信号至芯片元件需要大量的接合垫。因此,为了确保较高的芯片合格率,制作具有足够高合格率的接合垫是十分重要的。
一般传统的接合垫结构包含由芯片元件末端延伸的金属层,且该金属层由通常是氧化硅的金属层间介电层(inter-metal dielectric layer;IMD)所分隔。金属导通孔穿过上述金属层间介电层,以连接上述金属层。进行接合打线于接合的金属图案及上述芯片封装体,以在该芯片及封装体之间形成电性连接。接着,除了上述金属层的接合位置外,覆盖保护层于上述金属层的表面,封合该芯片,使得芯片免于污染物的污染及提供避免刮伤的保护层。
一种接合垫失效的形式是由于在接合工艺中所施加的外力,使得打线从上述接合的金属图案脱落。另一种接合垫失效的形式是由于在接合工艺中引起一个或多个底下层的分层所施予的外力,而引起接合垫的脱离。另外,再一种接合垫失效的形式是金属介电层的龟裂现象。
图1A及图1B显示已知用于集成电路(Integrated Circuit;IC)芯片的接合垫1。如图1A及图1B所示,通过导通孔10阵列连接一对接合垫金属层2A、2B。通过介电材料层12分隔上述接合垫金属层2A、2B,且上述导通孔10设置于介电材料层12之中。在例如是集成电路探针测试(IC probe test)或封装时的打线接合工艺中会施加外力至接合垫1。上述外力会在导通孔10间的介电材料层12引起龟裂14。由于龟裂14的蔓延路径是不受控制的,因此,龟裂14通常会延伸至接合垫外围的区域16。上述龟裂现象会引起漏电流(current leakage)、层间短路(interlayer short)、层间衰败(interlayer corrosion)以及降低集成电路的可靠性。再者,较大的龟裂14很容易在产品寿命周期的使用期间导致集成电路的失效。
因此,需要一种改良的导通孔排列,以减低在金属层间介电层发生龟裂的机会,且若在金属层间介电层发生龟裂时,上述改良的导通孔排列也可以减低或限制龟裂的蔓延。再者,上述导通孔排列的制作方法最好也不需要太高的制作成本。
发明内容
有鉴于此,本发明的目的是提供一种接合垫结构。上述接合垫结构,包含:第一导电材料层;介电材料层,设置于该第一导电材料层上方;第二导电材料层;多个导通孔,设置于该介电材料层之中,且所述导通孔电性连接该第一导电材料层与该第二导电材料层;以及导线,设置于所述导通孔的周边附近,且该导线设置于该介电材料层之中,其中相邻的所述导通孔之间的距离约等于所述导线与其相邻的导通孔的最小间距。
根据本发明的接合垫结构,其中所述导线包含直线形状,且所述直线形状具有外部周边及内部周边,所述导通孔设置于由所述导线的所述内部周边所定义的所述介电材料层的区域内。
根据本发明的接合垫,其中所述导线大体上围绕所述导通孔。
根据本发明的接合垫结构,还包含接合的金属图案,设置于所述第二导电材料层的顶部表面上方;以及接合打线,连接所述接合的金属图案。
根据本发明的接合垫结构,其中所述介电材料层包含复合式介电层。
根据本发明的接合垫结构,其中所述导通孔及所述导线,包含导电材料选自钨、铝、铜及硅化物所组成的群组。
根据本发明的接合垫结构,其中所述介电材料层的龟裂存在于所述第一及第二导电材料层,以及所述导线的所述内部周边之间。
本发明的另一个目的是提供一种接合垫结构。上述接合垫结构,包含第一、第二及第三导电材料层。上述接合垫结构也包含第一及第二介电材料层,该第一介电材料层设置于该第一及第二导电材料层之间,且该第二介电材料层设置于该第二及第三导电材料层之间。上述接合垫结构也包含第一多个导通孔,设置于该第一介电材料层之中,以电性连接该第一及第二导电材料层,以及第二多个导通孔,设置于该第二介电材料层之中,以电性连接该第二及第三导电材料层。上述接合垫结构还包含第一导线,设置于该第一介电材料层之中,该第一导线具有内部周边,且该第一导线大体上围绕该第一多个导通孔,以及第二导线,设置于该第二介电材料层之中,该第二导线具有内部周边,且该第二导线大体上围绕该第二多个导通孔。因此,以上述的方式排列,在第一介电材料层的龟裂存在于该第一及第二导电材料层,以及该第一导线的该内部周边之间,而在第二介电材料层的龟裂存在于该第二及第三导电材料层,以及该第二导线的该内部周边之间。
本发明的目的是提供一种接合垫的制作方法。上述接合垫的制作方法,包括:提供半导体芯片;形成第一介电材料层于该半导体芯片上方;形成第一导电材料层于该第一介电材料层上方;形成第二介电材料层于该第一导电材料层上;图案化该第二介电层,以形成多个开口于其中,该多个开口包含中央的开口阵列,以及第一线状开口,其大体上围绕该中央的开口阵列;提供导电材料于所述中央的开口阵列与所述第一线状开口之中,以分别形成多个导通孔与一导线;以及提供第二导电材料层于该第二介电材料层及所述导通孔与导线上方;其中该第二介电材料层的龟裂存在于该第一及第二导电材料层,以及设置于该导线的内部周边之间,且相邻的所述导通孔之间的距离约等于所述导线与其相邻的导通孔的最小间距。
根据本发明的接合垫的制作方法,其中所述第二介电材料层包含复合式介电层。
根据本发明的接合垫的制作方法,还包括:形成第三介电材料层于所述第二导电材料层上方;图案化所述第三介电材料层,以形成第二多个开口于其中,所述第二多个开口包含中央的开口阵列,以及第二线状开口大体上围绕所述中央的开口阵列;以及提供导电材料于所述第二多个开口之中。
根据本发明的接合垫的制作方法,其中形成于所述第二介电材料层内的所述第一线状开口的内部周边的尺寸与对应于所述第三介电材料层内的所述第二线状开口的内部周边的尺寸不相同。
根据本发明的接合垫的制作方法,其中形成于所述第二介电材料层内的所述第一线状开口的内部周边的尺寸与对应于所述第三介电材料层内的所述第二线状开口的内部周边的尺寸大体上相同。
上述导线对包围导通孔的介电层中产生的龟裂提供阻障层。虽然龟裂会无法控制地散布于导通孔阵列的导通孔之间,但通过导线可阻隔上述龟裂,因此,龟裂不会散布至芯片或晶片的附近区域。导线可以具有各种不同形状及尺寸,以配合适当的应用。另外,由于导线具有大体上连续的长度,因此,导线也会对接合垫提供额外的强度。
附图说明
接下来,通过配合附图详细说明本发明的较佳实施例,以更明显地公开及揭示本发明的优点及特征。而且,相同元件标号代表相同的元件,其中:
图1A及图1B显示已知接合垫的导通孔图案的剖面图,其中该已知接合垫显示金属层间介电层内蔓延的龟裂现象;
图2A及图2B分别显示具体实施例结合导线排列及接合垫的半导体芯片的剖面图及平面图;
图3显示设有导线排列的多层接合垫的剖面图;以及
图4显示设有另一导线排列于连接金属层间的多层接合垫的剖面图。
其中,附图标记说明如下:
1~接合垫;2A~接合垫金属层;2B~接合垫金属层;10~导通孔;12~介电材料层;14~龟裂。
20~接合垫;22A~接合垫金属层;22B~接合垫金属层;24~金属层间介电层;26~导通孔;28~导线;30~龟裂;32~多层接合垫结构;34~金属层;36~金属层间介电层;38~导通孔;39~导线;40~保护层;42~芯片。
具体实施方式
根据本发明的实施例,公开了使用导通孔阵列的接合垫的设计。而且,上述实施例的接合垫的排列方式可减低在处理及制作芯片时发生的金属层间介电层材料的龟裂现象。
如图2A及图2B所示,公开了包含一对接合垫金属层22A、22B的接合垫20,且金属层间介电层(inter-metal layer;IMD)24设置于接合垫金属层22A和22B之间。如图2A及图2B所示,设置多个导通孔(via)26于金属层间介电层24之中,且形成各别的电性接触于接合垫金属层22A、22B之间。另外,设置导线(line via)28于上述导通孔26的周边部位附近。上述导线28除了在接合垫金属层22A、22B之间形成电性接触之外,而且导线28也会围绕上述导通孔26,而形成隔离阻障层,以预防在进行打线接合(wire bonding)工艺时,所发生的金属层间介电层24内龟裂现象的扩大。因此,即使一开始金属层间介电层24之中发生龟裂30,也仅会扩及导线28附近,且龟裂30无法延伸至接合垫20外部的区域。
在图3中,显示多层接合垫结构32的基本构件,且上述多层接合垫结构32包含由芯片装置(未显示)的末端延伸出来的多个金属层34,且上述金属层34以金属层间介电层36隔开。上述各金属层34可以是通过导通孔38电性连接相邻的金属层34,同时也可以是通过同一层的环绕导通孔38的导线39电性连接相邻的金属层34。接着,除了接合垫结构32的接合位置之外,覆盖保护层40于最上面的金属层34的表面,以封合芯片42,且上述保护层40可避免污染物的污染及提供预防刮伤的保护层。在上述打线接合的工艺中,打线可以是直接接合于最上面的金属层34的接合位置,且接合至芯片封装体,或者,上述打线也可以是接合于接合的金属图案之间,且接合至芯片封装体。因此,于芯片42与封装体之间形成电性连接。
在图3中,显示如图2A和图2B所示的导通孔38及导线39的排列方式可以实施于多层接合垫32之中任两相邻金属层34之间。在一个较佳实施例中,当上述导通孔及导线的排列方式设置于接合垫顶部的两相邻金属层34之间时,导通孔38及导线39的排列方式的抗龟裂性能可以得到最有效的利用。
上述导线39除了可提供金属层间介电层36龟裂现象扩大的阻障层之外,导线39对于在进行芯片封装工艺时所引起的应力上升也可以提供加强的抑制能力。相较于已知接合垫结构,其仅由导通孔38提供接合垫的压缩强度(compressive strength),然而,在本发明的实施例中,由于导线39围绕上述导通孔38的连续长度会对接合垫产生大体上的强度。因此,导线39可以是适当的尺寸及形状,以最大化接触的金属层间的电性连接,且同时最大化接合垫的压缩强度,使得抑制金属层间介电层的龟裂现象,以及其它于制作过程中引发的应力所产生的损伤。在一个实施例中,导线39的宽度“LVW”可以是约为0.5~2倍的导通孔38的宽度“VW”。也就是说,导线39的宽度“LVW”可以是大于、等于或小于导通孔38的宽度。介于导线39与其相邻的导通孔38(离导线39最近的导通孔38)之间的最小间距“LVO”较佳可以是约等于相邻导通孔38之间的距离“VO”。可以了解到的是,虽然在说明的实施例的附图中,显示导线39为矩形,当然也可以使用其它形状的导线39。
虽然在图3中,显示在各金属层34之间设置导线39。但是,在另一个实施例中,本发明当然也可以是,仅使用单一层的导线39于最上面的两金属层34之间,且仅使用矩形导通孔38于其余的金属层34之间。另外,形成于多数层上的导线39(如图3所示),在每一相邻的层上的导线39也可以具有间距,以更增强接合垫32的强度,如图4所示。
如以上所述,设计导线39的布局,以从芯片或芯片封装体的余留部位分离接合垫32的金属层间介电层36,使得当填充导电材料于开口之中时,导通孔38会被填充有导电材料的导线39所围绕。因此,本发明的实施例可提供精简化的高强度通孔的排列方式(导通孔及导线),且上述通孔的排列方式也可以限制金属层间介电层龟裂的程度,且限制其龟裂于导线39所围绕的面积之中。值得注意的是,虽然在图2B所示的是以直线构成的导线39,当然导线39的形状也可以是其它形式。
可以了解的是,虽然金属层间介电层36在附图中显示单一沉积层,但金属层间介电层36当然也可以包含一个或多个金层层间介电层36所构成的复合式介电层。如上述的复合式介电层可减轻金属层间介电层36的内部应力,且由于上述内部应力会促成金属层间介电层36的龟裂现象,因此,复合式介电层也有助于减轻金属层间介电层的龟裂现象。在一个实施例中,但不以此实施例为限,上述复合式介电层可以是双层氧化层结构,且上述复合式介电层的其中一层可以使用高密度等离子体(high density plasma;HDP)的方式制作,而上述复合式介电层的另一层可以使用四乙氧基硅烷(Tetraethylorthosilicate;TEOS)气体的等离子体增强气相沉积(PlasmaEnhanced Chemical Vapor Deposition;PEVCD)法形成。
在一个较佳实施例中,上述导通孔及导线的排列方式的制作方法,可以先提供预先制作有电子构件的衬底44,且沉积介电材料于上述衬底44上方,以形成金属层间介电层36。形成金属层34于上述金属层间介电层36内之后,接着沉积另一金属层间介电层36于该金属层34上方。之后,形成多个开口于金属层间介电层36之中,且接着以导电材料填充上述开口,以形成导通孔阵列。上述开口可以是矩形或圆形,以形成矩形或圆形的导通孔。再者,形成环形开口于上述金属层间介电层36之中。上述环形开口围绕其它的开口,例如上述矩形或圆形的开口,使得当导电材料填充上述环形开口时,形成围绕导通孔38阵列的导线39(如图2所示)。
在一个实施例中,上述填充导电材料于导通孔38及导线39之中的方式可以使用钨插塞工艺完成。在另一实施例中,也可以是使用铝插塞工艺、铜插塞工艺或硅化物插塞工艺完成。在以导电材料填充导通孔38及导线39之后,可以进行化学机械研磨(chemical mechanical polishing;CMP)工艺,以平坦化金属层间介电层36的表面。
可以了解的是,接着可以适当重复进行上述形成金属层34、金属层间介电层36、导通孔38及导线39的工艺,以形成多层接合垫结构,如图3所示。接着,沉积接合的金属图案于最上面的金属层34的顶部表面上方。之后,进行接合打线于该接合的金属图案。
虽然本发明已以较佳实施例公开如上,但其并非用以限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,可作一些更动与润饰,据此,本发明的保护范围应当视随附的权利要求所界定为准。
Claims (12)
1.一种接合垫结构,包含:
第一导电材料层;
介电材料层,设置于所述第一导电材料层上方;
第二导电材料层;
多个导通孔,设置于所述介电材料层之中,且所述导通孔电性连接所述第一导电材料层与所述第二导电材料层;以及
导线,设置于所述导通孔的周边附近,且所述导线设置于所述介电材料层之中,其中相邻的所述导通孔之间的距离等于所述导线与其相邻的导通孔的最小间距。
2.如权利要求1所述的接合垫结构,其中所述导线包含直线形状,且所述直线形状具有外部周边及内部周边,所述导通孔设置于由所述导线的所述内部周边所定义的所述介电材料层的区域内。
3.如权利要求1所述的接合垫结构,其中所述导线围绕所述导通孔。
4.如权利要求1所述的接合垫结构,还包含接合的金属图案,设置于所述第二导电材料层的顶部表面上方;以及
接合打线,连接所述接合的金属图案。
5.如权利要求1所述的接合垫结构,其中所述介电材料层包含复合式介电层。
6.如权利要求1所述的接合垫结构,其中所述导通孔及所述导线包含的导电材料选自钨、铝、铜及硅化物所组成的群组。
7.如权利要求2所述的接合垫结构,其中所述介电材料层的龟裂存在于所述第一及第二导电材料层,以及所述导线的所述内部周边之间。
8.一种接合垫的制作方法,包括:
提供半导体芯片;
形成第一介电材料层于所述半导体芯片上方;
形成第一导电材料层于所述第一介电材料层上方;
形成第二介电材料层于所述第一导电材料层上;
图案化所述第二介电材料层,以形成多个开口于其中,所述多个开口包含中央的开口阵列,以及第一线状开口,其围绕所述中央的开口阵列;
提供导电材料于所述中央的开口阵列与所述第一线状开口之中,以分别形成多个导通孔与一导线;以及
提供第二导电材料层于所述第二介电材料层及所述导通孔与导线上方;
其中所述第二介电材料层的龟裂存在于所述第一及第二导电材料层,以及设置于所述导线的内部周边之间,且相邻的所述导通孔之间的距离等于所述导线与其相邻的导通孔的最小间距。
9.如权利要求8所述的接合垫的制作方法,其中所述第二介电材料层包含复合式介电层。
10.如权利要求8所述的接合垫的制作方法,还包括:
形成第三介电材料层于所述第二导电材料层上方;
图案化所述第三介电材料层,以形成第二多个开口于其中,所述第二多个开口包含中央的开口阵列,以及第二线状开口,其围绕所述中央的开口阵列;以及
提供导电材料于所述第二多个开口之中。
11.如权利要求10所述的接合垫的制作方法,其中形成于所述第二介电材料层内的所述第一线状开口的内部周边的尺寸与对应于所述第三介电材料层内的所述第二线状开口的内部周边的尺寸不相同。
12.如权利要求10所述的接合垫的制作方法,其中形成于所述第二介电材料层内的所述第一线状开口的内部周边的尺寸与对应于所述第三介电材料层内的所述第二线状开口的内部周边的尺寸相同。
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US20080122100A1 (en) | 2008-05-29 |
TW200822330A (en) | 2008-05-16 |
US7679180B2 (en) | 2010-03-16 |
TWI335650B (en) | 2011-01-01 |
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