TWI420628B - 奈米碳管結合墊結構及其方法 - Google Patents

奈米碳管結合墊結構及其方法 Download PDF

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Publication number
TWI420628B
TWI420628B TW095110450A TW95110450A TWI420628B TW I420628 B TWI420628 B TW I420628B TW 095110450 A TW095110450 A TW 095110450A TW 95110450 A TW95110450 A TW 95110450A TW I420628 B TWI420628 B TW I420628B
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Taiwan
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conductive layer
carbon nanotube
layer
bond pad
pad structure
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TW095110450A
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English (en)
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TW200711084A (en
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Chris Wyland
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

奈米碳管結合墊結構及其方法
本發明係關於積體電路(IC)封裝。更特定言之，本發明係關於一半導體基板至一封裝的導線結合與增強導線結合與基板結合墊介面的機械強度。
電子產業繼續依賴半導體技術的進步以在更緊密的區域內實現更高功能之器件。對於許多應用而言，實現更高功能的器件需將大量電子器件整合在一單一矽晶圓內。隨著每一既定矽晶圓區域的電子器件數量增加，製程變得更困難。
針對各種應用已採用許多原則來製造多種半導體器件。此類矽基半導體器件經常包括金氧半導體場效電晶體(MOSFET)(例如，p通道MOS(PMOS)、n通道MOS(NMOS)及互補MOS(CMOS)電晶體、雙極電晶體、BiCMOS電晶體)。此類MOSFET器件包括在一導電閘與矽類基板之間的一絕緣材料，因此該些器件一般稱為IGFET(絕緣閘FET)。
該些半導體器件之各半導體器件一般包括在其上形成許多主動器件的一半導體基板。一給定主動器件之特定結構可在器件類型之間變化。例如，在MOS電晶體內，一主動器件一般包括源極區域與汲極區域與在該等源極區域與汲極區域之間調整電流的一閘極電極。
此外，此類器件可以係在許多晶圓製程中所產生的數位或類比器件(例如，CMOS、BiCMOS、雙極等)。該等基板可以係矽、砷化鎵(GaAs)或適合在其上構建微電子電路的其他基板。
在經歷製程之後，矽晶圓具有一預定數目的器件。測試該些器件。收集並封裝優良的器件。將該等器件結合至使用者指定的封裝。使用結合導線依次連接器件晶粒至外部封裝接針，從而連接結合墊至半導體晶粒上。
導線結合係一固相焊接製程，其中使得二金屬材料(導線與墊表面)緊密接觸。一旦該等表面緊密接觸，便發生電子共用或原子的相互擴散，從而導致導線結合的形成。在導線結合製程中，結合力可引起材料的變形，打破污染層並平滑表面粗糙，其可藉由應用超音波能來增強。熱可加速原子間擴散，從而加速結合形成。結合需足夠強固以抵抗在使用電路期間所遭遇的力量。使用一「結合拉力」試驗機，可測量結合強度。使用此類裝置可篩選顯示強度不足之該等結合。表1顯示特定的拉力取決於結合導線之直徑。
參考圖1A至1C。結合導線5已從結合墊10抬起。此外，周圍材料15已變形。
在導線結合製程期間，執行焊接所需之力可能超過結合墊與基本結構的壓縮強度。一方法係在結合墊所定義的金屬區域內部形成介電墊陣列。在多級金屬器件中，該些陣列係通道陣列，其中沈積層間金屬以連接多個金屬化層。一通道陣列係在一介電層內部的接觸孔配置，介電層能經由使用一適當的導電材料(通常金屬化)填充該等接觸孔來連接一或多個導電層至另一導電層。
結合墊結構可以係圖2所示的一結構。在一範例性三金屬級系統中，在一第一金屬化170上使用一通道陣列160來定義一介電層150。此類介電質可包括(但不限於)氧化矽、氮化矽、氮氧矽或其他有機矽化合物。可在該些通道160內沈積金屬化140並在其上形成一層。在此導電層140上，使用相對該通道陣列160略微交錯的一通道陣列120沈積額外的介電材料130。一般而言，需在多級金屬系統中避免堆疊的通道。可在該些通道陣列120內沈積金屬化110並在其上形成一層。必要時(未顯示)，可使用一鈍化覆蓋在結合墊100中曝露的金屬以保護墊並最終保護器件免受潮濕及其他污染物的影響。已顯示多點處的該些通道陣列與金屬化之結合來增加結合墊與其所結合的任何導線之強度與彈性。
需一技術來提高結合墊結構之強度與彈性使得其所附著的導線可具有更多的附著力，從而減小導線結合破裂的可能性。
頃發現本發明對於增加在一積體電路器件上的結合墊之強度與彈性較有用。在該結合墊之構造中使用奈米碳管取代標準的金屬化。在一範例性具體實施例中，在一積體電路(IC)基板上存在一結合墊結構，該結合墊結構包含具有一頂部表面與一底部表面的一第一導電層，該底部表面接觸該IC基板。在該第一導電層之頂部表面上沈積一介電層，該介電層具有一通道陣列，該通道陣列充滿一奈米碳管材料，該奈米碳管材料係電性耦合至該第一導電層。存在一第二導電層，其具有一頂部表面與一底部表面，該第二導電層之底部表面係電性耦合至該奈米碳管材料。此具體實施例之一特徵包括包含一奈米碳管材料的該第一導電層或該第二導電層。
在另一範例性具體實施例中，在一積體電路(IC)基板上存在一結合墊結構，該結合墊結構包含具有一頂部表面與一底部表面的一第一導電層，該底部表面接觸該IC基板。在該第一導電層之頂部表面上沈積一介電層，該介電層具有一通道陣列，該通道陣列充滿一奈米碳管材料，該奈米碳管材料係電性耦合至該第一導電層。存在一後續導電層，其具有一頂部表面與一底部表面，該後續導電層之底部表面係電性耦合至該奈米碳管材料。
在另一範例性具體實施例中，在一積體電路(IC)基板上存在一結合墊結構，該結合墊結構包含具有一頂部表面與一底部表面的一第一導電層，該底部表面接觸該IC基板。以一預定的晶體定向，在該第一導電層之頂部表面沈積一奈米碳管層。該奈米碳管層具有一通道陣列，該通道陣列充滿一介面材料，該奈米碳管材料係電性耦合至該第一導電層。具有一頂部表面與一底部表面的一後續導電層係電性耦合至該奈米碳管材料。此具體實施例之一特徵係該介面材料可包括選自下列的材料：介電質、金屬化、與重摻雜矽。此外，介電質可包括二氧化矽、富含矽的氧化物、氮氧化矽、氮化矽、甲基矽酸鹽(MSQ)、與含氫矽酸鹽(HSQ)。此外，該介面材料可包括該第一導電層、該第二導電層、鋁、鋁合金、銅及銅合金。奈米碳管層之預定的晶體定向可以係垂直或水平。
在另一具體實施例中，存在一種製造一積體電路(IC)之方法，該積體電路在一IC基板上的結合墊內部具有一奈米碳管結構。該方法包含在該IC上定義一第一導電層，該導電層具有一頂部表面與一底部表面，該底部表面接觸該IC基板。在該介電層上，定義通道區域。在該等通道區域內，形成奈米碳管；該等奈米碳管電性耦合至該第一導電層。一後續導電層具有一頂部表面與一底部表面，該後續導電層之底部表面電性耦合至該奈米碳管材料。此具體實施例之一特徵包括包含金屬化的該第一導電層與該第二導電層。
在另一具體實施例中，存在一種製造一積體電路(IC)之方法，該積體電路在一IC基板上的結合墊內部具有一奈米碳管結構。該方法包含在該IC上定義一第一導電層，該導電層具有一頂部表面與一底部表面；該底部表面接觸該IC基板。在該第一導電層之頂部表面，沈積一介面層。在該介面層上定義通道區域。在該等通道區域內，形成奈米碳管；該等奈米碳管電性耦合至該第一導電層。定義具有一頂部表面與一底部表面的一後續導電層；該後續導電層之底部表面電性耦合至該奈米碳管。此具體實施例之一特徵包括可從下列材料之至少一材料沈積該介面層：介電質、金屬、及金屬合金、與重摻雜矽。此外，該等介電質可選自如下：二氧化矽、富含矽的氧化物、氮氧化矽與氮化矽、甲基矽酸鹽(MSQ)、與含氫矽酸鹽(HSQ)。
本發明之上述概述並不代表本發明之各揭示的具體實施例或各方面。在圖式與下列的詳細說明中提供其他方面及範例性具體實施例。
頃發現本發明在加強一導線結合至在一半導體基板上之結合墊的附著力較有用。使用奈米碳管取代結合墊結構中的金屬化。例如，使用奈米碳管取代通道的金屬化填料。奈米碳管強度高，一大約1000 G Pa之彈性係數對大約69 G Pa之鋁彈性係數。此外，奈米碳管之抗拉強度係大約170 M Pa對鋁的124 M Pa。電性上，奈米碳管提供足夠的導電率以電性耦合結合墊之多個金屬層。
在依據本發明之一範例性具體實施例中，通常充滿金屬的通道充滿奈米碳管材料。參考圖3A。結合墊300具有三金屬化層310、330、350。層間介電層320、340夾於該些金屬化層310、330、350之間。在該些層間介電層320、340內部係通道陣列325、345。該些通道陣列充滿奈米碳管材料。在最頂部的金屬層350上附著一導線結合360。注意，金屬層之數目未必限於三層。可考慮一奈米碳管結構370作為一導電層310、奈米管材料325、層間介電質320之一組合物。現代的積體電路器件可具有四、五、六或更多的層。因此，可針對一給定製程所需，在各層間介電質通道陣列中使用一奈米碳管結構370來構造結合墊。一CVD製程可用於使用該奈米碳管材料來填充該等通道325、345。在一範例性具體實施例中，取決於製程需求，可採用一垂直或水平方向來定向該奈米碳管材料之晶體定向(即，該奈米碳管材料在結晶期間的生長方向)。在另一範例性具體實施例中，該奈米碳管材料之一部分可垂直定向而另一部分可水平定向。
例如介電材料可包括(但不限於)氧化矽、氮氧化矽、或氮化矽、或富含矽的氧化物。其他的介電質可包括有機矽化合物。該些介電質可包括旋塗式介電質(例如，甲基矽酸鹽(MSQ)與含氫矽酸鹽(HSQ))。一給定製程之特定需求將決定最適當的介電質。
在另一範例性具體實施例中，結合墊400具有三奈米碳管層410、430、450，代替圖3A之標準金屬化。參考圖3B。層間介電層420、440夾於該些奈米碳管層410、430、450之間。在該些層間介電層420、440內部係通道陣列425、445。該些通道陣列充滿標準金屬化。在最頂部的奈米管層450上附著一導線結合460(代替金屬化)。可考慮將該奈米碳管結構470(如圖3A之情況)作為一導電層410、奈米管材料425、與層間介電質420之一組合物。
在另一範例性具體實施例中，結合墊500具有三奈米碳管層510、530、550，代替圖3A之標準金屬化。參考圖3C。層間介電層520、540夾於該些奈米碳管層510、530、550之間。在該些層間介電層520、540內部係通道陣列525、545。該些通道陣列亦充滿奈米碳管材料。因而，已使用奈米碳管材料取代結合墊500之金屬化。在最頂部的奈米碳管層550上附著一導線結合560。可考慮將該奈米碳管結構570作為一第一奈米管材料層510、奈米管材料525、與層間介電質520之一組合物。
可在積體電路器件之金屬化步驟處理中實施奈米碳管之使用。例如，在使用奈米碳管材料填充通道時，可使用一化學汽相沈積(CVD)製程。此類製程將與標準積體器件處理相互交錯。在頒於2003年11月13日的Haase之標題為「使用奈米碳管在一半導體器件內的一主動區域與一導電層之間提供導電率」的美國專利申請公開案(US 2003/0211724 A1)中可查找背景資訊，其以引用方式全體併入本文。
參考圖4A。在一範例性具體實施例中，一結合墊包括三層。第一層係一導電材料435。該導電材料可以係鋁或其合金，或銅及其合金，但並不限於該些金屬。其他的導電材料可包括摻雜的足夠使矽導電的多晶矽材料。在該第一層435上，可沈積一介電層415。可在此介電層415內定義接觸孔或通道425。該等通道425之深度使得存在對該導電材料435之存取。在該些通道425內部形成奈米管材料445。在本範例中，可經由化學汽相沈積(CVD)來形成該奈米管材料。其他技術包括電漿增強型化學汽相沈積(PEVCD)。取決於所涉及的處理參數，該奈米管材料445之晶體定向可以係垂直或水平。一第二或後續導電材料465可耦合至該奈米管材料445。可取決於在一給定製程技術中所使用的金屬層之數目來重複該奈米碳管結構475(包括層435、425、415、465)。
參考圖4B。在圖4A之具體實施例之一修改中，該第一層係一導電材料435a。在該第一導電層435a上，可沈積一第二導電層415a以取代該介電層415。在此介電層415內可定義通道425a。該等通道425a之深度使得存在對該導電材料435a之存取。在該些通道425a內部形成奈米管材料445a。因而，使用一第二導電層415a環繞該奈米管材料445a。該第二導電層415a可以係類似該第一導電層435a的一金屬化。一第二或後續導電材料465a可耦合至該奈米管材料445。可取決於在一給定製程技術中所使用的金屬層之數目來重複該奈米碳管結構475a(包括層435a、425a、415a、465a)。
可採用許多方向來相對在結合墊處的矽基板定向該等奈米碳管。在上述的其中施加一向上垂直力455、455a的範例性結合墊結構中，全部奈米管域之平均垂直應力相對鋁小大約36%。對於50%鋁與50%奈米管的一垂直組合物，平均垂直應力455a比單獨的鋁小46%。而且，對於50% SiO2 與50%奈米管的一垂直組合物，平均垂直應力455要比單獨的鋁小46%。
參考圖5。在另一範例性具體實施例中，在一導電材料535上，沈積奈米管材料515使得其晶體定向為水平。在此奈米管材料515上定義通道525。在該等通道525內沈積介電材料525。在圖5之結構的一變化中，可在該等通道內沈積導電材料以取代介電材料525。一第二或後續導電材料555可耦合至該奈米管材料515。可取決於在一給定製程技術中所使用的金屬層之數目來重複該奈米碳管結構575(包括層515、525、535、555)。
在如範例性具體實施例所述來應用本發明時，可使用圖6所概述的一範例性製程。在IC器件製造期間，可併入添加奈米管材料。在一製程600中，在結合墊上定義在IC器件上的一導電層610。在該導電層610上，形成一介電層620。在該介電層上定義通道區域630以提供從該導電層610至後續導電層的電性連接。在通道區域內形成奈米管640。必要時，可定義另外的奈米管/介電質/導電層結構650。藉由在一給定IC器件設計中可能的金屬層之數目來決定該些結構之數目。該些數目可在二、三、四或更多金屬層之範圍。
參考圖7。在另一範例性製程700中，定義一導電層710。在該導電層710上，定義一奈米管層720。在該奈米管層720上，定義一奈米管通道區域730。然後在奈米管通道區域中沈積介電質740。必要時，可形成額外的結構750。在此範例性製程之一變化中，可不在該等奈米管通道區域內沈積介電質740而使用導電材料(通常金屬化)。
儘管參考數個特定的範例性具體實施例已說明本發明，但習知此項技術者將認識到可對其作許多變化而不脫離隨附申請專利範圍所提出的本發明之精神與範疇。
5．．．結合導線
10．．．結合墊
15．．．周圍材料
100．．．結合墊
110．．．金屬化
120．．．通道
130．．．介電材料
140．．．導電層
150．．．介電層
160．．．通道陣列
170．．．第一金屬化
300．．．結合墊結構
310．．．第一導電層/金屬化層
320．．．介電層
325．．．奈米碳管材料/通道陣列
330．．．第二導電層/金屬化層
340．．．介電層
345．．．通道(陣列)
350．．．金屬化層
360．．．導線結合
370．．．奈米碳管結構
400．．．結合墊
410．．．第一導電層/奈米碳管層
415．．．介電層
415a．．．第二導電層
420．．．介電層
425．．．通道(陣列)/奈米管材料
425a．．．通道
430．．．第二導電層/奈米碳管層
435．．．導電材料
435a．．．導電材料/第一導電層
440．．．介電層
445．．．通道陣列/奈米管材料
445a．．．奈米管材料
450．．．奈米碳管層
455．．．向上垂直力/平均垂直應力
455a．．．向上垂直力/平均垂直應力
460．．．導線結合
465．．．導電材料
465a．．．導電材料
470．．．奈米碳管結構
475．．．奈米碳管結構
475a．．．奈米碳管結構
500．．．結合墊
510．．．第一導電層/奈米碳管層
515．．．通道/奈米管材料
520．．．介電層
525．．．通道陣列/奈米管材料/介電材料
530．．．第二導電層/奈米碳管層
535．．．第一導電層/導電材料
540．．．介電層
545．．．通道陣列/介面材料/介電質
550．．．奈米碳管層
555．．．導電材料
560．．．導線結合
570．．．奈米碳管結構
575．．．奈米碳管結構
600．．．製程
610．．．結合墊/導電層
620．．．介電層
630．．．介電層
640．．．通道區域
650．．．導電層
700．．．製程
710．．．導電層
720．．．奈米管層
730．．．奈米管通道區域
740．．．奈米管通道區域
750．．．結構
考慮本發明之各種具體實施例之上述的詳細說明且連接隨附圖式，可更全面地理解本發明，其中：圖1A至1C(先前技術)顯示結合導線抬起的一範例性結合墊結構；圖2與2A(先前技術)顯示具有三金屬化層的一範例性傳統結合結構；圖3A至3C顯示依據本發明之一結合墊結構之範例性具體實施例；圖4與4A採用俯視圖與側視圖來顯示奈米管在一介電質包圍的垂直方向上定向的一結合墊結構之一範例性具體實施例；圖4B採用側視圖來顯示在一導電材料包圍的一垂直方向上定向奈米管的一結合墊結構之一範例性具體實施例；圖5與5A採用俯視圖與側視圖來顯示垂直方向上定向的奈米管圍繞介電材料的一結合墊結構之一範例性具體實施例；圖6係依據本發明之一具體實施例構建併入奈米管的一結合墊之步驟的一流程圖；以及圖7係依據本發明之一具體實施例構建併入奈米管的一結合墊之步驟的一流程圖。
300．．．結合墊結構
310．．．第一導電層/金屬化層
320．．．介電層
330．．．第二導電層/金屬化層
325．．．通道陣列/奈米碳管材料
340．．．介電層
345．．．通道陣列/通道
350．．．金屬化層
360．．．導線結合
370．．．奈米碳管結構

Claims (17)

  1. 一種結合墊結構(300)，其在一積體電路(IC)基板上，該結合墊結構包含：一第一導電層(310)，其具有一頂部表面與一底部表面，該底部表面接觸附著於該IC基板；一介電層(320)，其沈積於該第一導電層之頂部表面上，該介電層具有一通道陣列，該通道陣列之各通道充滿一奈米碳管材料(325)，該奈米碳管材料電性耦合至該第一導電層(310)；以及一第二導電層(330)，其具有一頂部表面與一底部表面，該第二導電層之底部表面電性耦合至該奈米碳管材料(325)。
  2. 如請求項1之結合墊結構(400)，其中該第一導電層包含一奈米碳管材料(410)。
  3. 如請求項1之結合墊結構(400)，其中該第二導電層包含一奈米碳管材料(430)。
  4. 如請求項1之結合墊結構，其中該第一導電層係金屬化(310)。
  5. 如請求項1之結合墊結構，其中該第二導電層係金屬化(330)。
  6. 一種結合墊結構(300)，其在一積體電路(IC)基板上，該結合墊結構包含：一第一導電層(310)，其具有一頂部表面與一底部表面，該底部表面接觸附著於該IC基板；一介電層(320)，其沈積於該第一導電層之頂部表面上，該介電層具有一通道陣列(325)，該通道陣列之各通道充滿一奈米碳管材料(325)，該奈米碳管材料電性耦合至該第一導電層(310)；以及一後續導電層(330)，其具有一頂部表面與一底部表面，第二後續導電層之底部表面電性耦合至該奈米碳管材料(325)。
  7. 一種結合墊結構，其在一積體電路(IC)基板上，該結合墊結構包含：一第一導電層(535)，其具有一頂部表面與一底部表面，該底部表面接觸該IC基板；一奈米碳管層(515)，其以一預定的晶體定向沈積於該第一導電層(535)之頂部表面上，該奈米碳管層(445、445a)具有一通道陣列(525)，該通道陣列(525)充滿一介面材料(545)，該奈米碳管材料(515)電性耦合至該第一導電層(535)；以及一後續導電層(555)，其具有一頂部表面與一底部表面，該後續導電層之底部表面電性耦合至該奈米碳管材料(515)。
  8. 如請求項7之結合墊結構，其中該第一導電層(535)與該後續導電層(555)包括金屬化。
  9. 如請求項7之結合墊結構，其中該介面材料包括選自下列的至少一者：介電質(545)、金屬化、及重摻雜矽。
  10. 如請求項7之結合墊結構，其中介電質(545)包括下列的一或多個：二氧化矽、富含矽的氧化物、氮氧化矽、與氮化矽、甲基矽酸鹽(MSQ)與含氫矽酸鹽(HSQ)。
  11. 如請求項9之結合墊結構，其中該介面材料包括下列的至少一者：該第一導電材料、該第二導電材料、鋁、鋁合金、銅、與銅合金。
  12. 如請求項7之結合墊結構，其中該奈米碳管層(445、445a、515)之預定的晶體定向係選自下列：水平(515)、垂直(445a)。
  13. 一種製造在一IC基板上的結合墊內部具有一奈米碳管結構(600)之一積體電路(IC)之方法，該方法包含：在該IC上定義一第一導電層(610)，該導電層具有一頂部表面與一底部表面，該底部表面接觸該IC基板；在該第一導電層之頂部表面上沈積一介電層(620)；在該介電層上定義通道區域(630)；在該等通道區域內形成奈米碳管(640)，該等奈米碳管電性耦合至該第一導電層；以及定義具有一頂部表面與一底部表面的一後續導電層(650)，該後續導電層之底部表面電性耦合至該等奈米碳管。
  14. 如請求項13之製造一IC之方法，其中該第一導電層與該後續導電層進一步包含金屬化。
  15. 一種製造在一IC基板上的結合墊內部具有一奈米碳管結構(700)之一積體電路(IC)之方法，該方法包含：在該IC上定義一第一導電層(710)，該導電層具有一頂部表面與一底部表面，該底部表面接觸該IC基板；在該第一導電層之頂部表面上沈積一奈米管層(720)；在奈米管層上定義通道區域(730)；在該奈米管層內的該等通道區域內沈積一介面材料(740)；以及定義具有一頂部表面與一底部表面的一後續導電層(750)，該後續導電層之底部表面電性耦合至該等奈米碳管層。
  16. 如請求項13之製造一IC之方法，其中從下列材料之至少一材料來沈積該介面層：介電質、金屬、與金屬合金、及重摻雜矽。
  17. 如請求項15之製造一IC之方法，其中該介電質選自下列：二氧化矽、富含矽的氧化物、氮氧化矽、與氮化矽、甲基矽酸鹽(MSQ)、與含氫矽酸鹽(HSQ)。
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