TWI424544B - 積體電路裝置 - Google Patents

積體電路裝置 Download PDF

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Publication number
TWI424544B
TWI424544B TW100111301A TW100111301A TWI424544B TW I424544 B TWI424544 B TW I424544B TW 100111301 A TW100111301 A TW 100111301A TW 100111301 A TW100111301 A TW 100111301A TW I424544 B TWI424544 B TW I424544B
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Taiwan
Prior art keywords
pad
metal pad
integrated circuit
circuit device
metal
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TW100111301A
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English (en)
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TW201240043A (en
Inventor
Tai Hung Lin
Chang Tien Tsai
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Novatek Microelectronics Corp
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Publication date
Application filed by Novatek Microelectronics Corp filed Critical Novatek Microelectronics Corp
Priority to TW100111301A priority Critical patent/TWI424544B/zh
Priority to US13/423,264 priority patent/US8618660B2/en
Publication of TW201240043A publication Critical patent/TW201240043A/zh
Priority to US14/062,899 priority patent/US9041201B2/en
Application granted granted Critical
Publication of TWI424544B publication Critical patent/TWI424544B/zh
Priority to US14/666,322 priority patent/US20150194399A1/en
Priority to US14/740,286 priority patent/US9627337B2/en
Priority to US15/412,072 priority patent/US9881892B2/en

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Description

積體電路裝置
本發明是有關於一種積體電路裝置，且特別是有關於一種以打線取代部分內連線的積體電路裝置。
積體電路裝置的內部的電性傳遞常用金屬內連線來達成，而其連接的方式和途徑則透過積體電路設計軟體來做出實際圖面。這些金屬內連線是以微影蝕刻等製程產生，因此配置方式、長度和寬度都會受到製程能力的限制，也限制了連接的電性表現。另一方面，在積體電路裝置與外部裝置的端子的電性傳遞方面，則常用打線技術來達成。打線技術是利用打線製程所產生的金屬線來連接，提供了更好的電性表現，在設計上也少了限制而有更佳的設計彈性。
本發明提供一種積體電路裝置，具有較佳的電性表現與靜電防護功能。
本發明的積體電路裝置包括一基材、一第一內接墊、一第二內接墊、一外接墊以及一打線。基材內埋一第一電路、一第二電路、至少一內連線與一靜電防護電路。第一內接墊配置於基材的表面並電性連接第一電路。第二內接墊配置於基材的表面並電性連接第二電路。外接墊配置於基材的表面。第一內接墊經由打線電性連接第二內接墊。第一內接墊經由內連線電性連接靜電防護電路。靜電防護電路電性連接外接墊。外接墊用以電性連接一外部封裝接腳。
在本發明之一實施例中，第一電路為邏輯電路、數位電路或記憶體電路。
在本發明之一實施例中，第二電路為邏輯電路、數位電路或記憶體電路。
在本發明之一實施例中，第一內接墊包括一第一金屬墊、一第二金屬墊與一介電層，第一金屬墊電性連接第二金屬墊，介電層位於第一金屬墊與第二金屬墊之間。此外，第一金屬墊例如具有一打線接合區與一導通區，第一內接墊更包括多個導通件，貫穿介電層並連接第一金屬墊的導通區與第二金屬墊。另外，導通區例如位於打線接合區的一側。導通區環繞打線接合區。再者，第二金屬墊例如具有多個開孔，位於打線接合區下方。此外，第一金屬墊與第二金屬墊的材質例如為銅。另外，第一金屬墊的材質例如為鋁，第二金屬墊的材質為銅。
在本發明之一實施例中，第二內接墊包括一第一金屬墊、一第二金屬墊與一介電層，第一金屬墊電性連接第二金屬墊，介電層位於第一金屬墊與第二金屬墊之間。
在本發明之一實施例中，外接墊包括一第一金屬墊、一第二金屬墊與一介電層，第一金屬墊電性連接第二金屬墊，介電層位於第一金屬墊與第二金屬墊之間。
在本發明之一實施例中，基材的表面具有一線路淨空區，環繞外接墊，線路淨空區的外緣與外接墊的外緣的距離介於2微米至50微米。線路淨空區的外緣與外接墊的外緣的距離較佳是10微米。
基於上述，在本發明的積體電路裝置中，內部電路利用內接墊以及打線而電性連接，且外接墊與內接墊之間連接有靜電防護電路。因此，本發明的積體電路裝置具有較佳的電性表現，且可避免內部電路受到靜電的破壞。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A是本發明一實施例的積體電路裝置的剖面示意圖，圖1B是圖1A的積體電路裝置的電路方塊圖。請參照圖1A，本實施例的積體電路裝置100包括一基材110、一第一內接墊120、一第二內接墊130、一外接墊140以及一打線150。基材110內埋一第一電路160、一第二電路170、至少一內連線112與一靜電防護電路180。本實施例的基材110還可包括多條內連線114。第一內接墊120配置於基材110的表面並電性連接第一電路160。第二內接墊130配置於基材110的表面並電性連接第二電路170。外接墊140配置於基材110的表面。第一內接墊120經由打線150電性連接第二內接墊130。第一內接墊120經由內連線112電性連接靜電防護電路180。靜電防護電路180電性連接外接墊140。外接墊140用以電性連接一外部封裝接腳T10。
在其他實施例中，外接墊140也可以直接經由內連線112電性連接第一內接墊120而不經由靜電防護電路180。
請參照圖1A與圖1B，一外部系統S10所提供的訊號會先傳遞至外部封裝接腳T10，再從外部封裝接腳T10經由打線、外接墊140與內連線114傳遞至靜電防護電路180。接著，訊號再從靜電防護電路180經由內連線112、第一內接墊120與打線150傳遞至第二內接墊130，再從第二內接墊130經由內連線114傳遞至第二電路170。
在本實施例的積體電路裝置100中，基材110內的第一電路160與第二電路170不僅可採用內連線的路徑進行訊號傳遞，更可以經由第一內接墊120、打線150與第二內接墊130的路徑進行訊號傳遞。打線150是利用打線製程所形成的位於基材110之外的金屬線，打線150的線寬遠較內連線的線寬大，因此打線150的電阻值較小而可獲得較佳的電性表現。另外，利用打線150來進行第一電路160與第二電路170之間的訊號傳遞，可避免採用內連線進行訊號傳遞時必須想辦法避開基材110內的各種電路的困擾，也可減少形成內連線所需的金屬層的數量而進一步節省形成內連線所需的光罩數量，大幅縮短了積體電路裝置100的設計時程。
在本實施例的積體電路裝置100中，外接墊140與第一內接墊120之間存在靜電防護電路180。靜電防護電路180可避免第一電路160與第二電路170被從外部封裝接腳T10與外接墊140傳來的靜電破壞。
舉例而言，本實施例的第一電路160可以是邏輯電路、數位電路、記憶體電路或其他電路。第二電路170也可以是邏輯電路、數位電路、記憶體電路或其他電路。
圖2是圖1A之第一內接墊的剖示圖，而圖3與圖4分別是圖2的兩個金屬墊的正視圖。請參照圖2，本實施例的第一內接墊120包括一第一金屬墊122、一第二金屬墊124與一介電層126，第一金屬墊122電性連接第二金屬墊124，介電層126位於第一金屬墊122與第二金屬墊124之間。由於第一內接墊120採用了雙層金屬墊的結構，在進行打線製程時可降低打線的衝擊力對於第一內接墊120下方的結構的影響。因此，第一內接墊120下方也可配置電路，有利於縮減積體電路裝置的整體尺寸。
請參照圖2與圖3，第一金屬墊122例如具有一打線接合區R12與一導通區R14。第一內接墊120更包括多個導通件128，貫穿介電層126並連接第一金屬墊122的導通區R14與第二金屬墊124。導通區R14位於打線接合區R12的一側。打線接合區R12是後續進行打線製程時承受衝擊力的區域，打線接合區R12不配置導通件128的設計方式可提升第一內接墊120的耐衝擊強度。請參照圖2與圖4，第二金屬墊124可具有多個開孔P10(僅繪示於圖4)，位於打線接合區R12下方。開孔P10也可提升第一內接墊120的耐衝擊強度。另外，第一金屬墊122的打線接合區R12則保持完整以與打線保持最大的接觸面積而提升電性表現。藉由上述設計，第一內接墊120會較具有彈性而可減輕打線製程中施加在第一內接墊120上的應力的影響，以便於在第一內接墊120下方配置電路。請參照圖2，第一金屬墊122與第二金屬墊124的材質例如都是銅。或者，第一金屬墊122的材質為鋁，而第二金屬墊124的材質為銅。
圖5是另一實施例的第一內接墊的第一金屬墊的正視圖。請參照圖5，本實施例的第一金屬墊的導通區R24是環繞打線接合區R22。當然，導通區R24與打線接合區R22的相對位置也可採用其他適當的變化型態。
請參照圖1A，第二內接墊130與外接墊140也都可以採用類似第一內接墊120的結構，亦即由雙層金屬墊與位於雙層金屬墊之間的介電層所構成，以提升第一內接墊120的耐衝擊強度。
圖6是本發明另一實施例之基材的表面的局部示意圖。請參照圖6，本實施例之基材的表面具有一線路淨空區R30，環繞外接墊200。線路淨空區R30的外緣與外接墊200的外緣的距離D10介於2微米至50微米，線路淨空區R30的外緣與外接墊200的外緣的距離D10較佳是10微米。線路淨空區R30可避免線路被打線製程的衝擊力破壞。相似地，前述實施例的內接墊的外圍也可設置線路淨空區。
圖7是本發明另一實施例之外接墊與其周邊線路的配置方式的示意圖。請參照圖6與圖7，圖6是以外接墊200位於基材的最表層的部分來說明。然而，外接墊也可以如圖2的實施例所述，採用雙層金屬墊的設計。外接墊採用雙層金屬墊的設計時，下層金屬墊300與周圍的線路的關係可參照圖7。亦即是，圖7中的下層金屬墊300僅相當於圖2的第二金屬墊124，而下層金屬墊300上方會有相當於圖2的第一金屬墊122的上層金屬墊。然而，圖7重點在說明下層金屬墊300與同一層的其他線路的關係，故在此並不繪示上層金屬墊。下層金屬墊300所在的金屬層通常會形成有橫向和縱向交錯網狀格線(metal mesh)310，常見有對地格線(ground mesh)或電源格線(power mesh)。這些格線在遇到下層金屬墊300時，若非必須與下層金屬墊300連接者，則應斷開而與下層金屬墊300保持一距離D20，此距離D20介於0.5微米至10微米，此距離D20較佳是2微米。
綜上所述，在本發明的積體電路裝置中，內部電路利用內接墊以及打線而電性連接，金屬打線可提供較佳的電性表現，且設計限制較少而可縮短設計時程，並可減少形成內連線的金屬層的數量而降低成本。另外，在本發明的積體電路裝置中，外接墊與內接墊之間連接有靜電防護電路，因此可避免內部電路受到靜電的破壞。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．積體電路裝置
110．．．基材
120．．．第一內接墊
122．．．第一金屬墊
124．．．第二金屬墊
126．．．介電層
128．．．導通件
130．．．第二內接墊
140、200．．．外接墊
150．．．打線
160．．．第一電路
170．．．第二電路
180．．．靜電防護電路
300．．．下層金屬墊
310．．．格線
T10．．．外部封裝接腳
R12、R22．．．打線接合區
R14、R24．．．導通區
R30．．．線路淨空區
D10、D20．．．距離
圖1A是本發明一實施例的積體電路裝置的剖面示意圖。
圖1B是圖1A的積體電路裝置的電路方塊圖。
圖2是圖1A之第一內接墊的剖示圖。
圖3與圖4分別是圖2的兩個金屬墊的正視圖。
圖5是另一實施例的第一內接墊的第一金屬墊的正視圖。
圖6是本發明另一實施例之基材的表面的局部示意圖。
圖7是本發明另一實施例之外接墊與其周邊線路的配置方式的示意圖。
100．．．積體電路裝置
110．．．基材
120．．．第一內接墊
130．．．第二內接墊
140．．．外接墊
150．．．打線
160．．．第一電路
170．．．第二電路
180．．．靜電防護電路
T10．．．外部封裝接腳

Claims (15)

  1. 一種積體電路裝置，包括：一基材，內埋一第一電路與一第二電路；一第一內接墊，配置於該基材的表面且暴露於該基材外，並電性連接該第一電路；一第二內接墊，配置於該基材的表面且暴露於該基材外，並電性連接該第二電路；一外接墊，配置於該基材的表面且暴露於該基材外，並電性連接該第一內接墊；以及一打線，其中該第一內接墊經由該打線電性連接該第二內接墊。
  2. 如申請專利範圍第1項所述之積體電路裝置，其中該第一電路為邏輯電路、數位電路或記憶體電路。
  3. 如申請專利範圍第1項所述之積體電路裝置，其中該第二電路為邏輯電路、數位電路或記憶體電路。
  4. 如申請專利範圍第1項所述之積體電路裝置，其中該第一內接墊包括一第一金屬墊、一第二金屬墊與一介電層，該第一金屬墊電性連接該第二金屬墊，該介電層位於該第一金屬墊與該第二金屬墊之間。
  5. 如申請專利範圍第4項所述之積體電路裝置，其中該第一金屬墊具有一打線接合區與一導通區，該第一內接墊更包括多個導通件，貫穿該介電層並連接該第一金屬墊的該導通區與該第二金屬墊。
  6. 如申請專利範圍第5項所述之積體電路裝置，其中該導通區位於該打線接合區的一側。
  7. 如申請專利範圍第5項所述之積體電路裝置，其中該導通區環繞該打線接合區。
  8. 如申請專利範圍第5項所述之積體電路裝置，其中該第二金屬墊具有多個開孔，位於該打線接合區下方。
  9. 如申請專利範圍第4項所述之積體電路裝置，其中該第一金屬墊與該第二金屬墊的材質為銅。
  10. 如申請專利範圍第4項所述之積體電路裝置，其中該第一金屬墊的材質為鋁，該第二金屬墊的材質為銅。
  11. 如申請專利範圍第1項所述之積體電路裝置，其中該第二內接墊包括一第一金屬墊、一第二金屬墊與一介電層，該第一金屬墊電性連接該第二金屬墊，該介電層位於該第一金屬墊與該第二金屬墊之間。
  12. 如申請專利範圍第1項所述之積體電路裝置，其中該外接墊包括一第一金屬墊、一第二金屬墊與一介電層，該第一金屬墊電性連接該第二金屬墊，該介電層位於該第一金屬墊與該第二金屬墊之間。
  13. 如申請專利範圍第1項所述之積體電路裝置，其中該基材的表面具有一線路淨空區，環繞該外接墊，該線路淨空區的外緣與該外接墊的外緣的距離介於2微米至50微米。
  14. 如申請專利範圍第13項所述之積體電路裝置，其中該線路淨空區的外緣與該外接墊的外緣的距離為10微米。
  15. 如申請專利範圍第1項所述之積體電路裝置，更包括一靜電防護電路，電性連接該第一內接墊與該外接墊。
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US20120248606A1 (en) 2012-10-04
US20140048935A1 (en) 2014-02-20
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US8618660B2 (en) 2013-12-31
US9041201B2 (en) 2015-05-26

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