TWI436699B - 多層導通孔疊構 - Google Patents

多層導通孔疊構 Download PDF

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TWI436699B
TWI436699B TW099122895A TW99122895A TWI436699B TW I436699 B TWI436699 B TW I436699B TW 099122895 A TW099122895 A TW 099122895A TW 99122895 A TW99122895 A TW 99122895A TW I436699 B TWI436699 B TW I436699B
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metal layer
multilayer
opening
stack
hole wall
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TW099122895A
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TW201204196A (en
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Chih Kuang Yang
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Princo Corp
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Description

多層導通孔疊構
本發明係關於一種多層導通孔疊構，特別有關一種應用於軟性半導體或軟性多層基板之多層導通孔疊構。
多層基板用於製作封裝基板、印刷電路板、軟性封裝基板及軟性電路板等領域，整合成高密度系統為現今電子產品小型化必然之趨勢，特別是當前業界均不斷地投入研發更輕、更薄、更具可撓性之軟性積體電路以及軟性多層基板，製作各種應用更為廣泛之軟性電子產品。不僅能更有效地應用於各類產品，同時更符合商品微型化之需求。軟性多層基板之厚度更薄，積體電路及多層基板之繞線密度(routing density)要求便越高。
請參考第1圖，係顯示習知堆疊式導通孔(Stacked VIA)技術形成多層埋孔之多層導通孔疊構，以提高積體電路及多層基板之繞線密度之方法。如第1圖中所示，多層導通孔疊構此方法係將積體電路或多層基板中位於不同層之金屬層10、20及30(金屬線路或焊墊層)均設置於垂直對應之位置，於製作各別之介電層80及90後，再於金屬層10、20位置上製作一垂直之導通孔，填入導通金屬材料，形成導通孔金屬60、70，用以電性連接位於上下不同層之金屬層10、20及30(金屬線路或焊墊層)。此係為一種有效縮小繞線密度之技術，惟其僅適用於硬式之積體電路及多層基板，而不適用於軟性積體電路以及軟性多層基板。主要係因此多層之導通孔結構之堆疊特性，大量金屬材料設置於一密集之區域內，致使其幾不具可撓性，若將此技術應用於製作軟性積體電路以及軟性多層基板，當依此種習知技術製作之堆疊式導通孔被折曲時，折曲的動作很容易對其產生結構性之破壞。
請參考第2圖，亦為現有習知技術另一種堆疊式導通孔(Stacked VIA)之技術，形成一越層孔(盲孔)之多層導通孔疊構，以提高積體電路及多層基板之繞線密度之方法。此方法係將積體電路或多層基板中位於不同層之金屬層10或20(金屬線路或焊墊層)均設置於垂直對應之位置，分別以介電層80或90與其他層相隔，而利用單一垂直之導通孔，以一貫之。再以蝕刻法或是增層法形成第2圖中所示之形成導通孔金屬60，使金屬層10、20電性連接。惟，同樣地，此多層導通孔疊構亦僅適用於硬式之積體電路及多層基板，主要亦因此多層導通孔疊構之堆疊特性，大量金屬材料設置於一密集之區域內，致使其幾不具可撓性。是以，其亦不適用於軟性積體電路以及軟性多層基板。
請參考第3圖，係顯示另一習知技術堆疊式導通孔技術形成一越層孔，且具有斜孔壁之多層導通孔疊構。與第2圖中所示之多層導通孔疊構相似，此方法係將積體電路或多層基板中位於不同層之金屬層10或20(金屬線路或焊墊層)均設置於大致上垂直對應之位置，分別以介電層80或90與其他層相隔，亦利用單一垂直之導通孔，以一貫之。再以蝕刻法或是增層法形成第3圖中所示之導通孔金屬60使金屬層10、20電性連接。惟其疊構導孔之導孔壁均為具有一定角度之斜孔壁。然而此結構金屬層20、60(做為孔墊)面積較大，因此必然導致佈線密度較低。
請參考第4圖，係顯示習知交錯式導通孔(Staggered VIA)技術形成多層埋孔之多層導通孔疊構。如第4圖所示之多層導通孔疊構係先將導通孔金屬60形成於金屬層10上，同時亦於介電層80表面向金屬層10之外延伸出具有一定面積之一特定區域。接著，於形成介電層90並對其在前述特定區域開孔後，於前述特定區域上再形成導通孔金屬70，並且如第4圖中所示，導通孔金屬70之導通孔金屬邊緣垂直線99同樣地會落於前述特定區域上，亦即一般做法會使導通孔金屬70盡量不與導通孔金屬60的前述特定區域以外之部份重疊。此類結構係為目前最為普遍、用途最廣之多層導通孔疊構。惟其不若第3圖所示之堆疊式導通孔技術能讓積體電路以及多層基板尺寸縮小之幅度可觀。因此在提高積體電路及多層基板之繞線密度(routing density)方面勢將有先天存在之限制。特別是如前述當今面對軟性積體電路及軟性多層基板更進一步、更嚴苛之要求下恐更加力有未逮。然其相較於堆疊式導通孔技術，較具有可撓性。
是以，確有發展一多層導通孔疊構，以解決前述習知技術之缺點，進一步突破限制，在提高積體電路及多層基板之繞線密度的同時，亦能使其更具有可繞性，更為符合軟性積體電路及軟性多層基板之需要。
本發明之目的在於提供一種多層導通孔疊構，更薄、佈線密度更高、更具可撓性，因而能應用於軟性半導體或軟性多層基板之多層導通孔疊構。並且，本發明多層導通孔疊構之高佈線密度特性亦適用於一般封裝基板或印刷電路板。
本發明之多層導通孔疊構包含一金屬層、一第一介電層、一第一導通孔金屬層、一第二介電層以及一第二導通孔金屬層。第一介電層披覆金屬層，且於金屬層上方具有第一開口。第一導通孔金屬層形成於第一開口及第一介電層上，具有第一底部、位於第一介電層上之第一上端部以及第一斜孔壁。第一斜孔壁具有與第一上端部接合之第一頂端及與第一底部接合之第一底端。並且，第一底部具有一幾何中心。第二介電層披覆第一導通孔金屬層，且於第一導通孔金屬層之第一上端部及第一斜孔壁上方具有第二開口。第二導通孔金屬層形成於第二開口及第二介電層上，具有第二底部、位於第二介電層上之第二上端部以及第二斜孔壁。第二斜孔壁具有與第二上端部接合之第二頂端及與第二底部接合之第二底端。第二頂端最接近第一底部具有之幾何中心之一點所具有相對金屬層之垂直線係落於第一斜孔壁上。或者，第二底端最接近第一底部具有之幾何中心之一點所具有相對金屬層之垂直線係落於第一斜孔壁上。
請參考第5圖，係顯示本發明第一實施例之多層導通孔疊構。本發明第一實施例之多層導通孔疊構包含一金屬層100、一第一介電層202、一第一導通孔金屬層102、一第二介電層204以及一第二導通孔金屬層104。如第5圖中所示，金屬層100係作為軟性半導體電路或軟性多層基板之金屬線路或焊墊層。第一介電層202披覆金屬層100，且於金屬層100上方具有第一開口。第一導通孔金屬層102形成於第一開口及第一介電層202上。第一導通孔金屬層102具有第一底部102-1、第一上端部102-2及第一斜孔壁102-3。如圖所示，第一底部102-1形成於第一開口的位置且具有一幾何中心，其可為一對稱線或著一圓心，視第一底部102-1之形狀決定。第一上端部102-2則形成於第一介電層202上。第一斜孔壁102-3具有第一頂端及第一底端。第一頂端與第一上端部102-2接合，其第一底端則與第一底部102-1接合。第二介電層204披覆第一導通孔金屬層102，且如圖所示，於第一導通孔金屬層102之第一上端部102-2上方具有第二開口。第二導通孔金屬層104形成於第二開口及第二介電層204上。第二導通孔金屬層104具有第二底部104-1、第二上端部104-2及第二斜孔壁104-3。第二底部104-1形成於第二開口的位置。第二上端部104-2則形成於第二介電層204上。第二斜孔壁104-3具有第二頂端及第二底端。第二頂端與第二上端部104-2接合。第二底端與第二底部104-1接合。
第一導通孔金屬層102具有之第一上端部102-2預定於後形成第二導通孔金屬層104之位置，係較向外延伸，以準備與第二底部104-1接合。即所謂交錯式多層導通孔疊構。然而與習知技術最大不同處在於，第二導通孔金屬層104之第二頂端最接近第一底部102-1所具有之幾何中心110之一點所具有相對金屬層100之垂直線112係落於第一斜孔壁102-3上。亦即，若從俯視的角度來看，第一導通孔金屬層102與第二導通孔金屬層104有一部分重疊。
請參考第6圖，係顯示本發明第二實施例之多層導通孔疊構。本發明第二實施例與前述本發明之第一實施例結構相似，但第二介電層204具有之第二開口係如圖所示，位於第一導通孔金屬層102之第一上端部102-2及第一斜孔壁102-3上方，會露出部份之第一上端部102-2與部份之第一斜孔壁102-3。因此，第二導通孔金屬層104所具有之第二底部104-1的第二底端最接近第一底部102-1所具有之幾何中心110之一點所具有相對於金屬層100之一垂直線114係落於第一斜孔壁102-3 上，其中第二導通孔金屬層104中的第二底部104-1的一部份係與第一斜孔壁102-3重疊，第二導通孔金屬層104的第二底部104-1係為不平坦結構。亦即，若從俯視的角度來看，第一導通孔金屬層102與第二導通孔金屬層104重疊之部分，相較於第一實施例重疊之部分更多。
請參考第7圖，係顯示本發明比較例之多層導通孔疊構。此比較例與前述本發明之第一實施例、第二實施例相似，惟，相異處在於：第二導通孔金屬層104所具有之第二底部104-1的第二底端最接近金屬層100所具有之幾何中心110之一點所具有相對金屬層100之一垂直線114已落於第一導通孔金屬層102之第一底部102-1上，其中第二導通孔金屬層104中的第二底部104-1的一部分係與第一底部102-1重疊，第二導通孔金屬層104的第二底部104-1係為不平坦結構。亦即，若從俯視的角度來看，此比較例第一導通孔金屬層102與第二導通孔金屬層104重疊之部分，相較於本發明第一實施例、第二實施例重疊之部分已更多，已如第2圖、第3圖所示習知技術之堆疊式導通孔，可撓性已不佳。
比較前述第5圖、第6圖及第7圖所示，本發明之實施例及比較例可知，依據本發明，多層導通孔疊構不僅可保有交錯式導通孔疊構適用於軟性積體電路以及軟性多層基板可撓性之需求，能使積體電路以及多層基板之厚度製作得更薄，同時能更進一步提高積體電路及多層基板之繞線密度。並且，又不會如習知技術之堆疊式導通孔疊構，為單方面追求繞線密度提高，卻因其堆疊特性，大量金屬材料設置於一密集之區域內，致使其幾不具可撓性，而不適用於軟性積體電路以及軟性多層基板。
請參考第8a圖至第8g圖，係顯示本發明第二實施例的多層導通孔疊構之製作方法。
如第8a圖所示，於一軟性積體電路或一軟性多層基板之一介電層200上形成一金屬層100。
如第8b圖所示，於金屬層100上形成一第一介電層202，披覆金屬層100。
如第8c圖所示，於金屬層100上方形成一第一開口。形成第一開口之方式，則能以光學微影定義之製程或光學雷射鑽孔之製程。本發明並未對光學微影定義開口及鑽孔製程作任何限定，僅要對於開口之精確度能夠掌握，如前述光學微影解析度、景深足夠定義開口，光學雷射鑽孔之能量、解析度足夠在不平坦之位置進行精確開口即可。
如第8d圖所示，例如以金屬剝離製程(Metal Lift Off)選用負型光阻為例，在介電層202表面塗佈至少一光阻層203。塗佈光阻層203後，對第一導通孔金屬層102預定位置之光阻層203-1以外的光阻層203進行曝光後，即可以顯影劑(Developer)去除位於預定位置之光阻層203-1。
接著，如第8e圖所示，去除光阻層203及其上方與第一導通孔金屬層102同時形成的金屬層後，即完成第一開口及週遭先決之區域範圍內，形成具有第一底部、第一上端部及第一斜孔壁之第一導通孔金屬層102的製作。但本發明並未對形成第一導通孔金屬層102之方法做任何限定，惟經本發明者進行實際實驗而得出，若欲形成位置精準、形狀精確且厚度均勻之金屬層，以金屬剝離製程為較佳。
如第8f圖所示，形成一第二介電層204，披覆第一導通孔金屬層102。由於第一導通孔金屬層102呈凹陷之形狀外觀， 因此，形成之第二介電層204亦形成相似之凹陷形狀外觀。
如第8g圖所示，於第一導通孔金屬層102之第一上端部及第一斜孔壁上方形成一第二開口。形成第二開口之方式，則能以光學微影定義之製程或光學雷射鑽孔之製程。本發明並未對光學微影定義開口及鑽孔製程作任何限定，僅要對於開口之精確度能夠掌握，如前述光學微影解析度、景深足夠定義開口，光學雷射鑽孔之能量、解析度足夠在不平坦之位置進行精確開口即可。
如第8h圖所示，於第二開口及週遭先決之區域範圍內，形成具有第二底部、第二上端部及第二斜孔壁之第二導通孔金屬層104。則第二導通孔金屬層104之第二底端最接近第一底部102-1所具有之幾何中心之一點所具有相對金屬層100之垂直線114係落於第一斜孔壁上。並且，形成第二導通孔金屬層104之方法則可與前述形成第一導通孔金屬層102相同，可為金屬剝離製程(Metal Lift Off)。但本發明並未對形成第二導通孔金屬層104之方法做任何限定，惟經本發明者進行實際實驗而得出，形成金屬層之各種製程，以金屬剝離製程為較佳。特別是第二開口之底部係如第8g圖所示，非一平整之底面，能於非平整底面，形成位置精準、形狀精確且厚度均勻之第二導通孔金屬層104，應採用金屬剝離製程為較佳。上述雖以製作本發明之第二實施例進行說明，本發明之第一實施例亦能以同樣之方法製作，要注意的是決定第二開口的位置不同。
總言之，根據本發明之多層導通孔疊構，不僅能適用於軟性半導體或軟性多層基板之多層導通孔疊構更薄、更具可撓性之需求，同時能更進一步提高軟性積體電路及軟性多層基板之繞線密度。
綜上所述，雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧金屬層
20‧‧‧金屬層
30‧‧‧金屬層
60‧‧‧導通孔金屬
70‧‧‧導通孔金屬
80‧‧‧介電層
90‧‧‧介電層
99‧‧‧邊緣垂直線
100‧‧‧金屬層
102‧‧‧第一導通孔金屬層
102-1‧‧‧第一底部
102-2‧‧‧第一上端部
102-3‧‧‧第一斜孔壁
104‧‧‧第二導通孔金屬層
104-1‧‧‧第二底部
104-2‧‧‧第二上端部
104-3‧‧‧第二斜孔壁
110‧‧‧第一底部幾何中心
112‧‧‧第二頂端垂直線
114‧‧‧第二底端垂直線
202‧‧‧第一介電層
204‧‧‧第二介電層
204-1‧‧‧待移除之第二介電層
第1圖係顯示習知堆疊式導通孔技術形成多層埋孔之多層導通孔疊構。
第2圖係顯示習知堆疊式導通孔技術形成越層孔(盲孔)之多層導通孔疊構。
第3圖係顯示另一習知技術堆疊式導通孔技術形成越層孔，且具有斜孔壁之多層導通孔疊構。
第4圖係顯示習知技術交錯式導通孔技術形成多層埋孔之多層導通孔疊構。
第5圖係顯示本發明第一實施例之多層導通孔疊構。
第6圖係顯示本發明第二實施例之多層導通孔疊構。
第7圖係顯示本發明比較例之多層導通孔疊構。
第8a圖至第8h圖係顯示本發明第二實施例的多層導通孔疊構之製作方法。
100．．．金屬層
102．．．第一導通孔金屬層
102-1．．．第一底部
102-2．．．第一上端部
102-3．．．第一斜孔壁
104．．．第二導通孔金屬層
104-1．．．第二底部
104-2．．．第二上端部
104-3．．．第二斜孔壁
110．．．第一底部幾何中心
114．．．第二底端垂直線
202．．．第一介電層
204．．．第二介電層

Claims (15)

  1. 一種多層導通孔疊構，包含：一金屬層；一第一介電層，披覆該金屬層，且於該金屬層上方具有一第一開口；一第一導通孔金屬層，形成於該第一開口及該第一介電層上，具有一第一底部、位於該第一介電層上之一第一上端部以及一第一斜孔壁，該第一斜孔壁具有與該第一上端部接合之一第一頂端及與該第一底部接合之一第一底端，且該第一底部具有一幾何中心；一第二介電層，披覆該第一導通孔金屬層，且於該第一導通孔金屬層之該第一上端部及該第一斜孔壁上方具有一第二開口；以及一第二導通孔金屬層，形成於該第二開口及該第二介電層上，具有一第二底部、位於該第二介電層上之一第二上端部以及一第二斜孔壁，該第二斜孔壁具有與該第二上端部接合之一第二頂端及與該第二底部接合之一第二底端，其中該第二底端最接近該幾何中心之一點所具有相對該金屬層之一垂直線係落於該第一底部上，其中該第二導通孔金屬層中的第二底部的一部分係與該第一底部重疊，其中該第二導通孔金屬層的第二底部係為不平坦結構。
  2. 如申請專利範圍第1項所述之多層導通孔疊構，其中該第二開口係以光學微影定義。
  3. 如申請專利範圍第1項所述之多層導通孔疊構，其中該第二開口係以光學雷射鑽孔形成。
  4. 如申請專利範圍第1項所述之多層導通孔疊構，其中該 第一導通孔金屬層係以金屬剝離製程，同時形成該第一底部、該第一上端部以及該第一斜孔壁。
  5. 如申請專利範圍第1項所述之多層導通孔疊構，其中該第一開口係以光學微影定義。
  6. 如申請專利範圍第1項所述之多層導通孔疊構，其中該第一開口係以光學雷射鑽孔形成。
  7. 如申請專利範圍第1項所述之多層導通孔疊構，其中該多層導通孔疊構係應用於一軟性多層基板或一軟性半導體電路。
  8. 一種多層導通孔疊構，包含：一金屬層；一第一介電層，披覆該金屬層，且於該金屬層上方具有一第一開口；一第一導通孔金屬層，形成於該第一開口及該第一介電層上，具有一第一底部、位於該第一介電層上之一第一上端部以及一第一斜孔壁，該第一斜孔壁具有與該第一上端部接合之一第一頂端及與該第一底部接合之一第一底端，且該第一底部具有一幾何中心；一第二介電層，披覆該第一導通孔金屬層，且於該第一導通孔金屬層之該第一上端部及該第一斜孔壁上方具有一第二開口；以及一第二導通孔金屬層，形成於該第二開口及該第二介電層上，具有一第二底部、位於該第二介電層上之一第二上端部以及一第二斜孔壁，該第二斜孔壁具有與該第二上端部接合之一第二頂端及與該第二底部接合之一第二底端，其中該第二底端 最接近該幾何中心之一點所具有相對該金屬層之一垂直線係落於該第一斜孔壁上，其中該第二導通孔金屬層中的第二底部的一部份係與該第一斜孔壁重疊，其中該第二導通孔金屬層的第二底部係為不平坦結構。
  9. 如申請專利範圍第8項所述之多層導通孔疊構，其中該第二導通孔金屬層係以係以金屬剝離製程，同時形成該第二底部、該第二上端部以及該第二斜孔壁。
  10. 如申請專利範圍第8項所述之多層導通孔疊構，其中該第二開口係以光學微影定義。
  11. 如申請專利範圍第8項所述之多層導通孔疊構，其中該第二開口係以光學雷射鑽孔形成。
  12. 如申請專利範圍第8項所述之多層導通孔疊構，其中該第一導通孔金屬層係以金屬剝離製程，同時形成該第一底部、該第一上端部以及該第一斜孔壁。
  13. 如申請專利範圍第8項所述之多層導通孔疊構，其中該第一開口係以光學微影定義。
  14. 如申請專利範圍第8項所述之多層導通孔疊構，其中該第一開口係以光學雷射鑽孔形成。
  15. 如申請專利範圍第8項所述之多層導通孔疊構，其中該多層導通孔疊構係應用於一軟性多層基板或一軟性半導體電路。
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TWI424544B (zh) * 2011-03-31 2014-01-21 Novatek Microelectronics Corp 積體電路裝置
US8722530B2 (en) 2011-07-28 2014-05-13 Freescale Semiconductor, Inc. Method of making a die with recessed aluminum die pads
US10149390B2 (en) 2012-08-27 2018-12-04 Mycronic AB Maskless writing of a workpiece using a plurality of exposures having different focal planes using multiple DMDs
US10123465B2 (en) * 2015-04-15 2018-11-06 Ford Global Technologies, Llc Power-module assembly
TWI692281B (zh) * 2019-03-13 2020-04-21 中華精測科技股份有限公司 多層電路板及其製造方法
JP2022531153A (ja) * 2019-05-01 2022-07-06 アイオー テック グループ リミテッド ３ｄ印刷を用いてチップをトップコネクタと電気接続する方法

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JP2006216714A (ja) 2005-02-02 2006-08-17 Ibiden Co Ltd 多層プリント配線板
JP2007173371A (ja) 2005-12-20 2007-07-05 Shinko Electric Ind Co Ltd フレキシブル配線基板の製造方法及び電子部品実装構造体の製造方法
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