WO2010060286A1 - 多层基板的导孔结构及其制造方法 - Google Patents

多层基板的导孔结构及其制造方法 Download PDF

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Publication number
WO2010060286A1
WO2010060286A1 PCT/CN2009/070976 CN2009070976W WO2010060286A1 WO 2010060286 A1 WO2010060286 A1 WO 2010060286A1 CN 2009070976 W CN2009070976 W CN 2009070976W WO 2010060286 A1 WO2010060286 A1 WO 2010060286A1
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Prior art keywords
metal layer
layer
hole
multilayer substrate
metal
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PCT/CN2009/070976
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English (en)
French (fr)
Inventor
杨之光
Original Assignee
巨擘科技股份有限公司
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Application filed by 巨擘科技股份有限公司 filed Critical 巨擘科技股份有限公司
Priority to EP09828547.1A priority Critical patent/EP2360999B1/en
Priority to KR1020117011868A priority patent/KR101209553B1/ko
Publication of WO2010060286A1 publication Critical patent/WO2010060286A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09645—Patterning on via walls; Plural lands around one hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern

Definitions

  • the present invention relates to a via structure of a multilayer substrate and a method of fabricating the same, and more particularly to a via structure of a flexible multilayer substrate and a method of fabricating the same.
  • the miniaturization of any type of electronic product today is an inevitable trend.
  • the related technologies of the back-end packaging must also move toward miniaturization. Therefore, the integration of integrated circuits has been continuously improved, and the use of multilayer substrates for the production of package substrates, printed circuit boards, flexible package substrates, and flexible circuit boards has become an inevitable integration of high-density systems.
  • Trends, especially with flexible multilayer substrates are more effective in a wide range of products and meet the needs of miniaturization.
  • the multilayer substrate metal wiring or via structure is mostly fabricated by etching (Etch) or semi-additive.
  • Etch etching
  • the industry generally refers to Fine-pitch products that refer to products with high bulk density.
  • FIG. 1 is a schematic view showing a prior art fabrication of a via structure.
  • Fig. 1 is a view showing only a portion of a general multilayer substrate relating to a via structure.
  • the multilayer substrate has, for example, a metal layer 102 as a lower layer, a dielectric layer 104 over the metal layer 102, and a via 106 formed by laser or mechanical drilling.
  • the pilot holes 106 each have a vertical bore wall.
  • the metal layer 108 is used as a hole pad, and the main purpose is to electrically connect the metal layer 102 and other metal layers above the dielectric layer 104.
  • the metal layer 108 of the joint 110 of the dielectric layer 104 and the metal filler is connected in FIG. 1, or the metal layer 102 is connected to the metal filler. At 112, it is easy to crack.
  • the via structure of the multilayer substrate is an important part of the electrical connection between the different layers, when such a via structure is formed in the bent region of the flexible multilayer substrate, it must be frequently folded in the use of the product.
  • the metal layer 108 corresponding to the junction 110 of the dielectric layer 104 and the filler or the junction 112 of the metal layer 102 and the filler is more likely to be peeled.
  • the hole pad size A (VIA Land Size) of such a via structure must be larger than the via size B (VIA Diameter), resulting in a limited size of the via pitch (pin pitch) of the multilayer substrate and the metal line pitch, and Cannot be applied to high-density density
  • FIG. 2 is a schematic diagram showing another via structure in the prior art.
  • the multilayer substrate has, for example, a metal layer 202 as a lower layer, a dielectric layer 204 overlying the metal layer 202, and a dielectric layer 204 having vias 206. After the via holes 206 are formed, the via pads are formed, and the main purpose is to electrically connect the metal layer 202 and other metal layers above the dielectric layer 204.
  • the multilayer substrate is bent, the possibility that the joint 212 of the metal layer 202 and the hole pad is peeled off in FIG.
  • the via structure is formed by etching or semi-additive, and the process error needs to be considered (detailed later). Therefore, the hole pad size A (VIA Land size) of such a via structure must still be larger than the via hole size B (VIA diameter), resulting in a limited hole pitch (pin pitch) of the multilayer substrate and a limited size of the metal line pitch. It is no longer able to further meet the demand for today's high structural density.
  • FIG. 3A and FIG. 3B are schematic diagrams showing the structure of the guide hole formed by the prior art etching method.
  • the metal layer 302 is formed first, and then the dielectric layer 304 is formed over the metal layer 302.
  • a metal layer 308 which is later formed by etching to form the via pad 300 (VIALand) is filled into the via hole 306 while also covering the dielectric layer 304.
  • a photoresist layer 310 is applied to the position where the hole pad is to be formed.
  • the metal layer 308 not covered by the photoresist layer 310 is removed by etching.
  • the etching method not only removes the metal layer 308 not covered by the photoresist layer 310, but also etches the side surface of the hole pad, for example: as shown in FIG. 3A, etching to the dotted line The position indicated by 314, therefore, will eventually result in an undercut structure for the aperture pad as shown in Figure 3B. Therefore, in the fabrication process of the multilayer substrate, if the via structure of the multilayer substrate is formed by etching, the size of the photoresist layer 310 cannot accurately determine the VIA Land size, which leads to the hole pad size required for the circuit design. Considering this etching process error, the size of the hole pad cannot be further reduced. When the size requirements of the metal line or via structure are increasingly fine, the etching method has its limitations.
  • FIGS. 4A to 4C are schematic views showing a structure of a via hole formed by a conventional semi-additive process (SAP).
  • SAP semi-additive process
  • the metal layer 402 is formed first, and then the dielectric layer 404 is formed over the metal layer 402.
  • a via hole 406 is formed.
  • a seed metal 407 is formed first, and then a photoresist layer 410 is applied at a position other than the hole pad 400 (VIA Land) to be formed later, and a metal layer is plated to fill the hole pad ( VIA Land) location.
  • the photoresist layer 410 is removed as shown in FIG. 4B, the seed metal 407 other than the hole pad 400 (VIA Land) position is removed by etching to complete the fabrication of the via structure.
  • the hole pad 400 (the VIA LandM stands outside the seed metal 407, it will also be as shown As shown in FIG. 4B, the hole pad 400 (VIALand) is etched to the position indicated by the broken line 414. Therefore, as shown in FIG. 4C, a hole pad 400 (VIA Land) having a smaller size than that defined by the original photoresist layer 410 is formed. Therefore, in the fabrication process of the multilayer substrate, if the via structure is formed by the semi-additive method, it has the same disadvantages as the etching method described above, and the size of the photoresist layer 410 cannot accurately determine the VIA Land size, resulting in circuit design.
  • the size of the hole pad needs to consider the process error, the size of the hole pad cannot be further reduced.
  • the semi-additive method also has limitations, and can not further satisfy the current situation. The need for density of construction.
  • the via fill region (VIALand) is located in the via hole, which can reduce the possibility of the aforementioned stripping, and does not need to be in the circuit design of the foregoing process.
  • the size of the multilayer substrate can be further reduced, thereby increasing the density of the package, and can also be applied to the flexible multilayer substrate to increase the reliability of the package substrate.
  • the main object of the present invention is to provide a via structure for a multilayer substrate and a method for fabricating the same, which are applied to the fields of packaging substrates, printed circuit boards, flexible package substrates, and flexible circuit boards, and the pad (VIA Land) It is located in the via hole, so the size of the via hole (pin pitch) and the metal line pitch can be reduced, and the substrate mounting density is increased.
  • Another object of the present invention is to provide a via structure of a multilayer substrate and a method of fabricating the same, which can be applied to a flexible, bendable multilayer substrate and a flexible circuit board, and can increase the multilayer substrate. Reliability.
  • a via structure of a multilayer substrate includes a first metal layer, a dielectric layer, and a second metal layer.
  • the first metal layer has an upper surface.
  • the dielectric layer is coated on the first metal layer, and a via hole is formed at a position corresponding to the upper surface of the first metal layer.
  • the via hole has a slanted hole wall, and the slant hole wall has an upper end edge.
  • the second metal layer is formed in the via hole as a hole pad, and is joined to the upper surface and the inclined hole wall, and the formed joint surface has an upper edge, and the joint surface edge is lower than the upper end edge of the inclined hole wall.
  • a second metal layer can be simultaneously formed on the dielectric layer as a metal wire and bonded to the via pad to form an electrical connection.
  • the foregoing second metal layer is a metal stripping process (Metal
  • Lift-Off is formed in the aforementioned via hole and on the dielectric layer.
  • a method for manufacturing a via structure of a multilayer substrate comprising the following steps:
  • a via hole is formed on the dielectric layer and corresponding to the upper surface of the first metal layer, the via hole has a slant hole wall having an upper end edge;
  • the via structure and the manufacturing method thereof of the present invention can be applied not only to a package substrate but also to a technical field of manufacturing a flexible circuit board or a flexible package substrate.
  • the hole pad of the via structure of the multilayer substrate of the present invention is located in the via hole, there is no need to accurately determine the size of the hole pad due to the size of the photoresist layer as in the prior art, resulting in circuit design.
  • the hole pad size needs to consider this process error, but needs to be larger than the guide hole size. Therefore, compared with the prior art, the via pitch (pin pitch) and the metal pitch of the multilayer substrate can be further reduced, and the mounting density of the multi-layer substrate can be improved.
  • the hole pad is formed in the via hole by the metal stripping process, so that the hole pad has good adhesion to the first metal layer and the inclined hole wall of the dielectric layer.
  • the hole pad has a relatively smooth joint between the first metal layer and the inclined hole wall of the dielectric layer, and can be bent when the multilayer substrate is bent.
  • the structure has good ductility.
  • the guiding hole structure of the invention maintains the original guiding hole structure intact after multiple bending, does not cause peeling, and maintains good electrical connection between the first metal layer and the hole pad, and improves the reliability of the multilayer substrate. degree. [Description of the Drawings]
  • Figure 1 is a schematic view showing a prior art via structure.
  • Fig. 2 is a schematic view showing another guide hole structure of the prior art.
  • 3A and 3B are schematic views showing the structure of a via hole formed by a conventional etching method.
  • 4A to 4C are schematic views showing a structure of a via hole formed by a prior art semi-additive process.
  • Fig. 5 is an explanatory view showing a first embodiment of a via structure of the multilayer substrate of the present invention.
  • Fig. 6 is an explanatory view showing a second embodiment of a via structure of the multilayer substrate of the present invention.
  • Fig. 7 is a plan view showing a structure of a via hole of a multilayer substrate in accordance with a second embodiment of the present invention.
  • FIG. 5 is a view showing the first embodiment of the via structure of the multilayer substrate of the present invention. Ming map. In FIG. 5, only the portion of the via structure of the multilayer substrate of the present invention is shown.
  • the via structure of the multilayer substrate of the present invention includes: a first metal layer 502, a dielectric layer 506, and a second metal. Layer, the structure of each layer is as follows:
  • the first metal layer 502 has an upper surface 504.
  • Dielectric layer 506 is overlying first metal layer 502.
  • a via hole 508 is defined in the dielectric layer 506 at a position of the upper surface 504.
  • the via hole 508 has a slanted hole wall 510 having an upper end edge 510-2.
  • a second metal layer is formed in the via 508 as a hole pad 512.
  • the hole pad 512 is joined to the upper surface 504 and the inclined hole wall 510, and the formed joint surface has an upper edge 530. Further, the upper edge 530 of the joint surface of the hole pad 512 and the inclined hole wall 510 is lower than the upper end edge 510-2 of the inclined hole wall 510. Also, the hole pad 512 is also smaller in size and located inside the upper end edge 510-2 of the dielectric layer 506.
  • the material of the first metal layer 502 and the hole pad 512 may be copper.
  • the material of the dielectric layer 506 is preferably a polyimide (PI), which may be formed by coating on the first metal layer 502.
  • the second metal layer 512 is formed in the via hole 508 by a metal lift-off process (described later in detail). Since the via pad 512 (VIA Land) of the via structure of the multilayer substrate of the present invention is located in the via hole 508, it is not necessary to accurately determine the VIA Land size due to the size of the photoresist layer as in the prior art. When designing the circuit, the VIALand size needs to take into account this process error, which is greater than the VIA diameter. Therefore, compared with the prior art, the via pitch (pin pitch) and the metal pitch of the multilayer substrate can be further reduced, and the mounting density of the multilayer substrate can be improved.
  • the hole pad 512 is formed in the via hole 508 by a metal lift-off process, so that the hole pad 512 has good adhesion to the first metal layer 502 and the oblique hole wall 510 of the dielectric layer 506. Sex. Furthermore, in order to make the via structure of the multilayer substrate of the present invention, the hole pad 512 has a relatively smooth joint between the first metal layer 502 and the inclined hole wall 510 of the dielectric layer 506, and can be bent on the multilayer substrate. When the guide hole structure has good ductility.
  • the sharp angle ⁇ formed between the upper surface 504 of the first metal layer 502 and the inclined hole wall 510, that is, the lower end edge 510-4 of the inclined hole wall 510 is preferably less than 75 °. Therefore, it is applied even to a flexible, flexible flexible circuit board or a bent area of a package substrate.
  • the via structure of the present invention maintains the original via structure intact after multiple bending, and does not cause cracking, and maintains a good electrical connection between the first metal layer 502 and the hole pad 512, and improves the multilayer substrate. Reliability.
  • a method for fabricating a via structure of a multilayer substrate using the Metal Lift-Off method of the present invention is as follows:
  • a conductive hole 508 is defined in the upper surface 504 of the first metal layer 502, the conductive hole 508 has a slanted hole wall 510;
  • the photoresist layer 520 (not shown) is disposed in the via 508.
  • a negative photoresist is used, and the photoresist layer 520 is removed by using a developer. As shown in FIG. 5, the photoresist layer 520 is removed.
  • the area of the opening of the upper end edge 532 can be controlled to be smaller than the area of the upper end edge 510-2 of the inclined hole wall 510 and larger than the area of the lower end edge 510-4;
  • a second metal layer 512a is formed on the photoresist layer 520 forming the hole pad 512 and the surface of the dielectric layer 506 in the via hole 508, and the hole pad 512 formed in the via hole 508, and the upper surface 504 and the inclined hole wall 510 are formed.
  • the photoresist layer 520 on the surface of the dielectric layer 506 and the second metal layer 512a formed on the photoresist layer 520 are removed.
  • the via structure of the multilayer substrate of the present invention is completed.
  • the second metal layer formed in the via 508 is used as a hole pad 512.
  • the photoresist layer 520 at a predetermined position on the dielectric layer 506 can be simultaneously removed.
  • the second metal layer formed at the predetermined position is As a metal wire 514, it is joined to the hole pad 512 to form an electrical connection.
  • the photoresist layer 520 is mostly defined by a lithography process, and the upper edge 532 of the photoresist layer opening is transferred by a lithography process with a highly accurate lithography process. And formed. Therefore, the greatest advantage of the present invention over the prior art is that the shape and area of the aperture pad 512 is defined by the upper end edge 532 of the aperture of the photoresist layer 520 located on the surface of the dielectric layer 506, very close to the size of the mask. , that is, the ideal size of the original circuit design. That is, the prior art etching method and the semi-additive method are not used, resulting in the inability to accurately define the VIA Land size by the photoresist layer.
  • the present invention satisfies further requirements in the present and future in which the dimensional accuracy of metal wiring or via structures is increasingly stringent.
  • the VIA depth will be approximately 40 um
  • the VIA diameter will be approximately 40-60 ⁇ m
  • the hole pad size (VIA Land) The size) is about 70 m.
  • the minimum VIA depth is only about 3 ⁇ m
  • the VIA diameter is only about 5 ⁇ m
  • the VIA Land size limit is only about 7 ⁇ m. .
  • Fig. 6 is an explanatory view showing a second embodiment of a via structure of the multilayer substrate of the present invention.
  • Fig. 7 is a plan view showing a structure of a via hole of a multilayer substrate in accordance with a second embodiment of the present invention. In FIG. 6, only the portion of the via structure of the multilayer substrate of the present invention is shown.
  • the via structure of the multilayer substrate of the present invention includes: a first metal layer 502, a dielectric layer 506, and a second Metal layer. Details are as follows:
  • the first metal layer 502 has an upper surface 504.
  • Dielectric layer 506 is overlying first metal layer 502.
  • a via hole 508 is formed in the dielectric layer 506 at a position of the upper surface 504, and the via hole 508 has a slant hole wall 510.
  • a second metal layer is formed in the via hole 508 as a hole pad 512, and as a metal wire 514 on the dielectric layer 506, the hole pad 512 is joined to the upper surface 504 and the inclined hole wall 510, and the joint surface is formed.
  • the joint surface edge 530 is lower than the upper end edge 510-2 of the slanted hole wall 510, i.e., the hole pad 512 is smaller in size and located inside the upper edge 510-2 of the dielectric layer 506.
  • the dielectric layer 506 can also be removed, for example: A photoresist layer 520 in a predetermined position of the metal wire 514 (for example, a linear groove, not shown) is defined.
  • a second metal layer is formed in the via hole 508 and at a predetermined position as the hole pad 512 and the metal line 514, respectively.
  • different metal steps may be formed in the via 508 and at predetermined locations, respectively, as the via pads 512 and the metal lines 514, but still connected to each other to achieve electrical connection between the different layers.
  • the hole pad 512 has a relatively smooth joint between the first metal layer 502 and the slanted hole wall 510 of the dielectric layer 506, and the connection between the hole pad 512 and the metal line 514 is also smooth, and, in addition, the metal The line 514 is also rounded at the upper end edge 510-2 of the via hole, and has good ductility when the multilayer substrate is bent.
  • the sharp angle ⁇ formed between the upper surface 504 of the first metal layer 502 and the inclined hole wall 510, that is, the lower end edge 510-4 of the inclined hole wall 510 is preferably less than 75 °. .
  • a dotted line 516 is defined as a boundary between the hole pad 512 and the metal line 514.
  • the via pad 512 (VIA Land) is located in the via hole 508 (VIA), that is, smaller than the upper end edge 510-2 of the via hole 508, and larger than the lower end edge 510-4. Therefore, the VIA Land size of the present invention can be smaller than the VIA diameter, and it is not necessary to consider the error of the hole pad size in the prior art process design. At the same time, it has good bonding with the metal line 514, which can reduce the possibility of prior art guide hole structure peeling. Therefore, the size of the multilayer substrate can be further reduced, and the mounting density of the multilayer substrate can be increased. It can be applied to a wide range of flexible circuit boards and flexible package substrates, which can increase the reliability of the substrate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

多层基板的导孔结构及其制造方法
【技术领域】
本发明是有关于一种多层基板的导孔结构及其制造方法， 特别是关于一 种软性多层基板的导孔结构及其制造方法。
【背景技术】
现今任何类型电子产品的小型化是无可避免的趋势， 随着半导体晶圆制 程尺寸不断地缩小， 后段封装的相关技术也必须随之朝微型化的方向进歩。 因此， 当今集成电路的积集度已不断地提高， 其中使用多层基板用于制作封 装基板、 印刷电路板、 软性封装基板及软性电路板等领域， 整合成高密度系 统已为必然的趋势， 特别是利用软性多层基板， 更能有效地应用于各类产品， 符合微型化的需求。 而依据业界的现行作法， 多以蚀刻法 (Etch)或半加成法 (semi-additive)进行多层基板金属线路或导孔结构的制作。 多层基板的电路积 集度越高，金属线路或导孔结构的尺寸要求便越精细。一般业界所称 Fine-pitch 类产品即涉指具有高构装密度的产品。
请参考图 1所示， 图 1是表示现有技术制作导孔结构的示意图。 图 1是仅显 示一般多层基板有关导孔结构的部份。 多层基板具有例如作为下层线路的金 属层 102， 覆盖于金属层 102上的介电层 104， 以雷射或机械钻孔的方式所形成 的导孔 106。 此导孔 106均具有垂直的孔壁。在形成导孔 106后， 填入金属填充 物后， 与金属层 108作为孔垫， 主要目的是用以电性连接金属层 102以及介电 层 104上方的其它金属层。 当多层基板采用此类导孔结构并进行弯折应用时， 在图 1中对应介电层 104与金属填充物的连接处 110的金属层 108， 或是金属层 102与金属填充物的连接处 112均很容易发生剥裂。
因多层基板的导孔结构为不同层间电性连接的重要部分， 当在软性多层 基板的折曲区域中制作此类导孔结构时， 特别是在产品使用中必须经常性地 折曲时， 图 1中对应介电层 104与填充物的连接处 110的金属层 108或是金属层 102与填充物的连接处 112发生剥裂的可能性便更高。 并且此类导孔结构的孔 垫尺寸 A (VIA Land Size)须大于导孔尺寸 B (VIA Diameter), 导致多层基板的 导孔距 (接脚距)及金属线距的尺寸缩小有限， 而无法应用于高构装密度的产
P
PR o
请参考图 2所示， 图 2是表示现有技术另一导孔结构的示意图。 如前所述 多层基板具有例如： 作为下层线路的金属层 202， 覆盖于金属层 202上的介电 层 204， 介电层 204具有导孔 206。 在形成导孔 206后， 形成孔垫， 主要目的是 用以电性连接金属层 202以及介电层 204上方的其它金属层。 当多层基板进行 弯折应用时， 图 2中金属层 202与孔垫的连接处 212发生剥裂的可能性高， 尤其 是当导孔深度 C (VIA depth)更进一步加深时， 连接处 212剥裂的可能性便与图 1中连接处 112剥裂的可能性相异无几。 并且， 现今现有技术均以蚀刻法或半 加成法制作导孔结构， 需要考量制程误差 (于后详述)。 因此， 此类导孔结构的 孔垫尺寸 A (VIA Land size)仍须大于导孔尺寸 B (VIA diameter) , 导致多层 基板的导孔距 (接脚距)及金属线距的尺寸縮小有限，也已无法进一步满足现今 高构装密度的需求。
请同时参考图 3A及图 3B所示， 图 3A与图 3B是表示现有技术蚀刻法制作 导孔结构的示意图。 当以蚀刻法制作导孔结构时， 要先形成金属层 302， 再形 成介电层 304覆盖于金属层 302的上方。 接着， 形成一导孔 306后， 再形成稍后 欲以蚀刻法制作孔垫 300 (VIALand)的金属层 308填入导孔 306， 同时也覆盖于 介电层 304上。 之后， 再涂布一光阻层 310于欲制作孔垫的位置。 当涂布光阻 层 310后， 便以蚀刻法移除未被光阻层 310披覆的金属层 308。
由于蚀刻等向性的缘故，蚀刻法不仅会移除未被光阻层 310披覆的金属层 308, 更会对孔垫的侧表面也产生蚀刻， 例如： 如图 3A所示， 蚀刻至虚线 314 所指的位置， 因此， 最后将如图 3B所示，造成对孔垫产生底切 (undercut)结构。 因此多层基板制作过程中， 若以蚀刻法制作多层基板的导孔结构， 则光阻层 310的尺寸无法精确地决定孔垫尺寸 (VIA Land size) , 导致线路设计时， 孔垫 尺寸需要考量此蚀刻制程误差， 使孔垫尺寸无法进一步缩小， 当金属线路或 导孔结构的尺寸要求日益精细， 蚀刻法实有其限制存在。
请同时参考图 4A至图 4C所示， 图 4A至图 4C是表示现有技术半加成法 (SAP, semi-additive process)制作导孔结构的示意图。当以半加成法制作导孔结 构时，要先形成金属层 402,再形成介电层 404覆盖于金属层 402的上方。接着， 制作一导孔 406。 之后， 先形成一层晶种金属 407(seed metal), 接着在稍后欲 形成孔垫 400 (VIA Land)以外的位置涂布一光阻层 410后， 镀上一金属层填满 孔垫 (VIA Land)的位置。 如图 4B所示去除光阻层 410后， 接着以蚀刻的方式， 移除孔垫 400 (VIA Land)位置以外的晶种金属 407， 完成导孔结构的制作。
在前述移除孔垫 400 (VIA LandM立置以外晶种金属 407的同时， 也会如图 4B所示， 蚀刻孔垫 400 (VIALand)至虚线 414所指的位置。 因此， 将如图 4C所 示， 形成较原先光阻层 410所定义的尺寸较小的孔垫 400 (VIA Land)。 因此多 层基板制作过程中， 若以半加成法制作导孔结构， 具有与前述蚀刻法同样的 缺点， 光阻层 410的尺寸无法精确地决定孔垫尺寸 (VIA Land size), 导致线路 设计时， 孔垫尺寸需要考量此制程误差， 使孔垫尺寸无法进一步缩小， 在金 属线路或导孔结构的尺寸精细度日益严格的要求下， 半加成法也有其限制， 也无法进一步满足现今对构装密度的需求。
因此， 若能发展一种多层基板的导孔结构及其制造方法， 导孔填充区域 (VIALand)是位于导孔内， 能降低前述剥裂的可能性，且无须在前述制程的线 路设计时， 考量孔垫尺寸的误差而能进一步缩小多层基板尺寸， 从而使构装 密度增加， 也能应用于软性多层基板， 增加封装基板的可靠度。
【发明内容】
本发明的主要目的在于提供一种多层基板的导孔结构及其制造方法， 应 用于制作封装基板、 印刷电路板、 软式封装基板及软性电路板等领域， 其孔 垫 (VIA Land)是位于导孔内， 因此能缩小导孔距 (接脚距)及金属线距的尺寸， 使基板构装密度增加。
本发明的另一目的在于提供一种多层基板的导孔结构及其制造方法， 能 应用于软性、 可绕曲多层基板及软性电路板的折曲区域， 能增加多层基板的 可靠度。
为达成上述目的， 本发明采用如下技术方案： 一种多层基板的导孔结构 包括一第一金属层、 一介电层、 一第二金属层。 第一金属层具有一上表面。 介电层披覆于第一金属层上， 并在对应于第一金属层上表面的位置开设一导 孔， 该导孔具有一斜孔壁， 斜孔壁具有上端缘。 第二金属层形成于导孔内作 为一孔垫， 与上表面及斜孔壁接合， 形成的接合面具有上缘， 接合面上缘低 于斜孔壁的上端缘。 或者， 可同时形成第二金属层于介电层上作为一金属导 线并与该孔垫接合形成一电性连接。前述第二金属层是以金属剥离制程 (Metal
Lift-Off)形成于前述导孔内及介电层上。
为达成上述目的， 本发明还采用如下技术方案： 一种多层基板的导孔结 构的制造方法， 包含下列歩骤：
形成一第一金属层， 具有一上表面；
形成一介电层， 披覆于该第一金属层上； 在该介电层上并对应于该第一金属层的该上表面的位置开设一导孔， 使 该导孔具有一斜孔壁， 该斜孔壁具有上端缘；
对该介电层表面及该第一金属层的该上表面涂布至少一光阻层； 对该光阻层进行曝光；
去除位于该导孔内的该光阻层；
在该导孔内及该介电层表面的该光阻层上形成一第二金属层， 使形成于 该导孔内的该第二金属层， 与该上表面及该斜孔壁接合； 以及
移除该介电层表面的该光阻层及该光阻层上形成的该第二金属层。
值得一提的是， 本发明的导孔结构及其制造方法不仅能用于封装基板， 更可应用于制作印刷电路板软性电路板或软性封装基板的技术领域。
相较于现有技术， 由于本发明多层基板的导孔结构的孔垫是位于导孔内， 无需如现有技术， 因光阻层的尺寸无法精确地决定孔垫尺寸， 导致线路设计 时， 孔垫尺寸需要考量此制程误差， 而需大于导孔尺寸。 因此相较于现有技 术， 能更进一步使多层基板的导孔距 (接脚距)及金属线距的尺寸縮小，提高多 层基板的构装密度。 并且， 依据本发明以金属剥离制程形成孔垫于导孔内， 使得孔垫对第一金属层以及介电层的斜孔壁均有良好的附着性。 再者， 为使 本发明多层基板的导孔结构中， 孔垫对第一金属层及介电层的斜孔壁间具有 较圆滑的接合， 而能在多层基板折曲时， 导孔结构具有良好的延展性。 本发 明的导孔结构在多次折曲后依然维持原有的导孔结构完整， 不会发生剥裂， 依然维持第一金属层、 孔垫间的良好电性连接， 提高多层基板的可靠度。 【附图说明】
图 1是表示现有技术一导孔结构的示意图。
图 2是表示现有技术另一导孔结构的示意图。
图 3A及图 3B是表示现有技术蚀刻法制作导孔结构的示意图。
图 4A至图 4C是表示现有技术半加成法 (semi-additive process)制作导孔结 构的示意图。
图 5是表示本发明多层基板的导孔结构第一实施例的说明图。
图 6是表示本发明多层基板的导孔结构第二实施例的说明图。
图 7是表示本发明第二实施例的多层基板的导孔结构的俯视图。
【具体实施方式】
请参考图 5所示， 图 5是表示本发明多层基板的导孔结构第一实施例的说 明图。 在图 5中， 仅显示出有关本发明多层基板的导孔结构的部分， 本发明多 层基板的导孔结构包括有： 一第一金属层 502、一介电层 506及一第二金属层， 各层结构详述如下：
第一金属层 502具有一上表面 504。 介电层 506披覆于第一金属层 502上。 在上表面 504的位置对介电层 506开设一导孔 508， 导孔 508具有一斜孔壁 510， 斜孔壁 510具有上端缘 510-2。 第二金属层形成于导孔 508内作为孔垫 512。 孔 垫 512与上表面 504及斜孔壁 510接合， 形成的接合面具有上缘 530。 并且孔垫 512与斜孔壁 510接合面的上缘 530低于斜孔壁 510的上端缘 510-2。 并且， 孔垫 512尺寸也小于介电层 506的上端缘 510-2并位于其内部。
第一金属层 502及孔垫 512(第二金属层)的材质均可为铜。 介电层 506的材 质则较佳为聚醯亚胺 (PI, polyimide), 可以涂布方式披覆形成于第一金属层 502。 第二金属层 512是以金属剥离制程 (Metal Lift-Off)形成于导孔 508内 (于后 详述)。 由于本发明多层基板的导孔结构的孔垫 512 (VIA Land)是位于导孔 508 内， 无需如现有技术， 因光阻层的尺寸无法精确地决定孔垫尺寸 (VIA Land size), 导致线路设计时， 孔垫尺寸 (VIALand size)需要考量此制程误差， 而需 大于导孔尺寸 (VIA diameter)。 因此相较于现有技术， 能更进一步使多层基板 的导孔距 (接脚距)及金属线距的尺寸缩小， 提高多层基板的构装密度。
并且， 依据本发明以金属剥离制程 (Metal Lift-Off)形成孔垫 512于导孔 508 内， 使得孔垫 512对第一金属层 502以及介电层 506的斜孔壁 510均有良好的附 着性。 再者， 为使本发明多层基板的导孔结构中， 孔垫 512对第一金属层 502 以及介电层 506的斜孔壁 510间具有较圆滑的接合， 而能在多层基板折曲时， 导孔结构具有良好的延展性。 根据发明者的多次测试验证， 第一金属层 502 的上表面 504与斜孔壁 510间， 即斜孔壁 510的下端缘 510-4处形成的锐夹角 Θ 以小于 75 ° 为佳。 因此， 即便应用于软性、 可绕曲的软性电路板或封装基板 的折曲区域。本发明的导孔结构在多次折曲后依然维持原有的导孔结构完整， 不会发生剥裂， 依然维持第一金属层 502、 孔垫 512间的良好电性连接， 提高 多层基板的可靠度。
有关本发明利用金属剥离制程 (Metal Lift-Off),制作多层基板的导孔结构 的方法详述如下：
形成一第一金属层 502;
形成一介电层 506， 披覆于第一金属层 502上； 在第一金属层 502的上表面 504的位置开设一导孔 508， 使导孔 508具有一 斜孔壁 510;
对介电层 506表面及上表面 504涂布至少一光阻层 520;
对光阻层 520进行曝光；
去除位于导孔 508内的光阻层 520(图中未显示)， 例如： 选用负型光阻， 使 用显影剂 (Developer)去除光阻层 520， 则如图 5中所示， 光阻层 520上端缘 532 开孔的面积可控制为小于斜孔壁 510上端缘 510-2的面积而大于下端缘 510-4的 面积；
在导孔 508内形成孔垫 512及介电层 506表面的光阻层 520上形成一第二金 属层 512a， 使形成于导孔 508内的孔垫 512， 与上表面 504及斜孔壁 510接合； 以及
移除介电层 506表面的光阻层 520及光阻层 520上形成的第二金属层 512a。 至此， 即完成本发明多层基板的导孔结构。值得注意的是， 在本发明中， 形成在导孔 508内的第二金属层是用以作为一孔垫 512。 并且在去除位于导孔 508内光阻层 520的步骤中， 可同时去除在介电层 506上一预定位置的光阻层 520, 如图 6所示， 形成于预定位置的第二金属层是作为一金属导线 514， 与孔 垫 512接合形成一电性连接。 在本发明领域中， 光阻层 520大多是利用一光罩 以微影制程所定义，而光阻层开孔的上端缘 532即为利用光罩以精确度极高的 微影制程所转印而形成。 因此， 本发明相较于现有技术最大的优点是： 孔垫 512的形状及面积是由位于介电层 506表面的光阻层 520开孔的上端缘 532所定 义， 非常接近光罩的尺寸， 即原本电路设计时理想的尺寸。 也即无利用现有 技术蚀刻法及半加成法， 导致无法以光阻层精确地定义孔垫尺寸 (VIA Land size)的缺点。 在金属线路或导孔结构的尺寸精细度要求日益严格的当下及未 来， 本发明均能满足更进一步的要求。
以现今 Fine-pitch类产品相关业界中， 预期能实现达成的导孔深度 (VIA depth)约为 40 u m， 导孔尺寸 (VIA diameter)约为 40~60 μ m, 而孔垫尺寸 (VIA Land size)极限则约为 70 m。 而利用本发明能实现达成最小的导孔深度 (VIA depth)仅约 3 μ m， 导孔尺寸 (VIA diameter)仅约 5 μ m， 而孔垫尺寸 (VIA Land size)极限则仅约 7 u m。
请连同图 7—并参考图 6。图 6是表示本发明多层基板的导孔结构第二实施 例的说明图。 图 7是表示本发明第二实施例的多层基板的导孔结构的俯视图。 于第 6图中， 也仅显示有关本发明多层基板的导孔结构的部分， 本发明多层基 板的导孔结构包括有： 一第一金属层 502、 一介电层 506及一第二金属层。 详 述如下：
第一金属层 502具有一上表面 504。 介电层 506披覆于第一金属层 502上。 在上表面 504的位置对介电层 506开设一导孔 508， 导孔 508具有一斜孔壁 510。 一第二金属层， 形成于导孔 508内作为一孔垫 512， 以及在介电层 506上作为一 金属导线 514， 孔垫 512是与上表面 504及斜孔壁 510接合， 形成的接合面具有 上缘 530， 并且接合面上缘 530是低于斜孔壁 510的上端缘 510-2， 即孔垫 512尺 寸较介电层 506的上端缘 510-2为小并位于其内部。
与本发明的第一实施例不同的是， 在第二实施例中， 去除位于导孔 508 内的光阻层 520(图中未显示)的同时，也可去除介电层 506上例如：一定义金属 导线 514的预定位置 (例如： 线形沟， 图中未显示)中的光阻层 520。接着， 同时 在导孔 508内及在预定位置形成第二金属层分别作为孔垫 512及金属线路 514。 或者， 也可以不同制程步骤， 分别在导孔 508内及在预定位置形成不同的金属 层， 作为孔垫 512及金属线路 514， 但仍相互连接以实现相异层间的电性连接。 如同第一实施例， 孔垫 512对第一金属层 502以及介电层 506的斜孔壁 510间具 有较圆滑的接合， 并且孔垫 512及金属线路 514间的连接也较圆滑， 另外， 金 属线路 514位于导孔上端缘 510-2的位置也圆滑， 而能在多层基板折曲时， 具 有良好的延展性。根据发明者的多次测试验证，该第一金属层 502的上表面 504 与斜孔壁 510间， 即斜孔壁 510的下端缘 510-4处形成的锐夹角 Θ以小于 75 ° 为 佳。
如图 7所示， 一般而言， 孔垫 512与金属线路 514间是定义虚线 516作为分 界。 本发明多层基板的导孔结构中， 孔垫 512(VIA Land)是位于导孔 508(VIA) 内， 即小于导孔 508的上端缘 510-2， 大于下端缘 510-4。 因此， 本发明的孔垫 尺寸 (VIA Land size)能小于导孔尺寸 (VIA diameter)，无须在现有技术制程线路 设计时， 考量孔垫尺寸的误差。 同时又与金属线路 514间具有良好的接合， 能 降低现有技术的导孔结构剥裂的可能性。因此能更进一步缩小多层基板尺寸， 并且使多层基板的构装密度增加。 应用于现今运用广泛的软性电路板及软性 封装基板， 更可增加基板的可靠度。

Claims

权 利 要 求
1. 一种多层基板的导孔结构， 包括： 一第一金属层、 一介电层及一第二 金属层， 其中该第一金属层具有一上表面； 该介电层披覆于该第一金属层上， 并在对应于该第一金属层的该上表面的位置开设一导孔； 其特征在于： 该导 孔具有一斜孔壁， 该斜孔壁具有上端缘； 该第二金属层形成于该导孔内， 并 与该上表面及该斜孔壁接合， 形成的接合面具有上缘， 该接合面的该上缘低 于该斜孔壁的该上端缘。
2. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该第二金属 层也形成于该介电层上， 作为一金属导线， 形成于该导孔内的该第二金属层 是作为一孔垫， 该孔垫与该金属导线是同时形成。
3. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该斜孔壁的 下端缘面积小于该上端缘的面积。
4. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该第一金属 层的该上表面与该斜孔壁间形成的锐夹角小于 75° 。
5. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该多层基板 为软性多层基板。
6. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该第一金属 层的材料为铜。
7. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该第二金属 层的材料为铜。
8. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该介电层的 材料为聚醯亚胺。
9. 如权利要求 1所述的多层基板的导孔结构， 其特征在于： 该第二金属 层是以金属剥离制程形成于该导孔内。
10. 一种多层基板的导孔结构， 包括： 一第一金属层、 一介电层及一第 二金属层， 其中该第一金属层具有一上表面； 该介电层披覆于该第一金属层 上， 在对应于该第一金属层的该上表面的位置开设一导孔； 其特征在于： 该 导孔具有一斜孔壁， 该斜孔壁具有上端缘； 该第二金属层形成于该导孔内作 为一孔垫， 并形成于该介电层上的该第二金属层是作为一金属导线， 作为该 孔垫的该第二金属层与该上表面及该斜孔壁接合， 形成的接合面具有上缘， 该接合面的该上缘低于该斜孔壁的该上端缘。
11. 如权利要求 10所述的多层基板的导孔结构， 其特征在于： 该斜孔壁 的下端缘面积小于该上端缘的面积。
12. 如权利要求 10所述的多层基板的导孔结构， 其特征在于： 该第一金 属层的该上表面与该斜孔壁间形成的锐夹角小于 75 ° 。
13. 如权利要求 10所述的多层基板的导孔结构， 其特征在于： 该多层基 板为软性多层基板。
14. 如权利要求 10所述的多层基板的导孔结构， 其特征在于： 该第一金 属层的材料为铜。
15. 如权利要求 10所述的多层基板的导孔结构， 其特征在于： 该第二金 属层的材料为铜。
16. 如权利要求 10所述的导孔结构， 其特征在于： 该介电层的材料为聚 醯亚胺。
17. 如权利要求 10所述的多层基板的导孔结构， 其特征在于： 该第二金 属层是以金属剥离制程形成于该导孔内及该介电层上。
18. 一种制作多层基板的导孔结构的方法， 其特征在于： 该方法包括： 形成一第一金属层， 具有一上表面；
形成一介电层， 披覆于该第一金属层上；
在该介电层上并对应于该第一金属层的该上表面的位置开设一导孔， 使 该导孔具有一斜孔壁， 该斜孔壁具有上端缘；
对该介电层表面及该上表面涂布至少一光阻层；
对该光阻层进行曝光；
去除位于该导孔内的该光阻层；
在该导孔内及该介电层表面的该光阻层上形成一第二金属层， 使形成于 该导孔内的该第二金属层， 与该上表面及该斜孔壁接合， 形成的接合面具有 上缘； 以及
移除该介电层表面的该光阻层及该光阻层上形成的该第二金属层。
19. 如权利要求 18所述的方法， 其特征在于： 形成于该导孔内的该第二 金属层的形状及面积是由位于该介电层表面的该光阻层开孔的上端缘所定 义。
20. 如权利要求 18所述的方法， 其特征在于： 该斜孔壁的下端缘面积小 于该上端缘的面积。
21. 如权利要求 18所述的方法， 其特征在于： 该第一金属层的该上表面 与该斜孔壁间形成的锐夹角小于 75° 。
22. 如权利要求 18所述的方法， 其特征在于： 该介电层表面的该光阻层 上端缘的开孔面积是介于该斜孔壁的该上端缘面积及该斜孔壁的下端缘面积 之间。
23. 如权利要求 18所述的方法， 其特征在于： 在去除位于该导孔内该光 阻层的步骤中， 同时去除在该介电层上一预定位置的该光阻层， 形成于该导 孔内的该第二金属层是作为一孔垫， 形成于该预定位置的该第二金属层是作 为一金属导线。
24. 如权利要求 18所述的方法， 其特征在于： 该第一金属层的材料为铜。
25. 如权利要求 18所述的方法， 其特征在于： 该第二金属层的材料为铜。
26. 如权利要求 18所述的方法， 其特征在于： 该介电层的材料为聚醯亚 胺。
PCT/CN2009/070976 2008-11-03 2009-03-24 多层基板的导孔结构及其制造方法 WO2010060286A1 (zh)

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