580848 A7 —___________ B7 _ 1 丨丨· 一 — ---------------- 五、發明說明（） 【技術領域】 本發明係與電子工業有關，特別是關於一種印刷電路 板之電路佈局之電性連接體之製造方法。 5 【先前技術】 在習知的印刷電路板(printed circuit board，PCB)中’大 多都具有電性連接體（connections)，例如用以連接多層印 刷電路版（multi-layer PCB)層與層間之層間電性連接體 (interfacial connections)，或是用以連接該印刷電路板之電 10 路佈局（conductor pattern)與其他電子元件或電路的互連電 性連接體（interconnections)。 一般習知的製作互連電性連接體之方法為：將覆蓋於 境路佈局之抗姓罩（solder mask)之預定部位移除，藉以使 部分的電路佈局暴露，接著在電路佈局暴露的部份上鍍上 15 一層鎳-金層。此鎳-金層即為業界俗稱的，，金手指（golden fingers)”，可藉由打線(wire bonding)與其他電子元件或電 路連接。該鎳·金層亦可為焊塾(b〇n(jing pads)，可以直接 搭載(direct chip attach，DCA)的方式與一裸晶（bare chip)連 接。 經濟部智慧財產局員工消費合作社印製 裝--- 1 » f·· (請先閱讀背面之注意事項再填寫本頁) 20 至於在製作層間電性連接體時，電鍍法(plate method) 是業界最普遍使用之方法。因此，在習用的（多層）印刷電 路板上，我們常會發現鍍通孔(plated thr〇ugh h〇le，PTH)、 盲孔（blind hole)或埋孔（buried hole)。 習知的電性連接體大多會佔去較大的空間，而且在電 -3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） 580848 經濟部智慧財產局員工消費合作社印製 Λ7 B7_________ 五、發明說明（） 鍵微孔（plated via)之二端會有端接面（lands)的設置，因此， 電路佈局中二線路的間距（Pitch)被迫要加大。此不利於將 PCB體積縮小的設計趨勢。另外，電性連接體還有許多問 題，例如：微孔對準誤差（registration error of via)、微孔 5 内膠渣的清除（cleaning the smear)、塞孔(hole filling)以及 蚀薄銅（copper reduction)等問題。這些問題均會影響製程 的良率。 【詳細說明】 10 本發明之主要目的在於提供一種印刷電路板之電路佈 局之電性連接體之製造方法，其可減少電性連接體所佔用 之空間。 本發明之次一目的在於提供一種印刷電路板之電路佈 局之電性連接體之製造方法，其可提高製程之良率。 15 為達前述之發明目的，本發明所提供之印刷電路板之 免路佈局之電性連接體之製造方法，包含有下列步驟： a) 準備一基板，在其一面或二面上具有一導電層。 b) 將該導電層製作為一電路佈局，而該電路佈局具有 第一部分以及第二部分，其中該第一與該第二部分是具有 鬲度差且違弟一部分的南度高於該第二部分，以及 c) 設置一絕緣層覆蓋該電路佈局之第二部分，但是讓 該第一部分暴露。 【實施方式】 -4- -------------t--- Η €* (請先閱讀背面之注咅？事項再填寫本頁) 訂_ 本紙張尺度適用中國國^^7cNS)A4 規格（21〇χ 297公釐） 580848 A7 ___B7_ 五、發明說明（） 以下茲舉一較佳實施例，配合圖示，對本發明做進一 步之說明，其中 第一圖係本發明較佳實施例之流程圖； 第二圖係本發明較佳實施例所提供之製程之步驟a之 5 示意圖； 第三圖係本發明較佳實施例所提供之製程之步驟b之 π意圖， 第四圖係本發明較佳實施例所提供之製程之步驟c之 示意圖； 10 第五圖係本發明較佳實施例之形成具有高低差之電路 佈局之第一種方法之示意圖； 第六圖至第九圖係本發明較佳實施例之形成具有高低 差之電路佈局之第二種方法之示意圖； 第十圖至第十二圖係本發明較佳實施例之電路佈局之 15 第一部分暴露於絕緣層外之三種態樣之示意圖； 第十三圖至第十五圖係本發明較佳實施例應用於增層 法之示意圖，以及 第十六圖係本發明較佳實施例應用於製作金手指之示 意圖。 經濟部智慧財產局員工消費合作社印製 :!11,:-----;裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 20 請參閱第一圖至第四圖所示，本發明較佳實施例所提 供之印刷電路板之電路佈局之電性連接體之製造方法，包 含有下列步驟： a)準備一基板10,在其一面具有一導電層20。 請參閱第二圖，該基板10係以基板材料（base -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 580848 A7 五、發明說明（） material)，例如多功能環氧樹脂（multi-function epoxy resin) 所製成。而該導電層20係為一銅箔。 b)將該導電層20製作為一電路佈局21，而該電路佈 局21具有第一部分22以及第二部分23，其中該第一與 5 該第二部分22, 23是具有高度差，且該第一部分22的高 度高於該第二部分23。 請參閱第三圖，習知的照相顯影法（photochemical processes)施用於該導電層10，以移除不需要之部份，如 此可形成一電路佈局21。該電路佈局21具有第一部分22 10 以及第二部分23，其中該第一與該第二部分22, 23是具 有高度差，且該第一部分22的高度高於該第二部分23。 在此，發明人提供以下二種在電路佈局21上形成該第 一與該第二部分22, 23之方法： bl)請參閱第五圖，首先提供一厚度較大的電路佈局 15 21在該基板上，接著將該電路佈局21之預定部份移除， 使其變薄（圖中以虛線表示之部份）。如此，該電路佈局21 上較薄之部份即形成該第二部分23，而其餘較厚之部份 即為該第一部分22。 b2)請參閱第六圖至第九圖，先在基板10上設置一抗 20 蚀罩15，接著保角打開（conformal open)該抗蚀罩15之預 定部位，以形成微孔16。接著在該等微孔16中電鍍導電 材料(銅），以使電鍍導電材料填滿該等微孔16。最後再移 除該抗蝕罩15。如此，該等電鍍導電材料即形成第一部 分22，而其餘之部份即形成第二部分23。 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)580848 A7 —___________ B7 _ 1 丨 丨 · One—— ---------------- V. Description of the Invention (Technical Field) The present invention relates to the electronics industry, and particularly relates to a Method for manufacturing electrical connector of circuit layout of printed circuit board. 5 [Prior art] In conventional printed circuit boards (PCBs), most of them have electrical connections, for example, to connect layers between multi-layer PCBs and layers. Interfacial electrical connections (interfacial connections), or interconnected electrical connections (connector) used to connect the 10-conductor pattern of the printed circuit board with other electronic components or circuits. The conventional method for making an interconnect electrical connector is to remove a predetermined part of a solder mask covering the layout of the road to expose a part of the circuit layout, and then to expose the exposed part of the circuit layout. 15 parts are plated with a nickel-gold layer. This nickel-gold layer is commonly known in the industry as "golden fingers" and can be connected to other electronic components or circuits by wire bonding. The nickel-gold layer can also be a soldering tin (bon (jing pads), which can be directly mounted with a bare chip by direct chip attach (DCA). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs --- 1 »f ·· (Please read first (Notes on the back page, please fill out this page) 20 As for the production of interlayer electrical connectors, the plating method is the most commonly used method in the industry. Therefore, on conventional (multi-layer) printed circuit boards, we often find Plated through holes (PTH), blind holes or buried holes. Most conventional electrical connectors take up a large space, -This paper size applies to China National Standard (CNS) A4 specification (210 297 mm) 580848 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 B7_________ 5. Description of the invention () There will be two ends of the key via (plated via) The setting of the lands, so, The pitch of the two lines in the road layout is forced to increase. This is not conducive to the design trend of reducing the volume of the PCB. In addition, there are many problems with electrical connectors, such as: registration error of via ), Cleaning the smear, hole filling, and copper reduction in micropore 5. These problems will affect the yield of the process. [Detailed description] 10 The present invention The main purpose is to provide a method for manufacturing an electrical connector of a circuit layout of a printed circuit board, which can reduce the space occupied by the electrical connector. A second object of the present invention is to provide a circuit layout of a printed circuit board. A method for manufacturing a sexual connector, which can improve the yield of the manufacturing process. 15 In order to achieve the aforementioned object of the invention, a method for manufacturing an electrical connector of a printed circuit board free-path layout provided by the present invention includes the following steps: a ) Prepare a substrate with a conductive layer on one or both sides. B) Make the conductive layer into a circuit layout, and the circuit layout has the first part and Two parts, wherein the first part and the second part have higher degrees of difference and the south part of the part is higher than the second part; and c) an insulating layer is provided to cover the second part of the circuit layout, but let the The first part is exposed. [Embodiment] -4- ------------- t --- Η € * (Please read the note on the back? Please fill in this page for more details) Order _ This paper size applies to China ^^ 7cNS) A4 specification (21〇χ 297 mm) 580848 A7 ___B7_ V. Description of the invention () Here is a preferred embodiment, with illustrations, The present invention is further described, wherein the first diagram is a flowchart of a preferred embodiment of the present invention; the second diagram is a schematic diagram of step a-5 of the process provided by the preferred embodiment of the present invention; the third diagram is a comparison of the present invention The π intention of step b of the process provided by the preferred embodiment, the fourth diagram is a schematic diagram of step c of the process provided by the preferred embodiment of the present invention; 10 the fifth diagram is the formation of the preferred embodiment of the present invention with high and low differences Schematic diagram of the first method of circuit layout; Figures 6 to 9 are schematic diagrams of the second method of forming a circuit layout with step difference in the preferred embodiment of the present invention; Figures 10 to 12 are 15 of the preferred embodiment of the present invention is a schematic diagram of three aspects of the first part exposed to the insulation layer; Figures 13 to 15 are schematic diagrams of the preferred embodiment of the present invention applied to the build-up method, and First FIG six line embodiment of the present invention applied to a preferred embodiment of the production schematic cheat. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs:! 11,: -----; install -------- Order (Please read the precautions on the back before filling this page) 20 Please refer to the first As shown in Figures 4 to 4, the method for manufacturing an electrical connector of a circuit layout of a printed circuit board according to a preferred embodiment of the present invention includes the following steps: a) A substrate 10 is prepared, and a mask is provided with a conductive material. Layer 20. Please refer to the second figure. The substrate 10 is printed on the substrate material (base -5- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 580848 A7.) 2. Description of the invention () material), such as made of multi-function epoxy resin (multi-function epoxy resin). The conductive layer 20 is a copper foil. b) The conductive layer 20 is made into a circuit layout 21, and the circuit layout 21 has a first portion 22 and a second portion 23, where the first and 5 portions have a height difference, and the first portion The height of the portion 22 is higher than that of the second portion 23. Referring to the third figure, a conventional photochemical process is applied to the conductive layer 10 to remove unnecessary portions, so that a circuit layout 21 can be formed. The circuit layout 21 has a first portion 22 10 and a second portion 23, wherein the first portion 22 and the second portion 22 have a height difference, and the height of the first portion 22 is higher than the second portion 23. Here, the inventor provides the following two methods of forming the first and the second portions 22, 23 on the circuit layout 21: bl) Please refer to the fifth figure, and first provide a circuit layout 15 21 having a larger thickness in the Then, a predetermined portion of the circuit layout 21 is removed from the substrate to make it thin (the portion indicated by the dotted line in the figure). In this way, the thinner portion of the circuit layout 21 forms the second portion 23, and the remaining thicker portion is the first portion 22. b2) Please refer to the sixth to ninth figures. First, an anti-etching mask 15 is provided on the substrate 10, and then a predetermined portion of the resist mask 15 is conformally opened to form the micro-holes 16. A conductive material (copper) is then plated in the micro holes 16 so that the plated conductive material fills the micro holes 16. Finally, the resist 15 is removed. Thus, the plated conductive materials form the first portion 22, and the remaining portions form the second portion 23. -6- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
580848 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 10 15 在此要特別提出說明 、、〜 的疋，该罘一與該第二部分22 π 之咼低爰可預先在該導兩 2,23 a 〇Λ ^ ^ 導屯層20上形成，然後再將謗導而 層20製作成該電路佈总 導私 >丄，，不 局21，或亦可先將該導電層2〇愈J 作成該電路佈局21，炊接^ " 20製 ， “、、後再於該電路佈局21上形成 高低差之該第—與該第二部分22 23。 、有 C) Ρ月參閱第四圖，設置—絕緣層30覆蓋該電路体局21 之第二邵分23，但是讓該第一料22暴露。 该絕緣層30之設置可以塗佈（coating)或壓人 (laminating)等方式進行，或是如發明人之先前發明（US Pat. 6,395,625)^¾^^ (resin coated copper foil, RCC) 為之。 至於使孩電路佈局21之第一部分22暴露於該絕緣層 30外之方式有： 1.刷磨（scrubbing)該絕緣層30之表面。 2·電漿蚀刻（plasma etching)該絕緣層30之表面。 3·保角打開（conformal opening)該絕緣層30之預定部 位，以移除該絕緣層30位於該第一部分22上方之部份。 可以雷射或電漿蝕刻為之。 4·控制塗佈或壓合該絕緣層30之厚度，使其等於或略 小於該第一部分22之高度，如此在該絕緣層30完成後， 該第一部分22會自然暴露於外。 第十圖至第十二圖係顯示該電路佈局21之第一部分22 暴露於該絕緣層3 0外之三種態樣。第十圖顯示該第一部 分22與該絕緣層30呈平齊狀，前述之方法1、方法2與 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)580848 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention () 10 15 Special explanations should be provided here. The lower of the first and the second part 22 π can be pre-defined in the guide. Two 2,23 a 〇Λ ^ ^ is formed on the guide layer 20, and then the conductive layer 20 is made into the circuit cloth guide > 丄, not 21, or the conductive layer 2 may be first 〇 Yu J made the circuit layout 21, cooking connection ^ " 20 system, ", and then form the first and the second step on the circuit layout 21-and the second part 22 to 23. There are C) P See Fourth figure, setting-the insulating layer 30 covers the second component 23 of the circuit board 21, but the first material 22 is exposed. The setting of the insulating layer 30 can be coating or laminating, etc. Method, or as previously invented by the inventor (US Pat. 6,395,625) ^ ¾ ^^ (resin coated copper foil, RCC). As for exposing the first part 22 of the circuit layout 21 to the insulating layer 30 The methods are: 1. Scrubbing the surface of the insulating layer 30. 2. Plasma etching the insulation The surface of the layer 30. 3. Conformal opening a predetermined portion of the insulating layer 30 to remove the portion of the insulating layer 30 above the first portion 22. It can be laser or plasma etched. 4 Control the thickness of the insulating layer 30 by coating or pressing so that it is equal to or slightly smaller than the height of the first portion 22, so that after the insulating layer 30 is completed, the first portion 22 will be naturally exposed to the outside. The twelfth figure shows three aspects in which the first part 22 of the circuit layout 21 is exposed to the insulating layer 30. The tenth figure shows that the first part 22 is flush with the insulating layer 30, the aforementioned method 1, Method 2 and this paper size apply Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 580848 Λ7 B7_ 五、發明說明（) 方法4可能使該第一部分22形成如此之狀態。第十一圖 顯示該第一部分22呈凸出狀，前述之方法2與方法4可 能使該第一部分22形成如此之狀態。第十二圖顯示該第 一部分22呈凹陷狀，前述之方法3可能使該第一部分22 5 形成如此之狀態。 在此要特別提出說明，本較佳實施例之圖示係顯示該 基板10僅具有一面設有該具有高低差之該第一與該第二 部分22, 23之電路佈局21。實務上，該基板10之另一面 亦可以相同之方式形成一具有高低差之該第一與該第二部 10 分之電路佈局（未表示）。而二電路佈局間可以鍍通孔（PTH) 等方式達成電性連接。亦即，本發明可應用於單面印刷電 路板（single side PCB)以及雙面印刷電路板（double sides PCB)上。 當本發明之製作方法被應用於增層法(build-up process) 15 時，請參閱第十三圖至第十五圖，在該絕緣層30之表面 以化學沉積以及電鍍（非一定必要）之方式設置一第二導電 層40，其會於該電路佈局21之第一部分22達成實體與 電性之連接（第十三圖）。接著運用前述之方式，將該第二 導電層40製作成一第二電路佈局41，且其上具有第一部 20 分42與第二部分43(第十四圖）。該第一部分42與第二部 分43，如前所述，之間具有高低差，且該第一部分42之 高度高於第二部分43。接著再設置一第二絕緣層50，用 以覆蓋該第二電路佈局41之第二部分43，但使該第一部 分42暴露於外（第十五圖）。如此，即完成一雙層印刷電路 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I--— I. ·· --- 蝎 -* (請先閱讀背面之注意事項再填寫本頁) ^-r°J· 580848 A7 _____B7 五、發明說明(^ ^ 板(double-layer PCB)。重複執行前述的步驟b與步驟c即 可製作多層印刷電路板（multi-layer PCB)。而該等第—部 11 I 1111 •壯衣--- (請先閱讀背面之注意事項再填寫本頁) 分22, 42即形成層與層間之電路佈局21，41之層間電性連 接體。 5 當本發明之製作方法被應用於製作金手指或是焊栽 時，請參閱第十六圖，僅需要在該第一部分22之暴露^ 部份電鍍上一層鎳-金層60即可。 本發明之優點在於： 1·本發明之第一部分所需佔據之空間比習知的電鍍微 10孔(Platedvia)小，而且在電路佈局上並不需要設置端接^ : 因此該電路佈局可為無端接面（lancUess)的電路佈局。因 此，以本發明之方法所製成之印刷電路板之體積可縮小因 2·本發明呈實心之第一部分具有較佳之熱效應強度 (thermal strength)、與電路佈局以及絕緣層均具有較佳= 15附著狀態、無因基板漲縮所造成對準誤差之問題，以及具 有較佳的可靠度等優點，因此，以本發明所提供之方法所 製造出之印刷電路板具有較高之良率。 3·本發明之製造方法可同時應用於增層法或是製作金 手指。 … 經濟部智慧財產局員工消費合作社印製 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297 ^7 經濟部智慧財產局員工消費合作社印製 580848 A7 B7_ 五、發明說明（） 【圖示簡單說明】 第一圖係本發明較佳實施例之流程圖； 第二圖係本發明較佳實施例所提供之製程之步驟a之 示意圖； 5 第三圖係本發明較佳實施例所提供之製程之步驟b之 不·意圖， 第四圖係本發明較佳實施例所提供之製程之步驟c之 意圖， 第五圖係本發明較佳實施例之形成具有高低差之電路 10 佈局之第一種方法之示意圖； 第六圖至第九圖係本發明較佳實施例之形成具有高低 差之電路佈局之第二種方法之示意圖； 第十圖至第十二圖係本發明較佳實施例之電路佈局之 第一部分暴露於絕緣層外之三種態樣之7F意圖， 15 第十三圖至第十五圖係本發明較佳實施例應用於增層 法之示意圖，以及 第十六圖係本發明較佳實施例應用於製作金手指之示意 圖0 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 580848 Λ7 B7_ V. Description of the invention () Method 4 may make the first part 22 in such a state. The eleventh figure shows that the first portion 22 is convex. The aforementioned method 2 and method 4 may make the first portion 22 in such a state. The twelfth figure shows that the first portion 22 is in a concave shape, and the aforementioned method 3 may make the first portion 22 5 into such a state. It should be particularly noted here that the illustration of the preferred embodiment shows that the substrate 10 has only one side provided with the first and the second portions 22, 23 of the circuit layout 21 having the height difference. In practice, the other side of the substrate 10 can also form a circuit layout (not shown) of the first and second parts with a difference in height in the same manner. The two circuit layouts can be electrically connected by means of plated through holes (PTH). That is, the present invention can be applied to a single side printed circuit board (single side PCB) and a double side printed circuit board (double sides PCB). When the manufacturing method of the present invention is applied to the build-up process 15, please refer to FIGS. 13 to 15, and the surface of the insulating layer 30 is chemically deposited and electroplated (not necessarily necessary). In this way, a second conductive layer 40 is provided, which will achieve a physical and electrical connection in the first part 22 of the circuit layout 21 (Figure 13). Then, the second conductive layer 40 is fabricated into a second circuit layout 41 by using the aforementioned method, and has a first portion 20 and a second portion 43 (FIG. 14). The first portion 42 and the second portion 43 have a height difference as described above, and the height of the first portion 42 is higher than that of the second portion 43. Next, a second insulating layer 50 is provided to cover the second portion 43 of the second circuit layout 41, but to expose the first portion 42 to the outside (Fig. 15). In this way, a double-layer printed circuit is completed. -8- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) I ------ I. ·· --- Scorpion- * (Please read the back first Please note this page and fill in this page) ^ -r ° J · 580848 A7 _____B7 V. Description of the invention (^ ^ 板 (double-layer PCB). Repeat the above steps b and c to create a multilayer printed circuit board (multi -layer PCB). And the first part of the 11 I 1111 • strong clothing --- (Please read the precautions on the back before filling out this page) points 22, 42 form the circuit layout between the layers and the layers 21, 41 Electrical connector. 5 When the manufacturing method of the present invention is applied to the production of gold fingers or soldering, please refer to the sixteenth figure, only the nickel-gold layer needs to be plated on the exposed part ^ of the first part 22 60. The advantages of the present invention are: 1. The first part of the present invention requires less space than the conventional plated micro 10 holes (Platedvia), and does not need to be provided with a termination on the circuit layout. The circuit layout can be a circuit layout of a non-terminated surface (lancUess). Therefore, the method is made by the method of the present invention. The volume of the printed circuit board can be reduced because 2. The solid first part of the present invention has better thermal strength, and the circuit layout and the insulation layer have better = 15 adhesion state, no caused by the substrate expansion and contraction The problem of misalignment, as well as the advantages of better reliability, etc. Therefore, the printed circuit board manufactured by the method provided by the present invention has a higher yield. 3. The manufacturing method of the present invention can be applied at the same time to increase layers Or make a golden finger.… Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -9- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 x 297 ^ 7 Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 580848 A7 B7_ V. Description of the invention () [Brief description of the diagram] The first diagram is a flowchart of the preferred embodiment of the present invention; the second diagram is a diagram of step a of the process provided by the preferred embodiment of the present invention; The third figure is the intention of step b of the manufacturing process provided by the preferred embodiment of the present invention, and the fourth figure is the meaning of step c of the manufacturing process provided by the preferred embodiment of the present invention The fifth diagram is a schematic diagram of the first method for forming a circuit with a high-low step in the preferred embodiment of the present invention; the sixth to ninth diagrams are circuit layouts for forming a high-low step in the preferred embodiment of the present invention. Schematic diagram of the second method; The tenth to twelfth diagrams are the 7F intentions of the three aspects of the first part of the circuit layout of the preferred embodiment of the present invention exposed to the insulating layer, 15 thirteenth to tenth The fifth figure is a schematic diagram of the preferred embodiment of the present invention applied to the layering method, and the sixteenth figure is a schematic diagram of the preferred embodiment of the present invention applied to the production of golden fingers. 0 -10- This paper size is applicable to the Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the notes on the back before filling this page)
580848 A7 B7 五、發明說明（ 【圖號說明】 10基板 20導電層 23第二部分 30絕緣層 40第二導電層 43第二部分 50第二絕緣層 60鎳-金層 15抗蝕罩 21電路佈局 16微孔 22第一部分 41第二電路佈局42第一部分 經濟部智慧財產局員工消費合作社印刹衣 -11- (請先閱讀背面之注意事項再填寫本頁)580848 A7 B7 V. Description of the invention ([Illustration of drawing number] 10 substrate 20 conductive layer 23 second part 30 insulating layer 40 second conductive layer 43 second part 50 second insulating layer 60 nickel-gold layer 15 resist cover 21 circuit Layout 16 Micro-hole 22 First part 41 Second circuit layout 42 Part one The Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumption Cooperative Clothing-11- (Please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS)A4規格（21〇χ 297公t )This paper size is applicable to China National Standard (CNS) A4 (21〇χ 297 gt)