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五、發明說明（） 經濟部智慧財產局員工消費合作社衣 【技術領域】 本發明係與電子工業有關，特別是關於一種印刷電路 板之電路佈局之電性連接體之製造方法。 5 【先前技術】 在習知的印刷電路板(printed circuit board，PCB)中’大 多都具有電性連接體（connections)，例如用以連接多層印 刷電路版（multi-layer PCB)層與層間之層間電性連接體 (interfacial connections)，或是用以連接該印刷電路板之電 10 路佈局（conductor pattern)與其他電子元件或電路的互連電 性連接體（interconnections)。 一般習知的製作互連電性連接體之方法為：將覆蓋於 電路佈局之抗|虫罩（solder mask)之預定部位移除，藉以使 部分的電路佈局暴露，接著在電路佈局暴露的部份上鍍上 15 一層鎳-金層。此鎳·金層即為業界俗稱的，，金手指（golden fingers)”，可藉由打線(wire bonding)與其他電子元件或電 路連接。該鎳-金層亦可為焊塾(bonding pads)，可以直接 搭載(direct chip attach，DCA)的方式與一裸晶（bare chip)連 接。 20 至於在製作層間電性連接體時，電鍍法(plate method) 是業界最普遍使用之方法。因此，在習用的（多層）印刷電 路板上’我們常會發現鍵通孔(plate(j through hole，PTH)、 盲孔(Mind hole)或埋孔(buried hole)。 習知的電性連接體大多會佔去較大的空間，而且在電 -3- 本紙張尺度適用中國國家標準（CNSM4規格（210 X 297公爱) (靖先閱讀背面之注意事項再填寫本頁} 裝 Ί^τ.· 線· 200409572 Λ7 B7 五、發明說明（） I I -111--I I · 11 (請先閱讀背面之注意事項再填寫本頁) 鍍微孔（plated via)之二端會有端接面（lands)的設置，因此， 電路佈局中二線路的間距（pitch)被迫要加大。此不利於將 PCB體積縮小的設計趨勢。另外，電性連接體還有許多問 題’例如·微孔對準誤差（registrati〇n err〇r 〇f via)、微孔 5 内膠渣的清除（cleaning the smear)、塞孔（hole filling)以及 蝕薄銅（copper reduction)等問題。這些問題均會影響製程 的良率。 【詳細說明】 10 本發明之主要目的在於提供一種印刷電路板之電路佈 局之電性連接體之製造方法，其可減少電性連接體所佔用 之空間。 本發明《次一目的在於提供一種印刷電路板之電路佈 局之電性連接體之製造方法，其可提高製程之良率。 15 4達前述之發明目的，本發明所提供之印刷電路板之 ί線· 電路佈局之電性連接體之製造方法，包含有下列步驟： a) 準備一基板，在其一面或二面上具有一導電層。 b) 將該導電層製作為一電路佈局，而該電路佈局具有 第一部分以及第二部分，其中該第_與該第二部分是具有 經濟部智慧財產局員工消費合作社%^ 2〇高度差，且該第一部分的高度高於該第二部分，以及 c) 設置一絕緣層覆蓋該電路佈局之第二部分，但是讓 該第一部分暴露。 【實施方式】 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公餐） 200409572 意圖第十六圖係本發明較佳實施例應用於製作金手指之示 2〇供2參閱第一圖至第四圖所示，本發明較佳實施例所提 含有：::板之電路佈局之電性連接體之製造方法，包 a)準備-基板1()，在其—面具有_導電層2〇。 請參閱第二圖，該基板10係以基板材科(base A7 B7 五、發明說明（ 、下知舉一較佳實施例，配合圖示，對本發明做進一 步之說明，其中 a 第一圖係本發明較佳實施例之流程圖； 第二圖係本發明較佳實施例所提供之製程之步驟&之 5 示意圖； 罘三圖係本發明較佳實施例所提供之製程之步驟b之 不意圖； 一第四圖係本發明較佳實施例所提供之製程之 〇之 不意圖； 1〇 第五圖係本發明較佳實_之形成具有高低差之電路 佈局<第一種方法之示意圖； 弟六圖至第九圖係本發明較佳實施例之形成里有高低 電路侔局之第二種方法之示意圖； 15第^十_至第十二圖係本發明較佳實施例之電路佈局之 一★邵分暴露於絕緣層外之三種態樣之示意圖； 弟十三圖至第十五圖係本發明触實施觸用於增層 示意圖，以及 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（2ι〇 X视公爱V. Description of the invention () Consumer Cooperative Clothing for the Intellectual Property Bureau of the Ministry of Economic Affairs [Technical Field] The present invention relates to the electronics industry, and in particular relates to a method for manufacturing an electrical connector of a circuit layout of a printed circuit board. 5 [Prior art] In conventional printed circuit boards (PCBs), most of them have electrical connections, for example, to connect layers between multi-layer PCBs and layers. Interfacial electrical connections (interfacial connections), or interconnected electrical connections (connector) used to connect the 10-conductor pattern of the printed circuit board with other electronic components or circuits. Generally, a conventional method for making an interconnect electrical connector is: removing a predetermined portion of a solder mask covering a circuit layout to expose part of the circuit layout, and then exposing the exposed portion of the circuit layout 15 parts are plated with a nickel-gold layer. This nickel-gold layer is commonly known in the industry as "golden fingers" and can be connected to other electronic components or circuits by wire bonding. The nickel-gold layer can also be bonding pads , Can be directly mounted (direct chip attach, DCA) to connect with a bare chip. 20 As for the production of interlayer electrical connectors, the plating method is the most commonly used method in the industry. Therefore, On conventional (multilayer) printed circuit boards, we often find plate (j through hole (PTH), blind hole (bud hole), or buried hole). Most conventional electrical connectors will Takes up a lot of space, and is applicable to the Chinese national standard (CNSM4 specification (210 X 297 public love)) at the size of this paper. (Jing first read the precautions on the back before filling this page.) Ί ^ τ. · 线· 200409572 Λ7 B7 V. Description of the Invention (II) -111--II · 11 (Please read the precautions on the back before filling this page) There will be a land at the two ends of the plated via. Set, so the pitch of the two lines in the circuit layout is forced Large. This is not conducive to the design trend of reducing the volume of the PCB. In addition, there are many problems with electrical connectors, such as micro-hole alignment error (registrati〇n err〇r 〇f via), Problems such as cleaning the smear, hole filling, and copper reduction. These problems will affect the yield of the process. [Detailed description] 10 The main purpose of the present invention is to provide a printed circuit board The method for manufacturing an electrical connector with a circuit layout can reduce the space occupied by the electrical connector. The present invention provides a method for manufacturing an electrical connector with a circuit layout for a printed circuit board. To improve the yield of the process. 15 4 To achieve the aforementioned object of the invention, the method for manufacturing an electrical connector of a printed circuit board provided by the present invention includes the following steps: a) Prepare a substrate, There is a conductive layer on one or both sides. B) The conductive layer is made into a circuit layout, and the circuit layout has a first part and a second part, wherein the first and second Part is the height difference of% ^ 20 between the consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the height of the first part is higher than the second part, and c) an insulating layer is provided to cover the second part of the circuit layout, but let the The first part is exposed. [Embodiment] This paper size is in accordance with China National Standard (CNS) A4 specification (21 × 297 meals) 200409572. The intention is that the sixteenth figure is a preferred embodiment of the present invention applied to making golden fingers. 2 〇 For reference, as shown in the first to fourth figures, a method for manufacturing an electrical connector including :: a circuit layout of a board is provided in a preferred embodiment of the present invention, including a) preparation-substrate 1 (), in Its surface has a conductive layer 20. Please refer to the second figure. The base plate 10 is based on the base plate section (base A7 B7 V. Description of the invention (), a preferred embodiment is described below, and the figure is used to further explain the present invention, in which the first picture is The flowchart of the preferred embodiment of the present invention; the second diagram is a schematic diagram of steps & 5 of the process provided by the preferred embodiment of the present invention; the third diagram is the step b of the process provided by the preferred embodiment of the present invention Not intended; a fourth diagram is the intention of the manufacturing process provided by the preferred embodiment of the present invention; a fifth diagram is the preferred embodiment of the present invention_ forming a circuit layout with high and low differences < the first method Figures 6 to 9 are diagrams of the second method of forming a high-low circuit circuit in a preferred embodiment of the present invention; 15th to tenth to twelfth figures are preferred embodiments of the present invention One of the circuit layouts ★ Shao Fang is exposed to the three aspects of the insulation layer; Figures 13 to 15 are the schematic diagrams of the present invention's implementation and use for adding layers, and this paper scale is applicable to China National Standard (CNS) A4 Specification (2ιOX)
—^----；-------Μ — (請先閱讀背面之注意事項再填寫本頁) 一\*口*"- -線 200409572 經濟部智慧財產局員工消費合作社||?$衣 五、發明說明（ 15 20 ma=al) ’例如多功能環氧樹脂(mum_funeti 所製成。而孩導電層2〇係為一銅落。 b)將該導電層2〇製作為一 局21具有第—部 “佈局21，_路佈 .、乂 1 1刀22以及弟一邵分23,其中該第一與 該第二部分22, 23县且古古办辛 广 、有同度差，且該第一部分22的高 度高於該弟二部分23。 請參閱第三圖，習知的照相顯影法(photochemical processes)施用於該導電層1G，以移除Μ要之部份如 此可形成-電路佈局21。該電路佈局21具有第—部分Μ 以及第二部分23，其中該第—與該第二部分Α η是具 有高度差’且該第-部分22的高度高於該第二部分& 在此發明人提供以下二種在電路佈局^上形成該第 一與該第二部分22, 23之方法： bl) μ參閱第五圖，首先提供一厚度較大的電路佈局 21在S基板上接著將该電路伟局21之預定部份移除， 使其薄（圖中以虛線表示之部份）。如此，該電路佈局2 j 上較薄之部份即形成該第二部> 23，而其餘較厚之部份 即為該第一部分22。 b2)請參閱第六圖至第九圖，先在基板1〇上設置一抗 蝕罩15，接著保角打開（conformai 〇pen)該抗蝕罩丨5之預 定部位，以形成微孔16。接著在該等微孔16中電鍍導電 材料（銅），以使電鍍導電材料填滿該等微孔16。最後再移 除該抗蚀罩15。如此，該等電鍵導電材料即形成第一部 分22 ’而其餘之部份即形成第二部分23。 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---^----^-------裝--- (請先閱讀背面之注意事項再填寫本頁) -丨線· 200409572 A7 B? 五、發明說明（ >在此要特別提出說明的是，該第一與該第二部分U， 之高低差可預先在該導電層2〇上形成，然後再將謗導電 層2〇製作成該電路佈局21，或亦可先將該導電層如製 作成該電路佈局2卜然後再於該電路佈局21上形成具有 5高低差之該第一與該第二部分22,23。 ’、 c)叫參閱第四圖，設置_絕緣層3〇覆蓋該電路佈局b 之第二部分23，但是讓該第一部分22暴露。 該絕緣層30之設薏可以塗佈（c〇ating)或壓合 (laminating)等方式進行，或是如發明人之先前發明（us pat 10 6,395，625)所揭之以背膠鋼箔（resin c〇ated c〇pper f〇ii，rcc) 為之。 至於使該電路佈局21之第一部分22暴露於該絕緣層 30外之方式有： 1·刷磨（scrubbing)該絕緣層30之表面。 15 2.電漿蚀刻（plasma etching)該絕緣層30之表面。 3.保角打開（conformal opening)該絕緣層30之預定部 位，以移除該絕緣層30位於該第一部分22上方之部份。 可以雷射或電漿蝕刻為之。 4·控制塗佈或壓合該絕緣層30之厚度，使其等於或略 20 小於該第一部分22之高度，如此在該絕緣層30完成後， 該第/部分22會自然暴露於外。 第十圖至第十二圖係顯示該電路佈局21之第—部分22 暴露於該絕緣層3 0外之三種態樣。第十圖顯示該第一部 分22與該絕緣層30呈平齊狀，前述之方法1、方法2與 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 裝--- (請先閱讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員工消費合作社II?製 200409572 A7 B7 五、發明說明（ 15 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印ή 製·' · 20 方法4可能使該第一部分22形成如此之狀態。第十一圖 顯示該第一部分22呈凸出狀，前述之方法2與方法4可 能使該第一部分22形成如此之狀態。第十二圖顯示該第 一部分22呈凹陷狀，前述之方法3可能使該第一部分22 形成如此之狀態。 在此要特別提出說明，本較佳實施例之圖示係顯示該 基板10僅具有一面設有該具有高低差之該第一與該第二 部分22, 23之電路佈局21。實務上，該基板10之另一面 亦可以相同之方式形成一具有高低差之該第一與該第二部 分之電路佈局（未表示）。而二電路佈局間可以鍍通孔（ΡΤΗ) 等方式達成電性連接。亦即，本發明可應用於單面印刷電 路板（single side PCB)以及雙面印刷電路板（double sides PCB)上。 當本發明之製作方法被應用於增層法(build-up process) 時，請參閱第十三圖至第十五圖，在該絕緣層30之表面 以化學沉積以及電鍍（非一定必要）之方式設置一第二導電 層40，其會於該電路佈局21之第一部分22達成實體與 電性之連接（第十三圖）。接著運用前述之方式，將該第二 導電層40製作成一第二電路佈局41，且其上具有第一部 分42與第二部分43(第十四圖）。該第一部分42與第二部 分43，如前所述，之間具有高低差，且該第一部分42之 高度高於第二部分43。接著再設置一第二絕緣層50，用 以覆蓋該第二電路佈局41之第二部分43，但使該第一部 分42暴露於外（第十五圖）。如此，即完成一雙層印刷電路 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^ ^-------.— (請先閱讀背面之注意事項再填寫本頁) 訂·. ，線- 200409572 A7 _____ B7 五、發明說明（） 板(double-layer PCB) ^重複執行前述的步驟b與步驟c即 可製作多層印刷電路板(multi-layer PCB)。而該等第一部 分22, 42即形成層與層間之電路佈局21，41之層間電性連 接體。 5 當本發明之製作方法被應用於製作金手指或是焊墊 時，請參閱第十六圖，僅需要在該第一部分22之暴露之 部份電鏡上一層鎳-金層60即可。 本發明之優點在於： 1 ·本發明之第一部分所需佔據之空間比習知的電鍍微 10 孔(plated via)小，而且在電路佈局上並不需要設置端接面， 因此該電路佈局可為無端接面（landless)的電路佈局。因 此，以本發明之方法所製成之印刷電路板之體積可縮小。 2 ·本發明呈貫心之弟一部分具有較佳之熱效應強度 (thermal strength)、與電路佈局以及絕緣層均具有較佳之 15 附著狀態、無因基板漲縮所造成對準誤差之問題，以及具 有較佳的可靠度等優點，因此，以本發明所提供之方法所 製造出之印刷電路板具有較高之良率。 3·本發明之製造方法可同時應用於增層法或是製作金 手指。 . 裝·-- < (請先閱讀背面之注意事項再填寫本頁) --線· 經濟部智慧財產局員工消費合作社印f 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 200409572 A7 B7_ 五、發明說明（） 【圖示簡單說明】 第一圖係本發明較佳實施例之流程圖； 第二圖係本發明較佳實施例所提供之製程之步騾a之 示意圖； 5 第三圖係本發明較佳實施例所提供之製程之步驟b之 TF意圖， 第四圖係本發明較佳實施例所提供之製程之步驟C之 TF意圖， 第五圖係本發明較佳實施例之形成具有高低差之電路 10 佈局之第一種方法之示意圖； 第六圖至第九圖係本發明較佳實施例之形成具有高低 差之電路佈局之第二種方法之示意圖； 第十圖至第十二圖係本發明較佳實施例之電路佈局之 第一部分暴露於絕緣層外之三種態樣之示意圖； 15 第十三圖至第十五圖係本發明較佳實施例應用於增層 法之示意圖，以及 第十六圖係本發明較佳實施例應用於製作金手指之示意 圖。 ---裝— - 一 (請先閱讀背面之注意事項再填寫本頁) -線 經濟部智慧財產局員工消費合作社印‘|衣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 200409572 A7 B7 五、發明說明（） 經濟部智慧財產局員工消費合作社％ I衣 【圖號說明】 10基板 15抗蝕罩 16微孔 20導電層 21電路佈局 22第一部分 23第二部分 30絕緣層 40第二導電層 41第二電路佈局 42第一部分 43第二部分 50第二絕緣層 60鎳·金層 --^-------------- (請先閱讀背面之注意事項再填寫本頁) · 丨線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f )— ^ ---- ； ------- Μ — (Please read the notes on the back before filling out this page) A \ * 口 * "--line 200409572 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs || 5. Clothing description (15 20 ma = al) 'For example, made of multifunctional epoxy resin (mum_funeti. The conductive layer 20 is a copper drop. B) The conductive layer 20 is made as a Bureau 21 has the first-part "Layout 21, _ Lu Bu., 乂 1 1 knife 22, and brother Yi Shaofen 23, where the first and the second part 22, 23 counties and the ancient ancient office are wide and have the same degree Poor, and the height of the first part 22 is higher than the second part 23. Please refer to the third figure, the conventional photochemical processes are applied to the conductive layer 1G, so that it is possible to remove the necessary part of M A circuit layout 21 is formed. The circuit layout 21 has a first portion M and a second portion 23, wherein the first and second portions A n have a height difference 'and the height of the second portion 22 is higher than the second portion 22 Section & Here the inventor provides the following two methods of forming the first and second sections 22, 23 on the circuit layout ^: bl) μ Refer to the fifth figure, the first First provide a thicker circuit layout 21 on the S substrate, and then remove the predetermined portion of the circuit magnate 21 to make it thin (the portion indicated by the dotted line in the figure). Thus, the circuit layout 2 j The thinner part forms the second part > 23, and the remaining thicker part becomes the first part 22. b2) Please refer to the sixth to ninth figures, first set a primary antibody on the substrate 10. The etch mask 15 is then conformally opened to a predetermined portion of the resist mask 5 to form micro holes 16. Then, a conductive material (copper) is plated in the micro holes 16 to fill the plated conductive material. Fill the micro-holes 16. Finally remove the resist cover 15. In this way, the electrically conductive material of the keys will form the first part 22 'and the remaining part will form the second part 23. -6- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) --- ^ ---- ^ ------- install --- (Please read the precautions on the back before filling this page)-丨 Line · 200409572 A7 B? 5. Description of the invention (> It should be particularly mentioned here that the difference in height between the first and the second part U can be specified in advance. The electrical layer 20 is formed, and then the conductive layer 20 is made into the circuit layout 21, or the conductive layer can also be made into the circuit layout 2 and then formed on the circuit layout 21 with a height of 5 The difference between the first part and the second part 22,23. ', C) Refer to the fourth figure, and set the insulation layer 30 to cover the second part 23 of the circuit layout b, but let the first part 22 be exposed. The setting of the insulating layer 30 can be performed by coating or laminating, or by using a self-adhesive steel foil (as disclosed by the inventor's previous invention (us pat 10 6,395,625)) Resin coated copper foii (rcc). As for exposing the first portion 22 of the circuit layout 21 to the insulation layer 30, there are: 1. Scrubbing the surface of the insulation layer 30. 15 2. Plasma etching the surface of the insulating layer 30. 3. Conformal opening a predetermined portion of the insulating layer 30 to remove a portion of the insulating layer 30 above the first portion 22. Can be laser or plasma etching. 4. Control the thickness of the insulating layer 30 by coating or pressing so that it is equal to or slightly less than the height of the first portion 22, so that after the insulating layer 30 is completed, the / section 22 will be naturally exposed to the outside. The tenth to twelfth diagrams show three aspects of the circuit layout 21-part 22 exposed to the insulating layer 30. The tenth figure shows that the first part 22 and the insulating layer 30 are flush. The aforementioned method 1, method 2 and the paper size are applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm). Please read the notes on the back before filling out this page.) Order · The Intellectual Property Bureau of the Ministry of Economic Affairs ’Consumer Consumption Cooperative System II? 200409572 A7 B7 V. Description of the Invention (15 The Intellectual Property Bureau of the Ministry of Economic Affairs’ Employee Consumption Cooperative System ”· 20 4 may make the first part 22 in such a state. The eleventh figure shows that the first part 22 is convex, and the aforementioned methods 2 and 4 may make the first part 22 in such a state. The twelfth figure shows that The first part 22 is in a concave shape, and the above-mentioned method 3 may make the first part 22 into such a state. It should be particularly noted here that the illustration of the preferred embodiment shows that the substrate 10 has only one side provided with the height. The circuit layout 21 of the difference between the first and the second parts 22, 23. In practice, the other side of the substrate 10 can also form the first and the second parts with a difference in height. Circuit layout (not shown). The two circuit layouts can be electrically connected by means of plated through holes (PTT). That is, the invention can be applied to single side printed circuit boards (single side PCB) and double-sided printed circuits. On the double sides PCB. When the manufacturing method of the present invention is applied to the build-up process, please refer to FIG. 13 to FIG. 15, and the surface of the insulating layer 30 is chemically deposited. And electroplating (not necessarily necessary) a second conductive layer 40 is provided, which will achieve a physical and electrical connection in the first part 22 of the circuit layout 21 (figure 13). Then using the aforementioned method, the The second conductive layer 40 is fabricated as a second circuit layout 41, and has a first portion 42 and a second portion 43 (fourteenth figure) thereon. The first portion 42 and the second portion 43, as described above, have The height difference, and the height of the first portion 42 is higher than the second portion 43. Then, a second insulating layer 50 is provided to cover the second portion 43 of the second circuit layout 41, but the first portion 42 is exposed to Outside (fifteenth picture). That is, a double-layer printed circuit is completed. -8- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ^ ^ -------.— (Please read the precautions on the back before filling (This page) Order .., line-200409572 A7 _____ B7 V. Description of the invention () Double-layer PCB ^ Repeat steps b and c to make a multi-layer PCB. The first portions 22, 42 form the inter-layer electrical connection bodies of the circuit layouts 21, 41 of the layers. 5 When the manufacturing method of the present invention is applied to making gold fingers or solder pads, please refer to the sixteenth figure, and only a nickel-gold layer 60 is required on the exposed part of the first part 22 of the electron microscope. The advantages of the present invention are as follows: 1. The first part of the present invention requires less space than the conventional plated vias, and does not require a termination surface on the circuit layout, so the circuit layout can be Layout for a landless circuit. Therefore, the volume of the printed circuit board produced by the method of the present invention can be reduced. 2 · Part of the present invention has better thermal strength, better adhesion to circuit layout and insulation layer, no problem of alignment error caused by substrate expansion and contraction, Good reliability and other advantages. Therefore, the printed circuit board manufactured by the method provided by the present invention has a higher yield. 3. The manufacturing method of the present invention can be applied to both the build-up method and the gold finger. Packing --- < (Please read the precautions on the back before filling out this page) --Line · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs f This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 200409572 A7 B7_ V. Description of the invention () [Simplified illustration of the diagram] The first diagram is a flowchart of the preferred embodiment of the present invention; the second diagram is the steps of the process provided by the preferred embodiment of the present invention. The schematic diagram of a; 5 The third diagram is the TF intention of step b of the process provided by the preferred embodiment of the present invention, the fourth diagram is the TF intention of step C of the process provided by the preferred embodiment of the present invention, the fifth diagram It is a schematic diagram of the first method of forming a circuit with a high and low difference in the preferred embodiment of the present invention. The sixth to ninth figures are the second method of forming a circuit with a high and low difference in the preferred embodiment of the present invention. Schematic diagram of the method; Figures 10 to 12 are schematic diagrams of the three aspects of the first part of the circuit layout of the preferred embodiment of the present invention exposed to the insulating layer; 15 Figures 13 to 15 are the present invention The preferred embodiment applies to The schematic diagram of the layer method, and the sixteenth diagram are schematic diagrams of applying the preferred embodiment of the present invention to the production of golden fingers. --- Packing--I (Please read the precautions on the back before filling out this page)-Printed by the Consumers 'Cooperatives of the Intellectual Property Bureau of the Ministry of Line Economy' | The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 (Mm) 200409572 A7 B7 V. Description of the invention () Employees ’cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs [Cloth No.] 10 substrate 15 resist cover 16 micro-hole 20 conductive layer 21 circuit layout 22 first part 23 second part 30 Insulating layer 40 Second conductive layer 41 Second circuit layout 42 First part 43 Second part 50 Second insulating layer 60 Nickel-gold layer-^ -------------- (please first Read the notes on the back and fill in this page) · 丨 Line-This paper size is applicable to China National Standard (CNS) A4 (210 X 297mm f)