JP4165460B2 - 半導体装置 - Google Patents
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Description
本発明は上記問題に鑑みなされたものであり、チップ面積の小さいCSP構造の半導体装置の信頼性を向上させること、及び電極パッドと突起電極の数の多いCSP構造の半導体装置の信頼性を向上させることを目的とする。
すなわち、本発明の半導体装置は、主表面を有する半導体基板と、前記主表面上に形成された電極パッドと、前記電極パッドの表面の一部を露出する第1の開口部を有し、前記主表面上を覆うパッシベーション膜と、前記電極パッドの表面の一部を露出し前記第1の開口部よりも内側に配置された第2の開口部を有し、前記パッシベーション膜上を覆う絶縁膜と、外縁を有し前記電極パッドに電気的に接続された柱状の突起電極と、前記突起電極の側面及び前記絶縁膜上を覆う封止樹脂とを有する半導体装置であって、前記第2の開口部は、前記突起電極の外縁よりも内側に配置されていることを特徴としている。
図1(b)の上面図に示すように、本実施形態においては、電極パッド102と突起電極106とは完全に重なる。具体的には、絶縁膜104の開口部(第2の開口部)の直径は突起電極106の直径より小さく、パッシベーション膜103の開口部(第1の開口部)の中心、絶縁膜104の開口部の中心、及び突起電極106の中心は略一致し、上から見たときにパッシベーション膜103及び絶縁膜104の開口部は突起電極106の中に完全に含まれる。即ち、図1(a)において、平行な点線の内側に位置するようにそれらの開口部を形成する。
Claims (4)
- 主表面を有する半導体基板と、
前記主表面上に形成された電極パッドと、
前記電極パッドの表面の一部を露出する第1の開口部を有し、前記主表面上を覆うパッシベーション膜と、
前記電極パッドの表面の一部を露出し前記第1の開口部よりも内側に配置された第2の開口部を有し、前記パッシベーション膜上を覆う絶縁膜と、
外縁を有し前記電極パッドに電気的に接続された柱状の突起電極と、
前記突起電極の側面及び前記絶縁膜上を覆う封止樹脂とを有する半導体装置であって、
前記第2の開口部は、前記突起電極の外縁よりも内側に配置されていることを特徴とする半導体装置。 - 前記第1の開口部は、前記突起電極の外縁よりも内側に配置されていることを特徴とする請求項1記載の半導体装置。
- 前記第1の開口部は、前記突起電極の外縁の直下を跨ぐように配置されていることを特徴とする請求項1記載の半導体装置。
- 主表面を有する半導体基板と、
前記主表面上に形成された複数の電極パッドであって、前記半導体基板のコーナー部に配置された第1の電極パッドと、前記コーナー部を除く領域に配置された第2の電極パッドとを含む複数の電極パッドと、
前記第1及び第2の電極パッドの各々の表面の一部を露出する第1の開口部を有し、前記主表面上を覆うパッシベーション膜と、
前記第1及び第2の電極パッドの各々の表面の一部を露出し前記第1の開口部よりも内側に配置された第2の開口部を有し、前記パッシベーション膜上を覆う絶縁膜と、
外縁を有し対応する前記電極パッドの各々に電気的に接続された複数の柱状の突起電極と、
前記突起電極の側面及び前記絶縁膜上を覆う封止樹脂とを有する半導体装置であって、
前記第2の開口部は、前記突起電極の外縁よりも内側に配置されており、前記第2の電極パッドに対応する前記第1の開口部は、前記突起電極の外縁よりも内側に配置されており、前記第1の電極パッドに対応する前記第1の開口部は、前記突起電極の外縁の直下を跨ぐように配置されていることを特徴とする半導体装置。
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JP2004175098A JP4165460B2 (ja) | 2003-06-13 | 2004-06-14 | 半導体装置 |
US10/866,195 US7180185B2 (en) | 2003-06-13 | 2004-06-14 | Semiconductor device with connections for bump electrodes |
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JP2003169010 | 2003-06-13 | ||
JP2004175098A JP4165460B2 (ja) | 2003-06-13 | 2004-06-14 | 半導体装置 |
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JP4165460B2 true JP4165460B2 (ja) | 2008-10-15 |
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Families Citing this family (10)
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JP4381191B2 (ja) * | 2004-03-19 | 2009-12-09 | Okiセミコンダクタ株式会社 | 半導体パッケージ及び半導体装置の製造方法 |
US7451436B2 (en) * | 2004-11-23 | 2008-11-11 | National Instruments Corporation | Aggregate handling of operator overloading |
CN100416875C (zh) * | 2005-03-30 | 2008-09-03 | 南茂科技股份有限公司 | 使用凸块进行封装的结构及其形成方法 |
JP5165190B2 (ja) | 2005-06-15 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
JP4430062B2 (ja) * | 2006-12-06 | 2010-03-10 | シャープ株式会社 | Icチップ実装パッケージの製造方法 |
JP4708399B2 (ja) * | 2007-06-21 | 2011-06-22 | 新光電気工業株式会社 | 電子装置の製造方法及び電子装置 |
US20110186899A1 (en) * | 2010-02-03 | 2011-08-04 | Polymer Vision Limited | Semiconductor device with a variable integrated circuit chip bump pitch |
JP2012028708A (ja) | 2010-07-27 | 2012-02-09 | Renesas Electronics Corp | 半導体装置 |
JP2012064698A (ja) * | 2010-09-15 | 2012-03-29 | Ricoh Co Ltd | 半導体装置及びそのレイアウト方法 |
US11063009B2 (en) * | 2017-04-10 | 2021-07-13 | Renesas Electronics Corporation | Semiconductor device |
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US5152598A (en) * | 1990-10-24 | 1992-10-06 | Schaffer Garry D | Hole locator device |
US6739744B2 (en) * | 1997-07-02 | 2004-05-25 | Lumitex, Inc. | Light delivery systems and applications thereof |
US5921673A (en) * | 1997-11-13 | 1999-07-13 | Habel; David M. | Illuminated threading tool |
US6075290A (en) * | 1998-02-26 | 2000-06-13 | National Semiconductor Corporation | Surface mount die: wafer level chip-scale package and process for making the same |
JP4394266B2 (ja) | 2000-09-18 | 2010-01-06 | カシオ計算機株式会社 | 半導体装置および半導体装置の製造方法 |
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