JP4430062B2 - Icチップ実装パッケージの製造方法 - Google Patents
Icチップ実装パッケージの製造方法 Download PDFInfo
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- JP4430062B2 JP4430062B2 JP2006329993A JP2006329993A JP4430062B2 JP 4430062 B2 JP4430062 B2 JP 4430062B2 JP 2006329993 A JP2006329993 A JP 2006329993A JP 2006329993 A JP2006329993 A JP 2006329993A JP 4430062 B2 JP4430062 B2 JP 4430062B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 48
- 238000004080 punching Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 description 22
- 239000004973 liquid crystal related substance Substances 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 12
- 230000007547 defect Effects 0.000 description 10
- 238000005304 joining Methods 0.000 description 10
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 6
- 238000007789 sealing Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000012876 carrier material Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000027455 binding Effects 0.000 description 1
- 238000009739 binding Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81208—Compression bonding applying unidirectional static pressure
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- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
生じたりするといった不具合が発生する。このようなフィルム基材2における熱膨張は、従来のSOF構造においても発生するが、デバイスホール8が設けられている本発明の構造では、デバイスホール8の外縁でフィルム基材2が自由端となるため上記波打ちが発生しやすい。
2 フィルム基材(パッケージ基材)
3 ICチップ
4 インターポーザ
5 フィルム上配線
6 フィルム上配線
8 デバイスホール
9 第1のバンプ(バンプ電極)
12 ICチップ接続用端子(ICチップ側接続端子)
13 フィルム基材接続用端子(パッケージ基材側接続端子)
14 インターポーザ上配線
Claims (10)
- 出入力端子群を有するICチップと、
上記ICチップを実装するための、接続端子群を有するパッケージ基材とを備えたICチップ実装パッケージの製造方法において、
上記ICチップとパッケージ基材とは、上記接続端子群と接続するように構成されたパッケージ基材側接続端子群と、上記出入力端子群と接続するように構成されたICチップ側接続端子群と、当該パッケージ基材側接続端子群及びICチップ側接続端子群を接続する配線とを有したインターポーザを用いて接続されるものであると共に、上記ICチップは、上記パッケージ基材に形成されたデバイスホール内に配置されるものであり、
上記パッケージ基材におけるデバイスホールは、上記パッケージ基材上の上記接続端子群を含む配線が上記パッケージ基材上に形成された後に打ち抜きによって形成されるものであり、上記パッケージ基材上に形成される接続端子の先端から上記デバイスホールの縁までの距離は10μm以上かつ150μm以下に設定されていることを特徴とするICチップ実装パッケージの製造方法。 - 上記ICチップの外縁と上記インターポーザの外縁との距離は、0.20mm以上0.46mm以下に設定されていることを特徴とする請求項1に記載のICチップ実装パッケージの製造方法。
- 上記ICチップの外縁と上記インターポーザの外縁との距離は、周囲の全ての辺で同じ大きさに設定されていることを特徴とする請求項2に記載のICチップ実装パッケージの製造方法。
- 上記ICチップの外縁と上記インターポーザの外縁との距離は、短辺同士の間の距離よりも長辺同士の間の距離の方が大きく設定されていることを特徴とする請求項2に記載のICチップ実装パッケージの製造方法。
- 上記ICチップの外縁と上記インターポーザの外縁との距離は、長辺同士の間の距離よりも短辺同士の間の距離の方が大きく設定されていることを特徴とする請求項2に記載のICチップ実装パッケージの製造方法。
- 上記ICチップの外縁と上記デバイスホールの外縁との距離は、30μm以上150mm以下に設定されていることを特徴とする請求項1に記載のICチップ実装パッケージの製造方法。
- 上記ICチップの外縁と上記デバイスホールの外縁との距離は、周囲の全ての辺で同じ大きさに設定されていることを特徴とする請求項6に記載のICチップ実装パッケージの製造方法。
- 上記デバイスホールのコーナー部は、Rが付いた形状とされていることを特徴とする請求項1に記載のICチップ実装パッケージの製造方法。
- 上記デバイスホールのコーナー部は、R半径が0.1mm以下に設定されていることを特徴とする請求項8に記載のICチップ実装パッケージの製造方法。
- 上記パッケージ基材と上記インターポーザとの接続は、該パッケージ基材の接続端子に形成されたバンプ電極を上記パッケージ基材の接続端子に対してボンディングによって接続するものであり、
上記ボンディングに使用されるボンディングツールの外形寸法は、該ボンディングツールの外縁と上記バンプ電極の外縁とを一致させるように設定することを特徴とする請求項1に記載のICチップ実装パッケージの製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006329993A JP4430062B2 (ja) | 2006-12-06 | 2006-12-06 | Icチップ実装パッケージの製造方法 |
US12/312,981 US8129825B2 (en) | 2006-12-06 | 2007-11-30 | IC chip package employing substrate with a device hole |
PCT/JP2007/073189 WO2008069135A1 (ja) | 2006-12-06 | 2007-11-30 | Icチップ実装パッケージ |
CN2007800451678A CN101558489B (zh) | 2006-12-06 | 2007-11-30 | Ic芯片封装的制造方法 |
TW096146128A TWI363403B (en) | 2006-12-06 | 2007-12-04 | Ic chip package producing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006329993A JP4430062B2 (ja) | 2006-12-06 | 2006-12-06 | Icチップ実装パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008147262A JP2008147262A (ja) | 2008-06-26 |
JP4430062B2 true JP4430062B2 (ja) | 2010-03-10 |
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JP2006329993A Active JP4430062B2 (ja) | 2006-12-06 | 2006-12-06 | Icチップ実装パッケージの製造方法 |
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US (1) | US8129825B2 (ja) |
JP (1) | JP4430062B2 (ja) |
CN (1) | CN101558489B (ja) |
TW (1) | TWI363403B (ja) |
WO (1) | WO2008069135A1 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP4219953B2 (ja) * | 2006-12-11 | 2009-02-04 | シャープ株式会社 | Icチップ実装パッケージ、およびその製造方法 |
US11404375B2 (en) * | 2019-09-26 | 2022-08-02 | Rohm Co., Ltd. | Terminal configuration and semiconductor device |
KR20230023834A (ko) * | 2020-12-09 | 2023-02-20 | 주식회사 솔루엠 | 에어포켓 방지 기판, 에어포켓 방지 기판 모듈, 이를 포함하는 전기기기 및 이를 포함하는 전기기기의 제조 방법 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2852703B2 (ja) * | 1990-11-14 | 1999-02-03 | イビデン株式会社 | フィルムキャリア |
JPH11330167A (ja) * | 1998-05-19 | 1999-11-30 | Matsushita Electric Ind Co Ltd | テープキャリアパッケージ |
JP3967263B2 (ja) * | 2002-12-26 | 2007-08-29 | セイコーインスツル株式会社 | 半導体装置及び表示装置 |
US7180185B2 (en) * | 2003-06-13 | 2007-02-20 | Oki Electric Industry Co., Ltd | Semiconductor device with connections for bump electrodes |
JP2007335607A (ja) | 2006-06-14 | 2007-12-27 | Sharp Corp | Icチップ実装パッケージ、及びこれを用いた画像表示装置 |
-
2006
- 2006-12-06 JP JP2006329993A patent/JP4430062B2/ja active Active
-
2007
- 2007-11-30 US US12/312,981 patent/US8129825B2/en active Active
- 2007-11-30 WO PCT/JP2007/073189 patent/WO2008069135A1/ja active Application Filing
- 2007-11-30 CN CN2007800451678A patent/CN101558489B/zh active Active
- 2007-12-04 TW TW096146128A patent/TWI363403B/zh active
Also Published As
Publication number | Publication date |
---|---|
TW200841429A (en) | 2008-10-16 |
US8129825B2 (en) | 2012-03-06 |
WO2008069135A1 (ja) | 2008-06-12 |
CN101558489B (zh) | 2011-11-09 |
TWI363403B (en) | 2012-05-01 |
CN101558489A (zh) | 2009-10-14 |
JP2008147262A (ja) | 2008-06-26 |
US20100019394A1 (en) | 2010-01-28 |
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