JP4045261B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4045261B2 JP4045261B2 JP2004175097A JP2004175097A JP4045261B2 JP 4045261 B2 JP4045261 B2 JP 4045261B2 JP 2004175097 A JP2004175097 A JP 2004175097A JP 2004175097 A JP2004175097 A JP 2004175097A JP 4045261 B2 JP4045261 B2 JP 4045261B2
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- electrode
- insulating film
- semiconductor device
- protruding electrode
- columnar electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本発明は上記問題に鑑みなされたものであり、CSP構造の半導体装置を、突起電極に加わる応力及び突起電極の下部に加わるせん断応力の両方から保護することを目的とする。
図1(b)に図1(a)と直角な方向から見た断面構造を示す。また、図1(c)に該構造の上面図を示す。これらの図に示したように、本実施例は突起電極106を支持する絶縁膜104に、該突起電極の底部の周縁に沿って伸びるスリット状の開口を形成したことを特徴とする。
また、突起電極106の周縁からスリットまでの距離が長いと、絶縁膜104の弾性変形による応力緩和の効果が小さくなるので、半導体装置の製造の際の位置合わせ精度は上記距離を10μm以内にできる程度のものとすることが好ましい。
Claims (1)
- 主表面を有する半導体基板と、
前記主表面上に形成された電極パッドと、
前記電極パッドの表面の一部を露出する開口部を有し、前記主表面上を覆うパッシベーション膜と、
前記パッシベーション膜上に設けられた絶縁膜と、
周縁及び前記周縁に囲まれた中央部を有し、前記絶縁膜上に配置された柱状電極であって、前記電極パッドに電気的に接続された柱状電極と、
前記柱状電極の先端が露出するように前記柱状電極の側面及び前記絶縁膜上を覆う封止樹脂とを有する半導体装置であって、
前記柱状電極の前記周縁の直下に位置する前記絶縁膜の厚さは、前記柱状電極の前記中心部の直下に位置する前記絶縁膜の厚さ及び前記柱状電極が配置されていない領域に位置する前記絶縁膜の厚さよりも厚く形成されていることを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/866,189 US7358608B2 (en) | 2003-06-13 | 2004-06-14 | Semiconductor device having chip size package with improved strength |
JP2004175097A JP4045261B2 (ja) | 2003-06-13 | 2004-06-14 | 半導体装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003169013 | 2003-06-13 | ||
JP2004175097A JP4045261B2 (ja) | 2003-06-13 | 2004-06-14 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005026678A JP2005026678A (ja) | 2005-01-27 |
JP4045261B2 true JP4045261B2 (ja) | 2008-02-13 |
Family
ID=34067307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004175097A Expired - Fee Related JP4045261B2 (ja) | 2003-06-13 | 2004-06-14 | 半導体装置 |
Country Status (2)
Country | Link |
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US (1) | US7358608B2 (ja) |
JP (1) | JP4045261B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7999379B2 (en) * | 2005-02-25 | 2011-08-16 | Tessera, Inc. | Microelectronic assemblies having compliancy |
JP4818005B2 (ja) * | 2006-07-14 | 2011-11-16 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP2009010260A (ja) * | 2007-06-29 | 2009-01-15 | Fujikura Ltd | 半導体装置 |
US7935408B2 (en) * | 2007-10-26 | 2011-05-03 | International Business Machines Corporation | Substrate anchor structure and method |
JP5199189B2 (ja) * | 2009-06-29 | 2013-05-15 | ラピスセミコンダクタ株式会社 | 半導体装置、及び半導体装置の製造方法 |
US8736487B2 (en) | 2011-09-21 | 2014-05-27 | Csr Technology Inc. | Method and apparatus of using height aiding from a contour table for GNSS positioning |
JP6329059B2 (ja) * | 2014-11-07 | 2018-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9984987B2 (en) * | 2016-08-05 | 2018-05-29 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
JP7500208B2 (ja) * | 2020-02-04 | 2024-06-17 | ラピスセミコンダクタ株式会社 | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5291374A (en) * | 1990-12-17 | 1994-03-01 | Kabushiki Kaisha Toshiba | Semiconductor device having an opening and method of manufacturing the same |
JPH09107048A (ja) | 1995-03-30 | 1997-04-22 | Mitsubishi Electric Corp | 半導体パッケージ |
TW448524B (en) | 1997-01-17 | 2001-08-01 | Seiko Epson Corp | Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment |
US6441487B2 (en) * | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
DE19927749A1 (de) * | 1999-06-17 | 2000-12-28 | Siemens Ag | Elektronische Anordnung mit flexiblen Kontaktierungsstellen |
JP3440070B2 (ja) | 2000-07-13 | 2003-08-25 | 沖電気工業株式会社 | ウェハー及びウェハーの製造方法 |
JP4394266B2 (ja) | 2000-09-18 | 2010-01-06 | カシオ計算機株式会社 | 半導体装置および半導体装置の製造方法 |
JP3943037B2 (ja) | 2003-01-21 | 2007-07-11 | シャープ株式会社 | 半導体装置の製造方法 |
-
2004
- 2004-06-14 US US10/866,189 patent/US7358608B2/en not_active Expired - Fee Related
- 2004-06-14 JP JP2004175097A patent/JP4045261B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050012210A1 (en) | 2005-01-20 |
JP2005026678A (ja) | 2005-01-27 |
US7358608B2 (en) | 2008-04-15 |
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