CN101185164B - 碳纳米管键合焊盘结构及其制造方法 - Google Patents

碳纳米管键合焊盘结构及其制造方法 Download PDF

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CN101185164B
CN101185164B CN2006800187971A CN200680018797A CN101185164B CN 101185164 B CN101185164 B CN 101185164B CN 2006800187971 A CN2006800187971 A CN 2006800187971A CN 200680018797 A CN200680018797 A CN 200680018797A CN 101185164 B CN101185164 B CN 101185164B
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conductive layer
integrated circuit
layer
carbon nano
bond pad
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CN101185164A (zh
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克里丝·怀兰德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种用于集成电路(IC)的键合焊盘结构(300)，使用碳纳米管以提高线键合(360)的强度和弹性。在示例实施例中，在IC衬底上有键合焊盘结构(300)，该键合焊盘结构包括：具有顶表面和底表面的第一导电层(310)，底表面附着于IC衬底上。在第一导电层(310)的顶表面上沉积电介质层(320)，该电介质层具有通路阵列(325)，通路阵列中填充有碳纳米管材料(325)，该碳纳米管材料(325)与第一导电层(310)电耦合。存在着具有顶表面和底表面的第二导电层(330)，该第二导电层的底表面与碳纳米管材料(325)电耦合。该实施例的特征也可以包括由碳纳米管材料组成的第一(410、510)或第二(430、530)导电层。

Description

碳纳米管键合焊盘结构及其制造方法
技术领域
本发明涉及集成电路(IC)封装。更具体地，本发明涉及半导体衬底到封装的线键合以及增强线键合和衬底键合焊盘界面的机械强度。
背景技术
电子工业继续依赖于半导体技术的进展以便在更紧凑的区域中实现更高功能的器件。对于许多应用，实现更高功能的器件要求将大量的电子器件集成到单个硅晶片中。由于每给定面积的硅晶片的电子器件的数量增加，制造工艺变得更为困难。
已经制造了各种半导体器件，在许多学科有着各种应用。这些基于硅的半导体器件常常包括金属氧化物半导体场效应晶体管(MOSFET)，如p沟道MOS(PMOS)、n沟道MOS(NMOS)和互补MOS(CMOS)晶体管，双极晶体管，BiCMOS晶体管。这种MOSFET器件包括导电栅极和硅之类的衬底之间的绝缘材料；因此，这些器件通常称作IGFET(绝缘栅FET)。
这些半导体器件中的每一个通常包括在其上形成多个有源器件的半导体衬底。在器件类型之间，给定有源器件的特定结构可以改变。例如，在MOS晶体管中，有源器件通常包括源区和漏区，以及调节源区和漏区之间的电流的栅电极。
并且，这种器件可以是按照多个晶片制造步骤生产的数字或模拟器件，例如CMOS、BiCOMS、双极等。衬底可以是硅、砷化镓(GaAs)或其它适合于在其上构造微电子电路的衬底。
在经过制造步骤之后，硅晶片具有预定数量的器件。测试这些器件。收集并封装好的器件。将器件键合成用户规定的封装。采用键合线实现至半导体管芯上的键合焊盘的连接，键合线又将管芯连接至外部封装管脚。
线键合是固相焊接工艺，其中使两部分金属材料(线和焊盘表面)紧密接触。一旦表面紧密接触，就发生电子共享或原子的互扩散，导致形成线键合。在线键合步骤中，结合力可导致材料变形，驱除沾污层并平滑表面的粗糙，这可以通过施加超声能量而增强。热可促进互扩散，从而促进键合形成。所形成的键合必须足够牢固，以抵抗在电路使用期间可能遇到的力。采用“键合拉力”测试仪，可以测量键合强度。这些表现出不足强度的键合可以采用此类设备筛选出来。表1描述了取决于键合线直径的特定拉力。
Figure G200680018797101D00021
参照图1A-1C。已经将键合线5从键合焊盘10上卸下。并且，包围材料15已经变形。
在线键合步骤期间，用于执行焊接所需的力可能超过键合焊盘和下面的结构的抗压强度。一种方法是在键合焊盘限定的金属区内形成电介质焊盘的阵列。在多层面金属器件中，这些是通路阵列，其中沉积层间金属以连接多层金属化物(metallization)。通路阵列是使得可以通过在接触孔中填充合适的导电材料而将一个或更多个导电层连接到另一个的、位于电介质层内的接触孔配置，通常是金属化物。
键合焊盘结构可以是图2所描述的一种。在示例三金属层面系统中，在第一金属化物170上，电介质层150限定有通路阵列160。这种电介质可以包括但不限于氧化硅、氮化硅、氧氮化硅、或其它的有机硅化合物。金属化物140可以沉积在这些通路160中，以及其上形成一层。在该导电层140上，可以沉积附加的电介质材料130，通路阵列120相对于通路阵列160稍稍错开。通常，在多层面金属系统中要求避免堆叠的通路。在通路阵列120中沉积金属化物110，并在其上形成一层。如果需要(未说明)，可以使用钝化层覆盖键合焊盘100中暴露的金属，以保护焊盘，并最终保护器件不受湿气和其它沾污影响。已经示出了这些通路阵列和在多个点处的金属化键合，以提高键合焊盘和与之键合的任何线的强度和弹性(resilience)。
需要增强键合焊盘结构的强度和弹性的技术，使得附着到上面的线可以具有更大的粘合力，从而减小断裂的线键合的可能性。
发明内容
已经发现本发明可用于增强集成电路器件上键合焊盘的强度和弹性。在键合焊盘的构造中，使用碳纳米管代替标准的金属化物。在示例实施例中，在集成电路(IC)结构上有键合焊盘结构，键合焊盘结构包括具有顶表面和底表面的第一导电层，底表面接触IC衬底。在第一导电层的顶表面上沉积电介质层，该电介质层具有通路阵列，通路阵列中填充有碳纳米管材料，碳纳米管材料与第一导电层电耦合。存在着沉积于电介质层之上且具有顶表面和底表面的第二导电层，第二导电层的底表面与碳纳米管材料电耦合。该实施例的特征包括含有碳纳米管材料的第一或第二导电层。
在另一个示例实施例中，在集成电路(IC)结构上有键合焊盘结构，键合焊盘结构包括具有顶表面和底表面的第一导电层，底表面接触IC衬底。在第一导电层的顶表面上沉积电介质层，该电介质层具有通路阵列，通路阵列中填充有碳纳米管材料，碳纳米管材料与第一导电层电耦合。存在着沉积于电介质层之上且具有顶表面和底表面的后续导电层，该后续导电层的底表面与碳纳米管材料电耦合。
在又一个示例实施例中，在集成电路(IC)结构上有键合焊盘结构，键合焊盘结构包括具有顶表面和底表面的第一导电层，底表面接触IC衬底。在一水平的或垂直的晶体取向上，碳纳米管层沉积在第一导电层的顶表面上。碳纳米管层具有通路阵列，该通路阵列填充有界面材料；碳纳米管材料与第一导电层电耦合。沉积于碳纳米管层之上且具有顶表面和底表面的后续导电层与碳纳米管材料电耦合。该实施例的特征在于界面材料可以包括选自以下材料的材料：电介质、金属化物、以及重掺杂硅。并且，电介质可以包括二氧化硅、富硅的氧化物、氧氮化硅、氮化硅、甲基倍半硅氧烷(methyl silseqioxane)(MSQ)和氢倍半硅氧烷(hydrogen silsequioxane)(HSQ)。此外，界面材料可以包括第一导电层、第二导电层、铝、铜、以及铜合金。碳纳米管层的预定晶体取向可以是垂直或水平的。
在又一个实施例中，存在着一种制造在集成电路(IC)衬底上的键合焊盘内具有碳纳米管结构的集成电路(IC)的方法。该方法包括，在IC上限定第一导电层，该导电层具有顶表面和底表面，底表面接触IC衬底。在电介质层上，限定通路区。在通路区中，形成碳纳米管，所述碳纳米管与第一导电层电耦合。后续导电层沉积于电介质层之上且具有顶表面和底表面，该后续导电层的底表面与碳纳米管材料电耦合。该实施例的特征包括第一导电层和含有金属化物的第二导电层。
在又一个实施例中，存在着一种制造在集成电路(IC)衬底上的键合焊盘内具有碳纳米管结构的集成电路(IC)的方法。该方法包括在IC上限定第一导电层，该导电层具有顶表面和底表面，底表面接触IC衬底。在第一导电层的顶表面上，沉积界面层。在界面层上限定通路区。在通路区中，形成碳纳米管，所述碳纳米管与第一导电层电耦合。限定沉积于纳米管之上且具有顶表面和底表面的后续导电层，该后续导电层的底表面与碳纳米管电耦合。该实施例的特征包括：界面层可以由以下材料的至少一种材料来沉积：电介质、金属、以及重掺杂硅。并且，电介质可以选自以下材料：二氧化硅、富硅的氧化物、氧氮化硅、以及氮化硅、甲基倍半硅氧烷(MSQ)和氢倍半硅氧烷(HSQ)。
对本发明的上述总结不希望表示每一个所公开的实施例，或者本发明的每一个方面。在附图中和随后的详细描述中提供其它方面和示例实施例。
附图说明
结合附图，考虑到以下对本发明的各种实施例的详细描述，可以更全面地理解本发明，附图中：
图1A-1C(现有技术)描述了键合线卸下时的示例键合焊盘结构；
图2(现有技术)描述了具有三个金属化层的示例传统键合结构；
图3A-3C描述了根据本发明的键合焊盘结构的示例实施例；
图4A按照顶视图和侧视图描述了键合焊盘结构的示例实施例，其中纳米管沿垂直方向取向，并由电介质包围；
图4B描述了键合焊盘结构侧面的示例实施例，其中纳米管沿垂直方向取向，并由导电材料包围；
图5按照顶视图和侧视图描述了键合焊盘结构的示例实施例，其中电介质材料被沿水平方向的纳米管包围；
图6是根据本发明的实施例构建包含碳纳米管的键合焊盘的步骤的流程图；以及
图7是根据本发明的实施例构建包含碳纳米管的键合焊盘的步骤的流程图。
具体实施方式
已经发现本发明在增强与半导体衬底上的键合焊盘键合的线的粘合力方面是有用的。代替键合焊盘结构中的金属化，使用碳纳米管。例如，对通路的金属化填充由碳纳米管代替。碳纳米管具有高强度，相对于铝大约69GPa的弹性模量，碳纳米管的弹性模量为大约1000GPa。并且，相对于铝124MPa的拉伸强度，碳纳米管的拉伸强度为大约170MPa。在电性方面，碳纳米管提供了足够的导电性以电耦合键合焊盘的多个金属层。
在根据本发明的示例实施例中，通常填充有金属的通路被填充碳纳米管材料。参照图3A。键合焊盘300具有三个金属化层310、330、350。在这些金属化层310、330、350之间夹着层间电介质层320、340。在这些层间电介质层320、340内是通路阵列325、345。这些通路阵列填充有碳纳米管材料。在最顶层的金属层350上，附加线键合360。注意，金属层的数量不必限制为三层。碳纳米管结构370可以被设想为导电层310、纳米管材料325、层间电介质320的复合物。现代的集成电路器件可以有四个、五个、六个或更多层。因此，键合焊盘可被构造为如给定工艺所需的那样，在每一个层间电介质通路阵列中有碳纳米管结构370。可以将CVD工艺用于采用碳纳米管材料填充通路325、345。在示例实施例中，取决于工艺要求，碳纳米管材料的晶体取向(即在结晶期间碳纳米管材料生长的方向)可以沿垂直或水平方向取向。在另一示例实施例中，纳米管材料的一部分可以垂直取向，而另一部分水平取向。
例如，电介质材料可以包括但不限于氧化硅、氧氮化硅、或氮化硅、或富硅的氧化物。其它的电介质可包括有机硅化合物。这可包括旋涂电介质，如甲基倍半硅氧烷(MSQ)和氢倍半硅氧烷(HSQ)。给定工艺的特定要求将决定最合适的电介质。
在另一个示例实施例中，取代图3A的标准金属化，键合焊盘400具有三个碳纳米管层410、430、450。参照图3B。在这些碳纳米管层410、430、450之间夹着层间电介质层420、440。在这些层间电介质层420、440内是通路阵列425、445。这些通路阵列填充有标准的金属化物。在最顶层的纳米管层450上，取代金属化，附加线键合460。碳纳米管结构470(如同在图3A中的情形下)可以被设想为碳纳米管层410、通路阵列425、以及层间电介质420的复合物。
在另一个示例实施例中，取代图3A的标准金属化，键合焊盘500具有三个碳纳米管层510、530、550。参照图3C。在这些碳纳米管层510、530、550之间夹着层间电介质层520、540。在这些层间电介质层520、540内是通路阵列525、545。这些通路阵列也填充有碳纳米管材料。因而，键合焊盘500的金属化物已经由碳纳米管材料代替。在最顶层的碳纳米管层550上，附加线键合560。碳纳米管结构570可以被设想为第一纳米管材料层510、通路阵列525、以及层间电介质520的复合物。
可以在集成电路器件的金属化步骤的处理中实现使用碳纳米管。例如，在对通路填充碳纳米管材料时，可以使用化学气相沉积(CVD)工艺。这种工艺将与标准的集成器件处理相交接(intermesh)。在Haase的标题为“Providing Electrical Conductivity Between and Active Regionand an Conductive Layer in a Semiconductor Device Using CarbonNanotubes”、2003年11月13日的美国专利申请公开(US2003/0211724A1)中可以找到背景信息，并且通过引用全文结合其全部内容。
参照图4A。在示例实施例中，键合焊盘包括三层。第一层是导电材料435。导电材料可以是铝或其合金、或铜和其合金，但不仅限于这些金属。其它导电材料可包括掺杂足以使硅导电的多晶硅材料。在第一层435上，可以沉积电介质层415。可以在该电介质层415中限定接触孔或通路425。通路425的深度使得有至导电材料435的入口。在这些通路425内形成纳米管材料。在本示例中，纳米管材料可以通过化学气相沉积(CVD)来形成。其它的技术包括等离子体增强化学气相沉积(PECVD)。取决于所包含的处理参数，纳米管材料的晶体取向可以是垂直的或者水平的。可以是第二或后续导电材料465耦合到纳米管材料。取决于在给定的工艺技术中使用的金属层数量，可以重复碳纳米管结构475(包括层435、425、415、465)。
参照图4B。对图4A的实施例进行修改。第一层是导电材料435a。在第一导电层435a上，取代电介质层415，可以沉积第二导电层415a。通路425a可以在电介质层415中限定。通路425a的深度使得有至导电材料435a的入口。在这些通路425a内形成纳米管材料445a。因而，纳米管材料445a由第二导电层415a包围。第二导电层415a可以是金属化物，类似于第一导电层435a。可以是第二或后续导电材料465a耦合到纳米管材料445。取决于在给定的工艺技术中使用的金属层数量，可以重复碳纳米管结构475a(包括层435a、425a、415a、465a)。
在键合焊盘处，碳纳米管可以相对于硅衬底沿多个方向取向。在其中施加向上的垂直力455、455a的前述示例键合焊盘结构中，相对于铝，对于完整的纳米管场(field of nanotubes)存在着减少大约36％的平均法向应力(normal stress)。对于50％铝和50％纳米管的垂直复合物，平均法向应力455a比仅用铝小46％。同样，对于50％SiO2和50％纳米管的垂直复合物，平均法向应力455比仅用铝小46％。
参照图5。在另一个示例实施例中，在导电材料535上，沉积纳米管材料515，使得其晶体取向是水平的。在该纳米管材料515上，限定通路525。在通路525中沉积电介质材料。在图5结构的变体中，取代电介质材料，可以在通路内沉积导电材料。可以是第二或后续导电材料555耦合到纳米管材料515。取决于在给定的工艺技术中使用的金属层数量，可以重复碳纳米管结构575(包括层515、525、535、555)。
在应用示例实施例中所述的本发明时，可以使用图6概括的示例工艺。在IC器件制造期间，可以结合附加的纳米管材料、在步骤600，在键合焊盘上限定IC器件上的导电层(步骤610)。在导电层上，形成电介质层(步骤620)。在电介质层上限定通路区，以提供从导电层至后续导电层的电连接(步骤630)。在通路区中形成纳米管(步骤640)。如果需要，可以限定另外的纳米管/电介质/导电层结构(步骤650)。这些结构的数量由在给定的IC器件设计中有多少金属层来决定。其范围可以是两个、三个、四个、或更多个金属层。
参照图7。在另一个示例工艺700中，限定导电层(步骤710)。在导电层上，限定纳米管层(步骤720)。在纳米管层上，限定纳米管通路区(步骤730)。然后，将电介质沉积在纳米管通路区中(步骤740)。如果需要，可以形成附加的结构(步骤750)。在该示例工艺的变体中，代替在纳米管通路区中沉积电介质，可以使用导电材料，通常是金属化物。
尽管已经参照几个特定的示例实施例描述了本发明，本领域的技术人员将认识到在不背离在以下权利要求中提出的本发明的精神和范围的情形下，可以进行许多更改。

Claims (14)

1.一种集成电路衬底上的键合焊盘结构(300)，该键合焊盘结构包括：具有顶表面和底表面的第一导电层(310)，该底表面附着于集成电路衬底上并与之接触；在第一导电层的顶表面上沉积的电介质层(320)，该电介质层具有通路阵列，通路阵列中的每一个填充有碳纳米管材料(325)，碳纳米管材料与第一导电层(310)电耦合；以及沉积于电介质层(320)之上且具有顶表面和底表面的第二导电层(330)，该第二导电层的底表面与该碳纳米管材料(325)电耦合。
2.如权利要求1所述的键合焊盘结构(500)，其中第一导电层包括碳纳米管材料(510)。
3.如权利要求1所述的键合焊盘结构(500)，其中第二导电层包括碳纳米管材料(530)。
4.如权利要求1所述的键合焊盘结构，其中第一导电层(310)是金属化物。
5.如权利要求1所述的键合焊盘结构，其中第二导电层(330)是金属化物。
6.一种集成电路衬底上的键合焊盘结构，该键合焊盘结构包括：具有顶表面和底表面的第一导电层(535)，该底表面接触集成电路衬底；在第一导电层(535)的顶表面上按照一水平的或一垂直的晶体取向沉积的碳纳米管层(515)，碳纳米管层(515)具有通路阵列(525)，通路阵列(525)填充有电介质(545)或导电材料，碳纳米管层(515)与第一导电层(535)电耦合；以及沉积于碳纳米管层(515)之上且具有顶表面和底表面的后续导电层(555)，该后续导电层(555)的底表面与碳纳米管层(515)电耦合。
7.如权利要求6所述的键合焊盘结构，其中第一导电层(535)和后续导电层(555)包括金属化物。
8.如权利要求6所述的键合焊盘结构，其中电介质(545)包括以下材料中的一种或多种：二氧化硅、富硅的氧化物、氧氮化硅、以及氮化硅、甲基倍半硅氧烷和氢倍半硅氧烷。
9.如权利要求6所述的键合焊盘结构，其中导电材料包括以下材料中的至少一种材料：铝、铝合金、铜、以及铜合金。
10.一种制造集成电路的方法，该集成电路在集成电路衬底上的键合焊盘内具有碳纳米管结构，所述方法包括：在集成电路上限定第一导电层，该导电层具有顶表面和底表面，底表面接触集成电路衬底；在第一导电层的顶表面上沉积电介质层；在电介质层上限定通路区；在通路区中形成碳纳米管，该碳纳米管与第一导电层电耦合；以及沉积于电介质层之上且限定具有顶表面和底表面的后续导电层，该后续导电层的底表面与碳纳米管电耦合。
11.如权利要求10所述的制造集成电路的方法，其中第一导电层和后续导电层包括金属化物。
12.一种制造集成电路的方法，该集成电路在集成电路衬底上的键合焊盘内具有碳纳米管结构，所述方法包括：在集成电路上限定第一导电层，该导电层具有顶表面和底表面，底表面接触集成电路衬底；在第一导电层的顶表面上沉积纳米管层；在纳米管层上限定通路区；在纳米管层中的通路区中沉积电介质或导电材料；以及沉积于纳米管层之上且限定具有顶表面和底表面的后续导电层，该后续导电层的底表面与碳纳米管电耦合。
13.如权利要求12所述的制造集成电路的方法，其中电介质选自以下材料：二氧化硅、富硅的氧化物、氧氮化硅、以及氮化硅、甲基倍半硅氧烷和氢倍半硅氧烷。
14.如权利要求12所述的制造集成电路的方法，其中导电材料包括以下材料中的至少一种材料：铝、铝合金、铜、以及铜合金。
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