CN100373609C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN100373609C CN100373609C CNB2004100297419A CN200410029741A CN100373609C CN 100373609 C CN100373609 C CN 100373609C CN B2004100297419 A CNB2004100297419 A CN B2004100297419A CN 200410029741 A CN200410029741 A CN 200410029741A CN 100373609 C CN100373609 C CN 100373609C
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- film
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- insulating film
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- semiconductor device
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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- B01D35/00—Filtering devices having features not specifically covered by groups B01D24/00 - B01D33/00, or for applications not specifically covered by groups B01D24/00 - B01D33/00; Auxiliary devices for filtration; Filter housing constructions
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/76846—Layer combinations
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/5329—Insulating materials
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (36)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP083348/2003 | 2003-03-25 | ||
JP2003083348A JP4454242B2 (ja) | 2003-03-25 | 2003-03-25 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
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CN1536660A CN1536660A (zh) | 2004-10-13 |
CN100373609C true CN100373609C (zh) | 2008-03-05 |
Family
ID=33398846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100297419A Expired - Lifetime CN100373609C (zh) | 2003-03-25 | 2004-03-24 | 半导体器件及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (13) | US7323781B2 (zh) |
JP (1) | JP4454242B2 (zh) |
KR (1) | KR101055451B1 (zh) |
CN (1) | CN100373609C (zh) |
TW (1) | TWI239592B (zh) |
Families Citing this family (84)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100352036C (zh) * | 2002-10-17 | 2007-11-28 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
JP4454242B2 (ja) | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US20050269709A1 (en) * | 2004-06-03 | 2005-12-08 | Agere Systems Inc. | Interconnect structure including tungsten nitride and a method of manufacture therefor |
JP4683865B2 (ja) * | 2004-06-15 | 2011-05-18 | 富士通セミコンダクター株式会社 | 半導体基板の製造方法 |
JP2006005190A (ja) * | 2004-06-18 | 2006-01-05 | Renesas Technology Corp | 半導体装置 |
US7166543B2 (en) * | 2004-08-30 | 2007-01-23 | Micron Technology, Inc. | Methods for forming an enriched metal oxide surface for use in a semiconductor device |
JP2006140404A (ja) * | 2004-11-15 | 2006-06-01 | Renesas Technology Corp | 半導体装置 |
JP2006202852A (ja) * | 2005-01-18 | 2006-08-03 | Toshiba Corp | 半導体装置 |
KR100641364B1 (ko) * | 2005-01-25 | 2006-10-31 | 삼성전자주식회사 | 스크라이브 라인들 및 그 형성방법들 |
JP4516447B2 (ja) * | 2005-02-24 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2006286878A (ja) * | 2005-03-31 | 2006-10-19 | Consortium For Advanced Semiconductor Materials & Related Technologies | 半導体装置製造方法 |
JP4655725B2 (ja) * | 2005-04-01 | 2011-03-23 | パナソニック株式会社 | 半導体装置の製造方法 |
KR100632620B1 (ko) * | 2005-04-22 | 2006-10-11 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조방법 |
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US20030008493A1 (en) * | 2001-07-03 | 2003-01-09 | Shyh-Dar Lee | Interconnect structure manufacturing |
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KR20040084668A (ko) | 2004-10-06 |
US20170200637A1 (en) | 2017-07-13 |
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TWI239592B (en) | 2005-09-11 |
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US20140312499A1 (en) | 2014-10-23 |
US20170011994A1 (en) | 2017-01-12 |
KR101055451B1 (ko) | 2011-08-08 |
US10304726B2 (en) | 2019-05-28 |
JP4454242B2 (ja) | 2010-04-21 |
US20090256261A1 (en) | 2009-10-15 |
US20150235962A1 (en) | 2015-08-20 |
US8053893B2 (en) | 2011-11-08 |
US8617981B2 (en) | 2013-12-31 |
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US9818639B2 (en) | 2017-11-14 |
US20190244855A1 (en) | 2019-08-08 |
US9490213B2 (en) | 2016-11-08 |
CN1536660A (zh) | 2004-10-13 |
US10121693B2 (en) | 2018-11-06 |
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