TWI752464B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI752464B
TWI752464B TW109112504A TW109112504A TWI752464B TW I752464 B TWI752464 B TW I752464B TW 109112504 A TW109112504 A TW 109112504A TW 109112504 A TW109112504 A TW 109112504A TW I752464 B TWI752464 B TW I752464B
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contact
dielectric layer
upper portion
semiconductor structure
etching
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TW202139390A (zh
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黃加欣
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華邦電子股份有限公司
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Abstract

提供一種半導體結構及其形成方法。上述半導體結構之形成方法包含：形成介電層於基底上；形成接觸件於介電層中；凹蝕介電層，使得接觸件的上部突出於介電層的上表面；以及蝕刻接觸件的上部，以減少接觸件的上部的尺寸。上述半導體結構包含基底、位於基底上且包括上部與下部的接觸件、位於接觸件的下部的側壁與底部上的襯層、以及圍繞接觸件的介電層。介電層直接接觸接觸件的上部的側壁。

Description

半導體結構及其形成方法
本發明是關於半導體結構，特別是關於接觸件及其形成方法。
半導體積體電路產業經歷快速成長。積體電路設計與材料的科技發展生產了數世代的積體電路，其中每個世代具備比上個世代更小及更複雜的電路。在積體電路發展的進程中，幾何尺寸逐漸縮小。
隨著半導體裝置尺寸的微縮，製造半導體元件的難度也大幅提升。特別是在半導體製程中，於接觸件上方形成導電層時，容易因為曝光不完全、晶圓上有翹曲(warpage)等等的情況，造成導電層偏移(shift)。也就是說，實際製程上導電層與接觸件對準失誤(misalignment)。此時，接觸件容易因為與鄰近的導電層距離過近而產生短路的問題。因此，仍需改善接觸件的形成製程，以避免短路問題。
本發明的一些實施例提供一種半導體結構的形成方法，包含：形成介電層於基底上；形成接觸件於介電層中；凹蝕介電層，使得接觸件的上部突出於介電層的上表面；以及蝕刻接觸件的上部，以減少接觸件的上部的尺寸。
本發明的一些實施例提供一種半導體結構，包含：基底；接觸件，位於該基底上且具有導電材料，其中接觸件包括上部與下部；襯層，位於接觸件的下部的側壁與底部上；以及介電層，圍繞接觸件，其中介電層直接接觸接觸件的上部的側壁。
由於在半導體製程中，於接觸件上方形成導電層時，容易因為曝光不完全、晶圓上有翹曲(warpage)等等的情況，造成導電層偏移(shift)。也就是說，實際製程上導電層與接觸件對準失誤(misalignment)。此時，接觸件容易因為與鄰近的導電層距離過近而產生短路的問題。
為解決上述問題，本發明實施例所提供的半導體結構之接觸件具有較小的頂部寬度，以提供較大的製程寬裕度(process window)，進而提升製程良率與確保半導體元件的性能。
第1-7與10-12圖是根據本發明的一些實施例，繪示出例示性半導體結構的剖面圖。
參照第1圖，形成介電層104於基底102上。在一些實施例中，介電層104可以用作前段製程的層間介電層(inter-layer dielectric layer，ILD)。在另一些實施例中，介電層104可以用作後段製程的金屬間介電層(inter-metal dielectric layer，IMD)。
在一些實施例中，介電層104可由一種或多種的介電材料形成，例如氮化矽、氮氧化矽、磷矽玻璃(phosphosilicate glass，PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、未摻雜的矽玻璃(Undoped Silicate Glass，USG)、四乙氧基矽烷(tetraethylorthosilicate，TEOS)、低介電常數介電材料、及/或其他適合的介電材料等等。
接著，繼續參照第1圖，形成圖案化遮罩106於介電層104上。接著，使用圖案化遮罩106作為蝕刻遮罩，執行蝕刻製程610以於介電層104中形成接觸孔120，並去除圖案化遮罩106，如第2圖所示。在上視圖中，接觸孔120為被介電層104圍繞的孔洞(未繪示)。在一些實施例中，蝕刻製程610可為非等向性蝕刻製程，其包含各種乾蝕刻製程。
接著，執行沉積製程620以順應性沉積襯層142於接觸孔120中以及介電層104上，如第3圖所示。在一些實施例中，襯層142可包括金屬、合金、金屬氮化物、其他導電材料或上述之組合。具體而言，襯層142可包含鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、適合的材料或其組合等等。
接著，執行沉積製程630以沉積導電材料144於接觸孔120中以及介電層104上，如第4圖所示。詳細而言，導電材料144沉積於襯層142上。在一些實施例中，導電材料144可包含金屬，例如，鎢、鋁、銅、金、銀、其他合適的金屬材料或上述之組合等等。
由於在沉積導電材料144於基底102上的情況下容易產生過高的阻值，甚至容易產生小爆炸的現象，因此在一些實施例中，藉由在導電材料144與基底102之間形成襯層142，可防止導電材料144與基底102直接接觸，以避免阻值增加而造成產率降低。另一方面，藉由於導電材料144與介電層104之間形成襯層142，可防止導電材料144向介電層104擴散。
接著，執行平坦化製程640以去除接觸孔以外的導電材料144，留下接觸孔中的導電材料144作為接觸件140，如第5圖所示。詳細而言，上述平坦化製程640包含去除於介電層104上的襯層142與導電材料144，使得接觸件140的上表面與介電層104齊平。在一實施例中，平坦化製程640包含化學機械研磨(Chemical Mechanical Polishing，CMP)。
接著，執行蝕刻製程650以凹蝕介電層104，使得接觸件140的上部140U突出於介電層104的上表面，如第6圖所示。在此實施例中，蝕刻製程650類似於蝕刻製程610，因此在此不再贅述。應注意的是，在此，以介電層104之上表面上為接觸件140的上部140U，而介電層104之上表面下為接觸件140的下部。
接著，執行蝕刻製程660以蝕刻接觸件140的上部140U，進而減少接觸件140的上部140U的尺寸，而形成所需的接觸件150，如第7圖所示。在一些實施例中，蝕刻製程660包含等向性蝕刻。前述等向性蝕刻包括濕蝕刻、乾蝕刻、其他適合的蝕刻製程或其組合等等。在一些實施例中，蝕刻接觸件140的上部140U包含蝕刻接觸件140的上部140U的側壁與頂面，以等量地(equally)減少上部140U的高度與兩側的寬度，而形成接觸件150的上部150U。在一些實施例中，蝕刻製程660包含蝕刻接觸件140的上部140U的襯層142與部分的導電材料144。
第8與9圖是根據本發明的一些實施例，繪示出半導體結構100中的接觸件150的部分放大剖面圖。在此，接觸件150的下部的側壁具有襯層142而上部側壁不具有襯層142。在此實施例中，上部與下部皆朝向基底102的方向逐漸變窄(taper)。應注意的是，等向性蝕刻前的接觸件140的上部輪廓以虛線表示，等向性蝕刻後的的接觸件140(或接觸件150)的上部輪廓以實線表示，以表示縮小尺寸前後的相對關係。另外，為使圖示更為簡潔，在第8與9圖中的導電材料144與襯層142的圖樣不同於第1-7與10-12圖中的導電材料144。
在第8圖的實施例中，接觸件140的上部的側壁各減少寬度W S以及上部的頂面減少高度H S，而形成接觸件150。在此實施例中，減少的寬度W S與減少的高度H S大抵相同。舉例來說，減少的寬度W S為10nm，減少的高度H S在9-11nm之間。也就是說，大抵相同可包括±10%內的誤差在第8圖的實施例中，接觸件150的上部具有頂部寬度W UT(後續稱之為頂寬)與底部寬度W UB(後續稱之為底寬)，而接觸件150的下部具有頂部寬度W LT(後續稱之為頂寬)。在此實施例中，接觸件150的上部朝向基底102的方向逐漸變窄(taper)，因此可觀察到接觸件150的上部的頂寬W UT大於接觸件150的上部的底寬W UB。另一方面，減少接觸件150的上部的頂寬W UT所使用的蝕刻製程660，亦同時減少接觸件150的上部的底寬W UB，因此可觀察到接觸件150的上部的底寬W UB小於接觸件150的上部的頂寬W UT。也就是說，接觸件150的上部的側壁與下部的側壁藉由接觸件150的下部的頂面連接。
在一些實施例中，接觸件150的上部的側壁與下部的側壁大致上平行。舉例來說，接觸件150的下部的側壁與基底102之夾角為70°，接觸件150的上部的側壁與基底之夾角在67°-73°之間。也就是說，大致上平行可包括±5%內的誤差。
在一些實施例中，接觸件150的上部的側壁與上部的頂面之間之夾角θ大約介於60°-90°。由於製程影響，接觸件150由遠離基底102處往靠近基底102處逐漸變窄，因此接觸件的上部的側壁與上部的頂面之間的夾角θ一般小於90°。另一方面，如果夾角θ小於60°容易產生較大的頂寬，進而減少製程寬裕度。
在一些實施例中，接觸件140的上部所減少的總寬度2W S佔接觸件140的上部的原始總寬度W UT+2W S之比例不大於50%。上述比例大於50%時，由於與後續導電層之接觸面積變小，因此接觸電阻容易增加，進而降低半導體結構之效能。
在第8圖的實施例中，接觸件150的上部的頂寬W UT大於接觸件150的下部的頂寬W LT。然而，接觸件150的上部的頂寬W UT可以依據需求任意作改變，並不以此為限。
第9圖所示的接觸件150大致上與第8圖所示的接觸件150相似，其差異在於接觸件150的上部的頂寬W LT與下部的頂寬W UT之關係不同。在此實施例中，接觸件150的上部的頂寬W UT小於接觸件150的下部的頂寬W LT。然而，接觸件150的上部的頂寬W UT可以依據需求任意作改變，並不以此為限。
接著，回到第7圖。執行沉積製程670以沉積介電層104於基底上102的介電層104上與接觸件150上，如第10圖所示。由於沉積製程670與沉積製程630相似，因此在此不再贅述。
接著，執行平坦化製程680以去除接觸件上150的介電層104，如第11圖所示。由於平坦化製程680與平坦化製程640相似，因此在此不再贅述。
在一些實施例中，由於接觸件150的上部的側壁的襯層142已完全被蝕刻掉，因此接觸件150的上部的側壁直接接觸介電層104，且接觸件150的下部的頂部部分亦直接接觸介電層104。
接著，形成導電層160於接觸件150上，如第12圖所示。而第12圖的上視圖則如第13圖所示。用以形成導電層160的材料與沉積製程可類似於上述導電材料144與上述沉積製程630，因此在此不再贅述。在此實施例中，導電材料經沉積後，經過微影製程與蝕刻製程可形成第12圖中的導電層160。在另一實施例中，導電層160也可藉由鑲嵌(damascene)製程形成(未繪示)。
在第12圖的實施例中，導電層160位於接觸件150的正上方。在第13圖中，虛線處表示接觸件150與導電層160的接觸部分，也就是接觸件150的最頂表面。在第13圖的實施例中，接觸件150與導電層160的兩側的距離皆相同。
於習知技術中所形成的接觸件，在平坦化製程中容易對接觸件的上表面產生較大的刮傷(scratch)。相較之下，在本發明實施例中額外使用蝕刻製程650凹蝕介電層104以及蝕刻製程660蝕刻接觸件140的上部，可蝕刻掉平坦化接觸件140的過程中所產生的刮傷，以提升良率及可靠度。
再者，如果為了形成較小的頂部寬度的接觸件，而直接形成較小接觸孔，則容易在沉積導電材料時產生氣隙(seam)。相較之下，本發明實施例藉由先形成較大頂部寬度的接觸件，再藉由等向性蝕刻等製程減少接觸件的頂部寬度，可在不易產生氣隙的情況下，減少接觸件的頂部寬度，以增加製程寬裕度。
另外，現有技術中通常在形成接觸孔的蝕刻製程之後亦會使用單一或多步驟清洗製程(未繪示)，容易進一步增加接觸孔的頂部寬度，進而導致前文所述的短路問題。在本發明實施例中，即使在蝕刻製程之後使用清洗製程，而產生接觸孔的頂部寬度比預期大的情況，仍可形成具有較小的頂部寬度的接觸件，進而減少短路的可能性。
第14與15圖是根據本發明的一些實施例，繪示出例示性半導體結構的剖面圖與對應於此的上視圖。第14圖中的半導體結構200與第12圖中的半導體結構100的差異在於導體層160並非位於接觸件150的正上方。在一些實施例中，導體層160之中線與接觸件150之中線具有一距離。在第15圖中，接觸件150與導體層160的兩側距離不同。而在先前技術中，接觸件150將更靠近鄰近的導電層160，因此更容易造成短路。但在本發明實施例中的接觸件150減少了頂部寬度，因此與鄰近的導電層160的距離增加，不易短路。
第16圖是根據本發明的另一些實施例，繪示出例示性半導體結構的剖面圖。第16圖中的半導體結構300與第12圖中的半導體結構100的差異在於在襯層142與介電層104上形成具有不同於介電層104材料的介電層105。在此實施例中，介電層104與接觸件150的下部齊平，也就是說，介電層104與襯層142以及部分的導電材料144齊平。另一方面，介電層105與接觸件150的上部齊平，也就是說，介電層105與接觸件150的最頂表面齊平。介電層105可使用與介電層104類似但不同的材料，在此不再贅述。可依據製程所需任意選擇及置換介電層104與105之材料。
第17圖是根據本發明的其他實施例，繪示出例示性半導體結構的剖面圖。第17圖中的半導體結構400為應用接觸件150於半導體結構中的示例。在前段製程的實施例中，接觸件150可作為源極/汲極接觸插塞(contact plug)，形成於源極/汲極108與導電層160之間。或者，接觸件150可作為閘極接觸插塞，形成於閘極170與導電層160之間。在後段製程的實施例中，接觸件150可作為垂直電性連接的導孔(via)，形成於導電層160與導電層160之間。
綜上所述，本發明實施例提供一種半導體結構及其形成方法，特別是具有較小頂部尺寸的接觸件，其不但增加了製程寬裕度，還可改善良率及可靠度。
100/200/300/400 ~ 半導體結構 102 ~ 基底 104/105 ~ 介電層 106 ~ 圖案化遮罩 108 ~ 源極/汲極 120 ~ 接觸孔 140 ~ 接觸件 142 ~ 襯層 144 ~ 導電材料 150 ~ 接觸件 160 ~ 導電層 170 ~ 閘極 610 ~ 蝕刻製程 620 ~ 沉積製程 630 ~ 沉積製程 640 ~ 平坦化製程 650 ~ 蝕刻製程 660 ~ 蝕刻製程 670 ~ 沉積製程 680 ~ 平坦化製程 W UT~ (上部的)頂部寬度/頂寬 W UB~ (上部的)底部寬度/底寬 W LT~ (下部的)頂部寬度/頂寬 W S~ 減少的寬度 H S~ 減少的高度 θ ~ 角度
以下將配合所附圖式詳述本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本發明實施例的特徵。 第1-7圖是根據本發明的一些實施例，繪示出例示性半導體結構的剖面圖。 第8與9圖是根據本發明的一些實施例，繪示出例示性半導體結構的部分放大剖面圖。 第10-12圖是根據本發明的一些實施例，繪示出例示性半導體結構的剖面圖。 第13圖是根據本發明的一些實施例，繪示出對應於第12圖所示之半導體結構的上視圖。 第14圖是根據本發明的一些實施例，繪示出例示性半導體結構的剖面圖。 第15圖是根據本發明的一些實施例，繪示出對應於第14圖所示之半導體結構的上視圖。 第16圖是根據本發明的一些實施例，繪示出例示性半導體結構的剖面圖。 第17圖是根據本發明的其他實施例，繪示出例示性半導體結構的剖面圖。
100 ~ 半導體結構 102 ~ 基底 104 ~ 介電層 142 ~ 襯層 144 ~ 導電材料 150 ~ 接觸件 160 ~ 導電層

Claims (9)

  1. 一種半導體結構的形成方法，包括：形成一介電層於一基底上；形成一接觸件於該介電層中；凹蝕該介電層，使得該接觸件的一上部突出於該介電層的上表面；以及蝕刻該接觸件的該上部，以減少該接觸件的該上部的尺寸，其中該接觸件的一下部的頂寬大於該接觸件的該上部的底寬。
  2. 如申請專利範圍第1項所述之半導體結構的形成方法，其中蝕刻該接觸件的該上部的步驟包括等向性蝕刻該接觸件的該上部。
  3. 如申請專利範圍第2項所述之半導體結構的形成方法，其中蝕刻該接觸件的該上部的步驟包括等向性蝕刻該接觸件的該上部的側壁與頂面，以等量地(equally)減少該上部的高度與寬度。
  4. 一種半導體結構，包括：一基底；一接觸件，位於該基底上，其中該接觸件包括一上部與一下部；一襯層，位於該接觸件的該下部的側壁與底部上；以及一介電層，圍繞該接觸件，其中該介電層直接接觸該接觸件的該上部的側壁，其中該接觸件的該下部的頂寬大於該接觸件的該上部的底寬。
  5. 如申請專利範圍第4項所述之半導體結構，其中該接觸件的該上部的頂寬等於或小於該接觸件的該下部的頂寬。
  6. 如申請專利範圍第4項所述之半導體結構，其中該接觸件的該下部的頂部部分直接接觸該介電層。
  7. 如申請專利範圍第4項所述之半導體結構，其中該介電層包括：一第一介電層，與該接觸件的該下部齊平；以及一第二介電層，與該接觸件的該上部齊平。
  8. 如申請專利範圍第4項所述之半導體結構，其中該上部與該下部皆朝向該基底的一方向逐漸變窄(taper)。
  9. 如申請專利範圍第4項所述之半導體結構，其中該上部的側壁與該下部的側壁大致上平行。
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