US20030155657A1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- US20030155657A1 US20030155657A1 US10/365,437 US36543703A US2003155657A1 US 20030155657 A1 US20030155657 A1 US 20030155657A1 US 36543703 A US36543703 A US 36543703A US 2003155657 A1 US2003155657 A1 US 2003155657A1
- Authority
- US
- United States
- Prior art keywords
- film
- semiconductor device
- plasma treatment
- gas
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 238000009413 insulation Methods 0.000 claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 claims abstract description 110
- 239000002184 metal Substances 0.000 claims abstract description 110
- 238000009832 plasma treatment Methods 0.000 claims abstract description 104
- 230000004888 barrier function Effects 0.000 claims abstract description 101
- 239000007789 gas Substances 0.000 claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 64
- 239000000470 constituent Substances 0.000 claims abstract description 47
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims abstract description 39
- 239000001257 hydrogen Substances 0.000 claims abstract description 24
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims description 101
- 238000005530 etching Methods 0.000 claims description 63
- 239000010410 layer Substances 0.000 claims description 56
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 35
- 238000004544 sputter deposition Methods 0.000 claims description 30
- 238000000151 deposition Methods 0.000 claims description 25
- 125000004429 atom Chemical group 0.000 claims description 24
- 229910052756 noble gas Inorganic materials 0.000 claims description 23
- 238000011065 in-situ storage Methods 0.000 claims description 22
- 150000002431 hydrogen Chemical class 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 14
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims description 14
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 14
- 229910052734 helium Inorganic materials 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 12
- 229910052786 argon Inorganic materials 0.000 claims description 11
- 229910052715 tantalum Inorganic materials 0.000 claims description 10
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052743 krypton Inorganic materials 0.000 claims description 8
- 229910052754 neon Inorganic materials 0.000 claims description 8
- 229910052704 radon Inorganic materials 0.000 claims description 8
- 229910052724 xenon Inorganic materials 0.000 claims description 8
- 244000025254 Cannabis sativa Species 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 125000000962 organic group Chemical group 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- GPTXWRGISTZRIO-UHFFFAOYSA-N chlorquinaldol Chemical compound ClC1=CC(Cl)=C(O)C2=NC(C)=CC=C21 GPTXWRGISTZRIO-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 107
- 238000000926 separation method Methods 0.000 abstract description 16
- 125000004435 hydrogen atom Chemical class [H]* 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 266
- 230000008569 process Effects 0.000 description 74
- 238000001312 dry etching Methods 0.000 description 25
- 238000011282 treatment Methods 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 230000009977 dual effect Effects 0.000 description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 12
- 238000007747 plating Methods 0.000 description 12
- 238000004140 cleaning Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 10
- 238000011161 development Methods 0.000 description 10
- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
- 238000004380 ashing Methods 0.000 description 8
- 239000007788 liquid Substances 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 7
- 229910052681 coesite Inorganic materials 0.000 description 7
- 229910052906 cristobalite Inorganic materials 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 229910010272 inorganic material Inorganic materials 0.000 description 7
- 239000011147 inorganic material Substances 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 239000002356 single layer Substances 0.000 description 7
- 229910052682 stishovite Inorganic materials 0.000 description 7
- 229910052905 tridymite Inorganic materials 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000003475 lamination Methods 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000002407 reforming Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000000576 coating method Methods 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 229910004541 SiN Inorganic materials 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 125000001165 hydrophobic group Chemical group 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229920002472 Starch Polymers 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 235000019698 starch Nutrition 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a structure of a semiconductor device and a manufacturing method thereof, and more particularly to, in a damascene process using a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, an interface: structure of a barrier metal and the low dielectric film and a surface treatment method thereof.
- a so-called damascene process is generally performed, by which an interconnect is formed by embedding Cu in both a via hole and a wiring trench pattern concurrently followed by planarization through the CMP (Chemical Mechanical Polishing) method.
- the damascene process can increase density of wiring patterns; however, when the wiring patterns are formed too close, a parasitic capacitance between the wiring patterns causes problematic interconnect delay. Hence, a reduction in interconnect capacitance becomes an issue of great importance to improve the interconnect delay.
- FIG. 1A through FIG. 3B are cross sections showing the step-by-step sequence of a via first process, which is one embodiment of the conventional damascene process.
- HSQ hydrogen silsesquioxane
- MSQ methyl silsesquioxane
- the first reflection preventing film 11 a , the second interlayer insulation film 18 , the second etching stopper film 9 , and the first interlayer insulation film 8 are etched away sequentially through a known dry etching technique, using the first resist pattern 12 a as a mask. A via hole 3 penetrating through these films is thereby formed.
- a second reflection preventing film 11 b is formed and then photoresist is applied thereon, which is subjected to exposure and development.
- a second resist pattern 12 b to be used to form a wiring trench pattern through etching is thereby formed.
- the second reflection preventing film 11 b and the second interlayer insulation film 18 are etched away sequentially through a known dry etching technique, and a wiring trench pattern 13 is thereby formed (see FIG. 2A).
- the first etching stopper film 7 atop the lower layer wiring 6 is removed, after which, as shown in FIG. 2C, a barrier metal 4 to be used as a base layer for a wiring material is formed.
- a wiring material 5 such as Cu, is embedded in the interiors of the wiring trench pattern 13 and the via hole 3 , and the surface thereof is planarized through CMP (see FIG. 3A and FIG. 3B). A dual damascene structure is thus obtained.
- the second interlayer insulation film 18 when a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, is used as the second interlayer insulation film 18 , it does not adhere well to an inorganic material, particularly, a barrier metal, and as shown in FIG. 3B, the barrier metal is separated from an MSQ-based low dielectric film during CMP, which gives rise to a problematic scratch 21 on the surface of the MSQ-based low dielectric film, or stress caused by the multi-level interconnection gives rise to problematic film separation 20 at the barrier metal/MSQ interface having poor adhesion.
- a barrier metal is separated from an MSQ-based low dielectric film during CMP, which gives rise to a problematic scratch 21 on the surface of the MSQ-based low dielectric film, or stress caused by the multi-level interconnection gives rise to problematic film separation 20 at the barrier metal/MSQ interface having poor adhesion.
- the MSQ-based low dielectric film has a lower dielectric constant than HSQ, and is therefore expected as a promising next-generation interlayer film, which increases the importance of solving the adhesion problem at the interface between the MSQ-based low dielectric film and the barrier metal.
- HSQ has a structure in which oxygen and hydrogen are bonded to silicon atoms
- MSQ contains organic constituents having a large molecular structure, such as a methyl group, in order to lower a dielectric constant, and the organic constituents at the MSQ interface interfere with bonding of Si and the barrier metal 4 , such as tantalum (Ta) and tantalum nitride (TaN).
- Japanese Patent Laid-Open Publication No. Hei. 10-284600 discloses a method of protecting the sidewall by providing a Si 3 N 4 :or SiO 2 sidewall to a groove pattern formed in the low dielectric interlayer film. This method, however, cannot avoid an increase in dielectric constant when a thick film is formed, and deterioration in adhesion associated with a pin-hole when a thin film is formed.
- Japanese Patent Laid-Open Publication No. 2001-223269 discloses a method of reforming the surface of the interlayer insulation film to be a silicon oxide film or a silicon dioxide film containing excessive silicon through irradiation of a charged beam of an ionized oxygen gas.
- This method has a problem that water comes into the film and a dielectric constant of the insulation film is increased; moreover, the surface of the film is made rough and a residue is left thereon.
- This problem is not limited to the via first dual damascene process described above, and can occur in any other damascene process, such as a dual hard mask process and a single damascene process, as well as in any other process using a low dielectric film having a bond of Si and a group made of organic constituents.
- An object of the present invention is to provide a semiconductor device capable of improving adhesion of a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, to a barrier metal at the interface in a damascene process and a manufacturing method thereof.
- the object is to provide a structure of a semiconductor device capable of improving adhesion of the low dielectric interlayer film to an inorganic material, such as the barrier metal, by removing the organic constituents at the barrier metal/film interface, and a manufacturing method of the semiconductor device.
- a semiconductor device comprises an insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, and a wiring material embedded, through a barrier metal, in one of a via hole and a wiring groove formed in said insulation layer.
- a layer is formed between the low dielectric film and the barrier metal and has a relatively low concentration of organic constituents in comparison with the low dielectric film.
- a concentration of carbon (C) of the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film is 7 atom % or below.
- a concentration of carbon (C) of the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film is 7 atom % or below and 2 atom % or above.
- the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film has a film thickness of 25 nm or less.
- the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film has a Si—H bond.
- the low dielectric film is one of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of each.
- MSQ methyl silsesquioxane
- MHSQ methylated hydrogen silsesquioxane
- SiC silicon carbide
- SiOC or SiCOH silicon oxycarbide or carbon-doped glass
- OSG organo sillicated grass
- SiCN silicon carbonitride
- the barrier metal is made of tantalum nitride (TaN) on a side of the low dielectric film and tantalum (Ta) on a side of the wiring material.
- a manufacturing method of a semiconductor device of the invention in a manufacturing method of a semiconductor device including a step of embedding, through a barrier metal, a wiring material in one of a via hole and a wiring groove formed in an insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, a plasma treatment is performed before the barrier metal is deposited, using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of the low dielectric film with hydrogen, and a gas capable of decomposing at least part. of the group made of organic constituents to form a dangling bond.
- a manufacturing method of a semiconductor device of the invention in a manufacturing method of a semiconductor device including the steps of: forming at least a first interlayer insulation film and a second interlayer insulation film sequentially on a substrate in which a wiring pattern has been formed; forming a via hole penetrating through the first interlayer insulation film and the second interlayer insulation film using a first resist pattern formed on the second interlayer insulation film; removing the first resist pattern and then forming a trench pattern through etching of the second interlayer insulation film using a second resist pattern formed on the second interlayer insulation film; depositing a barrier metal on the second interlayer insulation film and on inner walls of the via hole and the trench pattern; depositing a wiring material and then embedding the wiring material in interiors of the via hole and the trench pattern; and removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, at least one of the first interlayer insulation film and the second interlayer insulation film is a low dielectric film having a bond of Si
- a manufacturing method of a semiconductor device of the invention in a manufacturing method of a semiconductor device including the steps of: depositing at least a first interlayer insulation film, a second interlayer insulation film, and a hard mask material on a substrate in which a wiring pattern has been formed; forming a hard mask through etching of the hard mask material using a first resist pattern formed on the hard mask material; forming a via hole penetrating through the first interlayer insulation film and the second interlayer insulation film using a second resist pattern formed on the hard mask; removing the second resist pattern and then forming a trench pattern through etching of the second interlayer insulation film using the hard mask; depositing a barrier metal on the second interlayer insulation film and on inner walls of the via hole and the trench pattern; depositing a wiring material and then embedding the wiring material in interiors of the via hole and the trench pattern; and removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, at least one of the first interlayer insulation film
- the invention can be arranged in such a manner that the plasma treatment and the deposition of the barrier metal are performed under one of in situ and in vacuo conditions, or that the method further includes a step of performing sputtering using an Ar gas prior to the plasma treatment, and the Ar sputtering, the plasma treatment, and the depositing of the barrier metal are performed under one of in situ and in vacuo conditions.
- the low dielectric film is one of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG); silicon carbonitride (SiCN), and a porous film of each.
- MSQ methyl silsesquioxane
- MHSQ methylated hydrogen silsesquioxane
- SiC silicon carbide
- SiOC or SiCOH carbon-doped glass
- OSG organo sillicated grass
- SiCN silicon carbonitride
- the invention is preferably arranged in such a manner that a mixed gas of hydrogen and a noble gas is used as a gas for the plasma treatment, or that a noble gas is used as a gas for the plasma treatment and RF bias is applied during the plasma treatment.
- the noble gas includes one of He, Ne, Ar, Kr, Xe, and Rn.
- the invention is preferably arranged in such a manner that, in a case where He is used as the gas for the plasma treatment, power of the RF bias is set to a range from 250 W to 400 W both inclusive.
- the plasma treatment is performed using a mixed gas of H 2 and He, a He gas, etc. as a pre-step of depositing the barrier metal after the trench pattern or the via hole is formed in the insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ.
- a mixed gas of H 2 and He, a He gas, etc. as a pre-step of depositing the barrier metal after the trench pattern or the via hole is formed in the insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ.
- FIG. 1A through FIG. 1C are cross sections showing the step-by-step sequence of a conventional via first process
- FIG. 2A through FIG. 2C are cross sections showing the step-by-step sequence of the conventional via first process
- FIG. 3A and FIG. 3B are cross sections showing the step-by-step sequence of the conventional via first process
- FIG. 4A and FIG. 4B are views schematically showing the mechanism of a plasma treatment of the invention.
- FIG. 5A through FIG. 5C are cross sections showing a part of the fabrication sequence including the plasma treatment of the invention.
- FIG. 6A through FIG. 6C are cross sections showing a part of the fabrication sequence including a structure and the plasma treatment of the invention.
- FIG. 7A through FIG. 7C are cross sections showing the step-by-step sequence of a via first process according to a first example of the invention.
- FIG. 8A through FIG. 8C are cross sections showing the step-by-step sequence of the via first process according to the first example of the invention.
- FIG. 9A through FIG. 9C are cross sections showing the step-by-step sequence of the via first process according to the first example of the invention.
- FIG. 10A through FIG. 10C are cross sections showing the step-by-step sequence of a dual hard mask process according to a second example of the invention.
- FIG. 11A through FIG. 11C are cross sections showing the step-by-step sequence of the dual hard mask process according to the second example of the invention.
- FIG. 12A through FIG. 12C are cross sections showing the step-by-step sequence of the dual hard mask process according to the second example of the invention.
- FIG. 13A and FIG. 13B are cross sections showing the step-by-step sequence of the dual hard mask process according to the second example of the invention.
- FIG. 14A through FIG. 14C are cross sections showing the step-by-step sequence of a single damascene process according to a third example of the invention.
- FIG. 15A through FIG. 15C are cross sections showing the step-by-step sequence of the single damascene process according to the third example of the invention.
- FIG. 16A and FIG. 16B are cross sections showing the step-by-step sequence of the single damascene process according to the third example of the invention.
- FIG. 17A through FIG. 17C are cross sections showing the step-by-step sequence of the single damascene process according to the third example of the invention.
- FIG. 18A through FIG. 18C are cross sections showing the step-by-step sequence of a single damascene process according to a fourth example of the invention.
- FIG. 19A through FIG. 19C are cross sections showing the step-by-step sequence of the single damascene process according to the fourth example of the invention.
- FIG. 20A and FIG. 20B are cross sections showing the step-by-step sequence of the single damascene process according to the fourth example of the invention.
- FIG. 21A through FIG. 21C are cross sections showing the step-by-step sequence of the single damascene process according to the fourth example of the invention.
- samples were manufactured by depositing tantalum (Ta), a tantalum nitride (TaN) layer, and a Cu layer as a barrier metal on an MSQ film through sputtering.
- the film structure was Cu 100 nm/Ta 15 nm/TaN 15 nm/MSQ 300 nm. More specifically, after the MSQ film was subjected to cleaning process described below in a pre-cleaning chamber, Ta and a TaN layer were deposited in a PVD chamber for a barrier metal, and then a Cu layer was deposited in a PVD chamber for Cu. The wafer was transported from chamber to chamber in vacuo (a range of 10 ⁇ 7 torr or less) to prevent contamination on the MSQ surface.
- Table 1 reveals that adhesion at the barrier metal/MSQ interface was unsatisfactory in the process performing Ar etching alone and the process performing the He plasma treatment after Ar etching, and the barrier metal layer and the Cu layer were separated from MSQ film at the barrier metal/MSQ interface in all the samples; however, adhesion at the barrier metal/MSQ interface was improved in the process of performing the He/H 2 plasma treatment after Ar etching, and no separation occurred. It is understood from the result that the plasma treatment using a gas containing H 2 is effective in improving adhesion of MSQ.
- Table 3 above reveals that, although a difference between these processes was not clear in the tape test, the angle of contact was reduced slightly in the process of performing the He plasma treatment (no RF bias) after Ar etching in comparison with the process of performing Ar etching alone, from which it is understood that the He plasma treatment itself is effective in improving adhesion. Also, the angle of contact was further reduced in the process of performing the He/H 2 plasma treatment after Ar etching, from which it is understood that a H 2 gas is highly effective in reforming the surface. In addition, Table 4 above reveals that the angle of. contact was gradually reduced with application of .RF bias even in the He plasma treatment, and in particular, when RF bias of 250 W or above was applied, the surface reforming effect was higher than that attained in the He/H 2 plasma treatment.
- the effect achieved by the plasma treatment will now be explained with reference to FIG. 4A and FIG. 4B.
- the non-treated MSQ surface is covered with methyl groups, and for example, by exposing the MSQ surface to H 2 plasma, a Si—CH 3 bond on the MSQ surface is replaced by a Si—H bond as shown in FIG. 4A.
- a Si—CH 3 bond on the MSQ surface is replaced by a Si—H bond as shown in FIG. 4A.
- a Si—CH 3 bond on the MSQ surface is broken to form a dangling bond as RF bias is increased, and the bonding strength between Si and the barrier metal is thus improved.
- a mixed gas containing a highly reactive gas capable of replacing a methyl group with a group having a small molecular structure, such as hydrogen, or a gas capable of decomposing only a methyl group covering the surface without decomposing a MSQ molecule as a whole Besides He and He/H 2 , a mixed gas of H 2 and a noble gas, such as Ne, Ar, Kr, Xe, and Rn, a gas containing ammonia, etc. can be used.
- RF bias may be applied in the He/H 2 plasma treatment.
- hydrogen atoms penetrate into the interior of a substance exposed to plasma, and in particular, in a case where Cu used as a wiring material is exposed, there occurs a problem that Cu becomes brittle.
- RF bias needs to be optimized when a hydrogen gas is used.
- a component ratio of a H 2 gas and a noble gas when a ratio of a H 2 gas is increased, the reactivity becomes too high to remain controllable, and there is the possibility that a replacement-reaction of methyl groups takes place not only on the surface layer, but also in the interior, which undesirably increases a dielectric constant of MSQ.
- it is preferable to set a component ratio such that a few percent of a highly reactive gas, such as H 2 , is contained (in the case of H 2 and He, H 2 is 1 to 10% and He is 99 to 90%, for example, H 2 and He 4% and 96%).
- ammonia gas may be a possible choice when the ability to react with a methyl group is considered.
- Cu used as a wiring material undergoes nitridation with ammonia, and an adverse effect on the reliability of interconnections is concerned. For this reason, the concentration of ammonia, RF bias, a processing time, etc. need to be optimized.
- a material capable of improving adhesion through the plasma treatment using the above-specified gases can be any material containing organic constituents or any material containing a group having a large molecular structure.
- the material can be methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), etc., or a porous film of each.
- these films can be formed through any method, and an arbitrary method, such as the CVD method and the coating method, can be used.
- FIG. 5A through FIG. 5C are schematic views showing the sequence in a case where the plasma treatment described above, which is capable of replacing a Si—CH 3 bond on the MSQ surface with a Si—H bond, is applied to a damascene process.
- a via hole 3 is formed in an insulation layer including MSQ 1 deposited on a substrate 2
- the MSQ exposed surface on the main surface and on the inner wall of the via hole 3 is covered with methyl groups as shown in FIG. 5A.
- methyl groups are replaced by hydrogen as shown in FIG. 5B, and the surface thereby turns to hydrophilic, which improves adhesion to an inorganic material.
- FIG. 6A through FIG. 6C are schematic views showing the sequence in a case where the plasma treatment described above, which is capable of breaking a Si—CH 3 bond on the MSQ surface to form a dangling bond, is applied to a damascene process.
- a wiring trench pattern 13 is formed in an insulation layer including MSQ 1 deposited on a substrate 2
- the MSQ exposed surface on the main surface and the inner wall of the wiring trench pattern 13 is covered with methyl groups as shown in FIG. 6A.
- Si—CH 3 bonds are broken to form a dangling bond layer 25 as shown in FIG. 6B.
- a releasing degree of C from the dangling bond layer 25 and a thickness thereof can be changed depending on the plasma treatment conditions.
- samples were prepared by depositing a barrier metal 4 and Cu used as a wiring material 5 on the wiring trench pattern 13 , and analysis was conducted as to scratches caused by separation resulted from CMP, by varying a releasing degree of C and the thickness.
- the number of scratch defects and an interconnect capacitance with respect to the concentration of C of the dangling bond layer 25 and the film thickness thereof were measured through the local EDX method, the result of which is set forth in Table 5 below.
- a barrier metal material that comes in contact with the dangling bond layer 25 is preferably TaN. Because Ta excels TaN in the wetting property and adhesion to Cu, the barrier metal preferably has a lamination structure of Ta/TaN.
- the barrier metal having the Ta/TaN lamination structure has been known, it should be noted that the fact that the Ta/TaN lamination structure is optimal when forming a barrier metal on the wiring groove or on the via hole on which the dangling bond layer has been formed in the damascene process using a low dielectric film having a bond of Si and a group made of organic constituents is a novel fact obtained by the knowledge of the inventor of the present application.
- FIG. 7A through FIG. 9C are cross sections showing the step-by-step sequence of a via first process to which the structure and the plasma treatment of the invention are applied.
- a first etching stopper film 7 , a first interlayer insulation film 8 , a second etching stopper film 9 , and a second interlayer insulation film 10 are formed sequentially from bottom to top in certain thickness through the CVD method, the plasma CVD method, etc.
- a film that can achieve the effect of the plasma treatment of the invention can be any low dielectric film containing hydrophobic groups having a large molecular structure like MSQ that contains methyl groups, and it may be MHSQ, SiC, SiCN, SiOC, SiCOH, etc. or a porous film of each.
- the low dielectric film can be formed through any adequate means, such as CVD and coating.
- the low dielectric film can be used as the first interlayer insulation film 8 or as both the first and second interlayer insulation films 8 and 10 .
- materials of films other than the low dielectric film are not especially limited. Any combination of materials such that can attain an etching selection ratio can be used, and materials can be selected from SiO 2 , SiN, SiON, etc. as needed.
- a problem may possibly occur in the CMP step of the wiring.
- a cap insulation film may be formed on the second interlayer insulation film 10 .
- a first reflection preventing film 11 a to be used to control reflection of exposing light is deposited on the second interlayer insulation film 10 in a thickness of approximately 50 nm
- chemically amplified resist to be used to form a via hole pattern is applied thereon in a thickness of approximately 600 nm, which is subjected to exposure and development through KrF photolithography.
- a first resist pattern 12 a is thereby formed.
- the first reflection preventing film 11 a , the second interlayer insulation film 10 , the second etching stopper film 9 , and the first interlayer insulation film 8 are etched away sequentially through known dry etching, and a via hole 3 penetrating through these films is thereby formed.
- the first resist pattern 12 a and the first reflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed.
- a chemically amplified resist is applied thereon in a thickness of approximately 600 nm and baked followed by exposure and development through KrF photolithography.
- a second resist pattern 12 b to be used to form a wiring trench pattern is thereby formed.
- the exposed second reflection preventing film 11 b is then removed through a dry etching method.
- the second interlayer insulation film 10 is etched away using the second etching stopper film 9 as an etching stopper, and a wiring trench pattern 13 is thereby formed.
- the second resist pattern 12 b and the second reflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed (see FIG. 8A).
- the plasma treatment which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is, while maintaining a vacuum.
- This plasma treatment is preferably a plasma treatment using a He/H 2 mixed gas or a plasma treatment using a He gas with application of certain RF bias.
- a He/H 2 mixed gas methyl groups of MSQ exposed on the main surface and the trench sidewall are replaced by hydrogen, and adhesion to the barrier metal is thereby improved.
- a barrier metal 4 such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum.
- a seed metal 19 of Cu to be used as the wiring material is formed in a film thickness of . approximately 100 nm to make it easier for Cu-plating to be grown.
- it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %.
- FIG. 10A through FIG. 13B are cross sections showing the step-by-step sequence of a dual hard mask process to which the structure and the plasma treatment of the invention are applied.
- a first etching stopper film 7 , a first interlayer insulation film 8 , a second etching stopper film 9 , and a second interlayer insulation film 10 are formed sequentially from bottom to top through the CVD method, the plasma CVD method, etc.
- a first hard mask film 16 and a second hard mask film 17 to be used as an etching mask for a wiring trench pattern are deposited on these films.
- the second interlayer insulation film 10 may be a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, MHSQ, SiC, SiCN, SiOC, SiCOH and OSG.
- the first reflection preventing film 11 a and the second hard mask film 17 are etched away through known dry etching, using the first resist pattern 12 a , and an opening to be used to form a wiring trench pattern through etching is thereby formed.
- the first resist pattern 12 a and the first reflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed.
- the second reflection preventing film 11 b , the first hard mask film 16 , the second interlayer insulation film 10 , the second etching stopper film 9 , and the first interlayer insulation film 8 are etched away through known dry etching, using the second resist pattern 12 b as a mask, and a via hole 3 penetrating through these films is thereby formed.
- the second resist pattern 12 b and the second reflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed.
- the first hard mask film 16 and the second interlayer insulation film 10 are etched away through a known dry etching method, using the second hard mask film 17 as a mask, and a wiring trench pattern 13 is thereby formed.
- the plasma treatment which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is, while maintaining a vacuum.
- the method, the conditions, the gas kind, etc. of the plasma treatment are the same as those set forth in the first example above.
- a barrier metal 4 such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is while maintaining a vacuum.
- a seed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown.
- it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %.
- FIG. 14A through FIG. 17C are cross sections showing the step-by-step sequence of the single damascene process to which the structure and the plasma treatment of the invention are applied.
- a first etching stopper film 7 and a first interlayer insulation film 8 are formed sequentially from bottom to top in certain thickness atop a lower layer wiring 6 through the CVD method, the plasma CVD method, etc. Then, after a first reflection preventing film 11 a to be used to control reflection of exposing light is deposited on the first interlayer insulation film 8 in a thickness of approximately 50 nm, chemically amplified resist to be used to form a via hole pattern is applied thereon in a thickness of approximately 500 nm, which is subjected to exposure and development through ArF photolithography. A first resist pattern 12 a is thereby formed.
- a film that can achieve the effect. of the plasma treatment of the invention can be any low dielectric film containing hydrophobic groups having a large molecular structure like MSQ that contains methyl groups, and it may be MHSQ, SiC, SiCN, SiOC, SiCOH, and OSG, etc. or a porous film of each.
- the low dielectric film can be formed through any adequate means, such as CVD and coating.
- the low dielectric film can be used as either of the first interlayer insulation film 8 and the second interlayer insulation film 10 .
- materials of films other than the low dielectric film are not especially limited. Any combination of materials such that can attain an etching selection ratio can be used, and materials can be selected from SiO 2 , SiN, SiON, SiC, SiCN, etc. as needed.
- the first reflection preventing film 11 a and the first interlayer insulation film 8 are etched away sequentially through known dry etching, and a via hole 3 penetrating through these films is thereby formed. Subsequently, the first resist pattern 12 a and the first reflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed.
- the plasma treatment which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is, while maintaining a vacuum.
- the method, the conditions, the gas kind, etc. of the plasma treatment are the same as those set forth in the first and second examples above.
- a barrier metal 4 such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum.
- a seed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown.
- it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %.
- the second reflection preventing film 11 b and the second interlayer insulation film 10 are etched away sequentially through known dry etching, and a wiring trench pattern 13 penetrating through these films is thereby formed.
- the second resist pattern 12 b and the second reflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed.
- the surface of the via pattern at the bottom of the wiring trench pattern 13 is cleaned through sputtering using an Ar gas.
- the plasma treatment which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that .is, while maintaining a vacuum.
- the method, the conditions, the gas kind, etc. are the same as those applied when forming the via plug.
- a barrier metal 4 such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum.
- a seed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown.
- it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %.
- FIG. 18A through FIG. 21C are cross sections showing the step-by-step sequence of the single damascene process to which the structure and the plasma treatment of the invention are applied.
- a first etching stopper film 7 , a first interlayer insulation film 8 , and a first cap insulation film 23 are formed sequentially from bottom to top in certain thickness atop a lower layer wiring 6 through the CVD method, the plasma CVD method, etc.
- a first reflection preventing film 11 a to be used to control reflection of exposing light is deposited on the first cap insulation film 23 in a thickness of approximately 50 nm
- chemically amplified resist to be used to form a via hole pattern is applied thereon in a thickness of approximately 500 nm, which is subjected to exposure and development through ArF photolithography.
- a first resist pattern 12 a is thereby formed.
- a film that can achieve the effect of the plasma treatment of the invention can be any low dielectric film containing hydrophobic groups having a large molecular structure like MSQ that contains methyl groups, and it may be MHSQ, SiC, SiCN, SiOC, SiCOH, and OSG, etc. or a porous film of each. Also, the low dielectric film can be formed through any adequate means, such as CVD and coating.
- This example will described a case where SiOC is used as both the first interlayer insulation film 8 and a second interlayer insulation film 10 . It should be appreciated, however, that the low dielectric film can be used as either of the first interlayer insulation film 8 and the second interlayer insulation film 10 . Also, materials of films other than the low dielectric film are not especially limited. Any combination of materials such that can attain an etching selection ratio can be used, and materials can be selected from SiO 2 , SiN, SiON, SiC, SiCN etc. as needed.
- the first reflection preventing film 11 a , the first cap insulation film 23 , and the first interlayer insulation film 8 are etched away sequentially through known dry etching, and a via hole 3 penetrating through these films is thereby formed.
- the first resist pattern 12 a and the first reflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed.
- the plasma treatment which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is while maintaining a vacuum.
- the method, the conditions, the gas kind, etc. of the plasma treatment are the same as those set forth in the first through third examples above.
- a barrier metal 4 such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum.
- a seed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown.
- it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %.
- the second reflection preventing film 11 b , the second cap insulation film 24 , and the second interlayer insulation film 10 are etched away sequentially through known dry etching, and a wiring trench pattern 13 penetrating through these films is thereby formed.
- the second resist pattern 12 b and the second reflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed.
- the surface of the via pattern at the bottom of the wiring trench pattern 13 is cleaned through sputtering using an Ar gas.
- the plasma treatment which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is while maintaining a vacuum.
- the method, the conditions, the gas kind, etc. are the same as those applied when forming the via plug.
- a barrier metal 4 such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum.
- a seed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown.
- it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %.
- a metal film such as a barrier metal
- a low dielectric film such as MSQ, MHSQ, SiC, SiCN, SiOC, and SICOH
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
Description
- 1. Field of the Invention
- The present invention relates to a structure of a semiconductor device and a manufacturing method thereof, and more particularly to, in a damascene process using a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, an interface: structure of a barrier metal and the low dielectric film and a surface treatment method thereof.
- 2. Description of the Related Art
- To meet the high integration of a semiconductor device and a reduction in chip size in recent years, not only the miniaturization of the wiring, but also the multi-level interconnection is being promoted. As a method of forming a multi-level interconnect structure, a so-called damascene process is generally performed, by which an interconnect is formed by embedding Cu in both a via hole and a wiring trench pattern concurrently followed by planarization through the CMP (Chemical Mechanical Polishing) method. The damascene process can increase density of wiring patterns; however, when the wiring patterns are formed too close, a parasitic capacitance between the wiring patterns causes problematic interconnect delay. Hence, a reduction in interconnect capacitance becomes an issue of great importance to improve the interconnect delay.
- In order to reduce the interconnect capacitance, there has been discussed a method of using a low dielectric material for the interlayer insulation film instead of a conventionally used SiO 2-based insulation film. The conventional damascene process using a low dielectric film as the interlayer insulation film will now be explained with reference to the accompanying drawings. FIG. 1A through FIG. 3B are cross sections showing the step-by-step sequence of a via first process, which is one embodiment of the conventional damascene process.
- Initially, as shown in FIG. 1A, a first
etching stopper film 7 to be used as an etching stopper for a via hole by preventing diffusion of Cu, a firstinterlayer insulation film 8 made of SiO2, a secondetching stopper film 9 to be used as an etching stopper for a wiring trench pattern, and a secondinterlayer insulation film 18 of a low dielectric film, such as hydrogen silsesquioxane (hereinafter, abbreviated to HSQ) and methyl silsesquioxane (hereinafter, abbreviated to MSQ), are deposited sequentially from bottom to top on asubstrate 2 in which alower layer wiring 6 made of Cu has been formed. Subsequently, after a firstreflection preventing film 11 a is formed on the secondinterlayer insulation film 18, photoresist is applied thereon, which is subjected to exposure and development. Afirst resist pattern 12 a to be used to form avia hole 3 is thereby formed. - Then, as shown in FIG. 1B, the first
reflection preventing film 11 a, the secondinterlayer insulation film 18, the secondetching stopper film 9, and the firstinterlayer insulation film 8 are etched away sequentially through a known dry etching technique, using thefirst resist pattern 12 a as a mask. Avia hole 3 penetrating through these films is thereby formed. - Then, after the
first resist pattern 12 a and the first reflection preventing film 11 aare removed, as shown in FIG. 1C, a secondreflection preventing film 11 b is formed and then photoresist is applied thereon, which is subjected to exposure and development. Asecond resist pattern 12 b to be used to form a wiring trench pattern through etching is thereby formed. Subsequently, the secondreflection preventing film 11 b and the secondinterlayer insulation film 18 are etched away sequentially through a known dry etching technique, and awiring trench pattern 13 is thereby formed (see FIG. 2A). - Then, as shown in FIG. 2B, the first
etching stopper film 7 atop thelower layer wiring 6 is removed, after which, as shown in FIG. 2C, abarrier metal 4 to be used as a base layer for a wiring material is formed. Then, awiring material 5, such as Cu, is embedded in the interiors of thewiring trench pattern 13 and thevia hole 3, and the surface thereof is planarized through CMP (see FIG. 3A and FIG. 3B). A dual damascene structure is thus obtained. - In the conventional damascene process described above, when HSQ is used as the second
interlayer insulation film 18, because HQS is an inorganic low dielectric film, it adheres well to a barrier metal, a silicon oxide film, and a silicon nitride film, which are also made of inorganic materials, and there occurs no problem that these inorganic materials are separated at the HSQ interface. - However, when a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, is used as the second
interlayer insulation film 18, it does not adhere well to an inorganic material, particularly, a barrier metal, and as shown in FIG. 3B, the barrier metal is separated from an MSQ-based low dielectric film during CMP, which gives rise to aproblematic scratch 21 on the surface of the MSQ-based low dielectric film, or stress caused by the multi-level interconnection gives rise toproblematic film separation 20 at the barrier metal/MSQ interface having poor adhesion. It should be noted, however, that the MSQ-based low dielectric film has a lower dielectric constant than HSQ, and is therefore expected as a promising next-generation interlayer film, which increases the importance of solving the adhesion problem at the interface between the MSQ-based low dielectric film and the barrier metal. - The reason why HSQ and MSQ have different adhesion to the
barrier metal 4 as described above is attributed to the difference as follows: HSQ has a structure in which oxygen and hydrogen are bonded to silicon atoms, whereas MSQ contains organic constituents having a large molecular structure, such as a methyl group, in order to lower a dielectric constant, and the organic constituents at the MSQ interface interfere with bonding of Si and thebarrier metal 4, such as tantalum (Ta) and tantalum nitride (TaN). - In order to prevent such unwanted separation, there has been discussed a structure that protects the groove sidewall after the groove is formed. For example, Japanese Patent Laid-Open Publication No. Hei. 10-284600 discloses a method of protecting the sidewall by providing a Si 3N4:or SiO2 sidewall to a groove pattern formed in the low dielectric interlayer film. This method, however, cannot avoid an increase in dielectric constant when a thick film is formed, and deterioration in adhesion associated with a pin-hole when a thin film is formed.
- Also, in order to prevent separation due to poor adhesion as described above, there has been discussed a method of improving adhesion by applying various surface treatments to the surface of MSQ after it is deposited. For example, during the fabrication sequence of a semiconductor device, cleaning through sputtering using an Ar gas is performed in many steps as needed, and Ar sputtering is performed to clean the surface of the
lower layer wiring 6 at the bottom of thevia hole 3 after thewiring trench pattern 13 is formed and before thebarrier metal 4 is deposited. However, because merely a sputtered material is etched away through Ar sputtering, it proves to be ineffective in reforming the MSQ surface. - Also, there has been discussed a method of performing an ozone treatment, a UV ozone treatment, or an oxygen plasma treatment after MSQ is deposited, and Japanese Patent Laid-Open Publication No. 2001-223269 discloses a method of reforming the surface of the interlayer insulation film to be a silicon oxide film or a silicon dioxide film containing excessive silicon through irradiation of a charged beam of an ionized oxygen gas. This method, however, has a problem that water comes into the film and a dielectric constant of the insulation film is increased; moreover, the surface of the film is made rough and a residue is left thereon.
- As has been described, it is essential to use a low. dielectric film containing organic constituents, such as MSQ, as an interlayer insulation film to reduce an interconnect capacitance. However, the reliability reduced by poor adhesion of the low dielectric film to an inorganic material, particularly, a barrier metal, poses a serious problem, and there has been a need to develop a structure capable of increasing adhesion of the low dielectric film to the barrier metal, and a process capable of reforming the surface of the low dielectric film. This problem is not limited to the via first dual damascene process described above, and can occur in any other damascene process, such as a dual hard mask process and a single damascene process, as well as in any other process using a low dielectric film having a bond of Si and a group made of organic constituents.
- An object of the present invention is to provide a semiconductor device capable of improving adhesion of a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, to a barrier metal at the interface in a damascene process and a manufacturing method thereof.
- In particular, the object is to provide a structure of a semiconductor device capable of improving adhesion of the low dielectric interlayer film to an inorganic material, such as the barrier metal, by removing the organic constituents at the barrier metal/film interface, and a manufacturing method of the semiconductor device.
- A semiconductor device according to the present invention comprises an insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, and a wiring material embedded, through a barrier metal, in one of a via hole and a wiring groove formed in said insulation layer. A layer is formed between the low dielectric film and the barrier metal and has a relatively low concentration of organic constituents in comparison with the low dielectric film.
- It is preferable for the semiconductor device of the invention that a concentration of carbon (C) of the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film is 7 atom % or below.
- It is preferable for the semiconductor device of the invention that a concentration of carbon (C) of the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film is 7 atom % or below and 2 atom % or above.
- It is preferable for the semiconductor device of the invention that the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film has a film thickness of 25 nm or less.
- It is preferable for the semiconductor device of the invention that the layer having the relatively low concentration of organic constituents in comparison with the low dielectric interlayer film has a Si—H bond.
- It is preferable for the semiconductor device of the invention that the low dielectric film is one of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of each.
- It is preferable for the semiconductor device of the invention that the barrier metal is made of tantalum nitride (TaN) on a side of the low dielectric film and tantalum (Ta) on a side of the wiring material.
- Also, according to a manufacturing method of a semiconductor device of the invention, in a manufacturing method of a semiconductor device including a step of embedding, through a barrier metal, a wiring material in one of a via hole and a wiring groove formed in an insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, a plasma treatment is performed before the barrier metal is deposited, using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of the low dielectric film with hydrogen, and a gas capable of decomposing at least part. of the group made of organic constituents to form a dangling bond.
- Also, according to a manufacturing method of a semiconductor device of the invention, in a manufacturing method of a semiconductor device including the steps of: forming at least a first interlayer insulation film and a second interlayer insulation film sequentially on a substrate in which a wiring pattern has been formed; forming a via hole penetrating through the first interlayer insulation film and the second interlayer insulation film using a first resist pattern formed on the second interlayer insulation film; removing the first resist pattern and then forming a trench pattern through etching of the second interlayer insulation film using a second resist pattern formed on the second interlayer insulation film; depositing a barrier metal on the second interlayer insulation film and on inner walls of the via hole and the trench pattern; depositing a wiring material and then embedding the wiring material in interiors of the via hole and the trench pattern; and removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, at least one of the first interlayer insulation film and the second interlayer insulation film is a low dielectric film having a bond of Si and a group made of organic constituents, and a plasma treatment is performed before the barrier metal is deposited, using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of the low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.
- Also, according to a manufacturing method of a semiconductor device of the invention, in a manufacturing method of a semiconductor device including the steps of: depositing at least a first interlayer insulation film, a second interlayer insulation film, and a hard mask material on a substrate in which a wiring pattern has been formed; forming a hard mask through etching of the hard mask material using a first resist pattern formed on the hard mask material; forming a via hole penetrating through the first interlayer insulation film and the second interlayer insulation film using a second resist pattern formed on the hard mask; removing the second resist pattern and then forming a trench pattern through etching of the second interlayer insulation film using the hard mask; depositing a barrier metal on the second interlayer insulation film and on inner walls of the via hole and the trench pattern; depositing a wiring material and then embedding the wiring material in interiors of the via hole and the trench pattern; and removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, at least one of the first interlayer insulation film, the second interlayer insulation film, and the hard mask is a low dielectric film having a bond of Si and a group made of organic constituents, and a plasma treatment is performed before the barrier metal is deposited, using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of the low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.
- The invention can be arranged in such a manner that the plasma treatment and the deposition of the barrier metal are performed under one of in situ and in vacuo conditions, or that the method further includes a step of performing sputtering using an Ar gas prior to the plasma treatment, and the Ar sputtering, the plasma treatment, and the depositing of the barrier metal are performed under one of in situ and in vacuo conditions.
- In the invention, it is preferable that the low dielectric film is one of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG); silicon carbonitride (SiCN), and a porous film of each.
- The invention is preferably arranged in such a manner that a mixed gas of hydrogen and a noble gas is used as a gas for the plasma treatment, or that a noble gas is used as a gas for the plasma treatment and RF bias is applied during the plasma treatment.
- In the invention, it is preferable that the noble gas includes one of He, Ne, Ar, Kr, Xe, and Rn.
- The invention is preferably arranged in such a manner that, in a case where He is used as the gas for the plasma treatment, power of the RF bias is set to a range from 250 W to 400 W both inclusive.
- As has been described, according to the invention, in a damascene process using an insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, provision of such a structure that can ensure adhesion between the low dielectric film and the barrier metal makes it possible to eliminate a problem that the barrier metal is separated during CMP and scratches are left on the low dielectric film, and to prevent film separation at the barrier metal/low dielectric film interface caused by stress resulted from the multi-level interconnection. The reliability of the damascene process using the low dielectric film can be thus improved.
- Also, according to the invention, the plasma treatment is performed using a mixed gas of H 2 and He, a He gas, etc. as a pre-step of depositing the barrier metal after the trench pattern or the via hole is formed in the insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ. Thus, it is possible to replace the organic constituents (a methyl group in the case of MSQ) on the surface of the low dielectric film with hydrogen or decompose the organic constituents to form a dangling bond. Adhesion of the low dielectric film to the barrier metal can be thus improved. Consequently, it is possible to eliminate a problem that the barrier metal is separated during CMP and scratches are left on the low dielectric film, and to prevent film separation at the barrier metal/low dielectric film interface caused by stress resulted from the multi-level interconnection. The reliability of the damascene process using the low dielectric film-can be thus improved.
- FIG. 1A through FIG. 1C are cross sections showing the step-by-step sequence of a conventional via first process;
- FIG. 2A through FIG. 2C are cross sections showing the step-by-step sequence of the conventional via first process;
- FIG. 3A and FIG. 3B are cross sections showing the step-by-step sequence of the conventional via first process;
- FIG. 4A and FIG. 4B are views schematically showing the mechanism of a plasma treatment of the invention;
- FIG. 5A through FIG. 5C are cross sections showing a part of the fabrication sequence including the plasma treatment of the invention;
- FIG. 6A through FIG. 6C are cross sections showing a part of the fabrication sequence including a structure and the plasma treatment of the invention;
- FIG. 7A through FIG. 7C are cross sections showing the step-by-step sequence of a via first process according to a first example of the invention;
- FIG. 8A through FIG. 8C are cross sections showing the step-by-step sequence of the via first process according to the first example of the invention;
- FIG. 9A through FIG. 9C are cross sections showing the step-by-step sequence of the via first process according to the first example of the invention;
- FIG. 10A through FIG. 10C are cross sections showing the step-by-step sequence of a dual hard mask process according to a second example of the invention;
- FIG. 11A through FIG. 11C are cross sections showing the step-by-step sequence of the dual hard mask process according to the second example of the invention;
- FIG. 12A through FIG. 12C are cross sections showing the step-by-step sequence of the dual hard mask process according to the second example of the invention;
- FIG. 13A and FIG. 13B are cross sections showing the step-by-step sequence of the dual hard mask process according to the second example of the invention;
- FIG. 14A through FIG. 14C are cross sections showing the step-by-step sequence of a single damascene process according to a third example of the invention;
- FIG. 15A through FIG. 15C are cross sections showing the step-by-step sequence of the single damascene process according to the third example of the invention;
- FIG. 16A and FIG. 16B are cross sections showing the step-by-step sequence of the single damascene process according to the third example of the invention;
- FIG. 17A through FIG. 17C are cross sections showing the step-by-step sequence of the single damascene process according to the third example of the invention;
- FIG. 18A through FIG. 18C are cross sections showing the step-by-step sequence of a single damascene process according to a fourth example of the invention;
- FIG. 19A through FIG. 19C are cross sections showing the step-by-step sequence of the single damascene process according to the fourth example of the invention;
- FIG. 20A and FIG. 20B are cross sections showing the step-by-step sequence of the single damascene process according to the fourth example of the invention; and
- FIG. 21A through FIG. 21C are cross sections showing the step-by-step sequence of the single damascene process according to the fourth example of the invention.
- As has been described in the related art column, sputtering using an Ar gas has been used extensively as means for cleaning the surface layer when a semiconductor device is manufactured. Impurities and foreign matters adhering on the surface of a sputtered material can be removed through Ar sputtering; however, applying Ar sputtering to a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, cannot improve adhesion of the low dielectric film to a barrier metal.
- The reason why is assumed as follows: Ar used for the sputtering has a large size and large energy because of RF bias, and therefore, not only methyl groups covering the MSQ surface, but also MSQ molecules as a whole are sputtered, which allows new MSQ molecules to appear on the sputtered surface, and methyl groups thus cover the surface again. Hence, in order to remove only methyl groups effectively from MSQ,. it may be appropriate to use a gas having a small atomic weight and the ability to perform a replacement reaction with methyl groups. Hence, the following experiment was conducted using, as a representative kind of gas,. a mixed gas of a highly reactive gas and a noble gas or single noble gas (to be more specific, a mixed gas of H 2 and He or a He gas).
- Initially, samples were manufactured by depositing tantalum (Ta), a tantalum nitride (TaN) layer, and a Cu layer as a barrier metal on an MSQ film through sputtering. The film structure was Cu 100 nm/
Ta 15 nm/TaN 15 nm/MSQ 300 nm. More specifically, after the MSQ film was subjected to cleaning process described below in a pre-cleaning chamber, Ta and a TaN layer were deposited in a PVD chamber for a barrier metal, and then a Cu layer was deposited in a PVD chamber for Cu. The wafer was transported from chamber to chamber in vacuo (a range of 10−7 torr or less) to prevent contamination on the MSQ surface. - As the cleaning process, three types as follows were performed: a process of performing only etching using an Ar gas; a process of performing etching using an Ar gas followed by an in situ plasma treatment using a He/H 2 mixed gas; and a process of performing etching using an Ar gas followed by an in situ plasma treatment using a He gas. The samples cleaned in the respective processes were subjected to a tape test using an adhesive tape. The result is set forth in Table 1 below.
TABLE 1 Separation Percentage in Cleaning Process Tape Test Only Ar Etching 100% Ar Etching + He Plasma 100% Treatment Ar Etching + He/H2 Plasma 0% Treatment - Table 1 reveals that adhesion at the barrier metal/MSQ interface was unsatisfactory in the process performing Ar etching alone and the process performing the He plasma treatment after Ar etching, and the barrier metal layer and the Cu layer were separated from MSQ film at the barrier metal/MSQ interface in all the samples; however, adhesion at the barrier metal/MSQ interface was improved in the process of performing the He/H 2 plasma treatment after Ar etching, and no separation occurred. It is understood from the result that the plasma treatment using a gas containing H2 is effective in improving adhesion of MSQ.
- Different from H 2, He is less reactive but has a smaller atomic weight than Ar, and therefore, may be able to remove only methyl groups from MSQ depending on the conditions. Hence, samples were manufactured by performing cleaning with He plasma having larger energy by gradually applying RF bias during the He plasma treatment, and subjected to a tape test in the same manner as above. The result is set forth in Table 2 below.
TABLE 2 Separation Percentage Cleaning Process in Tape Test Only Ar Etching 100% Ar Etching + He Plasma 100% Treatment (Bias 0 W) Ar Etching + He Plasma 0% Treatment (Bias 250 W) Ar Etching + He Plasma 0% Treatment (Bias 400 W) - Table 2 reveals that no adhesion improving effect was acknowledged in the treatment where no RF bias was applied, whereas when RF bias of 250 W or above was applied, no separation occurred, indicating that adhesion was improved. The reason why is assumed that energy of He plasma without application of RF bias is too small to decompose methyl groups. Hence, the result indicates that even when a gas having no or poor reactivity is used, it is still possible to decompose methyl groups by applying RF bias and conferring energy needed. However, adhesion was not improved by applying RF bias in the case of Ar, from which it is understood that the effect cannot be achieved unless an adequate gas is selected.
- It is understood from the results set forth in Table 1 and Table 2 above that adhesion at the interface of MSQ and the barrier metal can be improved through the use of a mixed gas (He/H 2) containing a highly reactive gas or a noble gas (He). However, it remains uncertain whether the improvement effect is attributed to removal of methyl groups on the MSQ surface. In general, methyl groups are hydrophobic, whereas hydrogen groups and dangling bonds are hydrophilic. Hence, it is anticipated that removing methyl groups effectively can increase an affinity for water of the MSQ surface, which improves the wetting property and thereby reduces an angle of contact. Hence, samples were manufactured by performing cleaning in the same processes set forth in Table 1 above, and an angle of contact between water and the MSQ surface was measured. The results were set forth in Table 3 and Table 4 below.
TABLE 3 Cleaning Process Angle of Contact (deg.) Only Ar Etching 51 Ar Etching + He Plasma 45 Treatment Ar Etching + He/H2 Plasma 32 Treatment -
TABLE 4 Angle of Contact Cleaning Process (deg.) Only Ar Etching 51 Ar Etching + He Plasma 45 Treatment (Bias 0 W) Ar Etching + He Plasma 18 Treatment (Bias 250 W) Ar Etching + He Plasma 14 Treatment (Bias 400 W) - Table 3 above reveals that, although a difference between these processes was not clear in the tape test, the angle of contact was reduced slightly in the process of performing the He plasma treatment (no RF bias) after Ar etching in comparison with the process of performing Ar etching alone, from which it is understood that the He plasma treatment itself is effective in improving adhesion. Also, the angle of contact was further reduced in the process of performing the He/H 2 plasma treatment after Ar etching, from which it is understood that a H2 gas is highly effective in reforming the surface. In addition, Table 4 above reveals that the angle of. contact was gradually reduced with application of .RF bias even in the He plasma treatment, and in particular, when RF bias of 250 W or above was applied, the surface reforming effect was higher than that attained in the He/H2 plasma treatment.
- The effect achieved by the plasma treatment will now be explained with reference to FIG. 4A and FIG. 4B. The non-treated MSQ surface is covered with methyl groups, and for example, by exposing the MSQ surface to H 2 plasma, a Si—CH3 bond on the MSQ surface is replaced by a Si—H bond as shown in FIG. 4A. It is hence assumed that because a methyl group having a large molecular structure is replaced by hydrogen, a distance between Si and a metal forming the barrier metal becomes shorter, and the bonding strength is thus improved. Also, in the case of the He plasma treatment, as shown in FIG. 4B, it is assumed that a Si—CH3 bond on the MSQ surface is broken to form a dangling bond as RF bias is increased, and the bonding strength between Si and the barrier metal is thus improved.
- It is understood from the results of the experiments above that, in order to achieve the adhesion improving effect of the invention, it is sufficient to use a mixed gas containing a highly reactive gas capable of replacing a methyl group with a group having a small molecular structure, such as hydrogen, or a gas capable of decomposing only a methyl group covering the surface without decomposing a MSQ molecule as a whole. Besides He and He/H 2, a mixed gas of H2 and a noble gas, such as Ne, Ar, Kr, Xe, and Rn, a gas containing ammonia, etc. can be used.
- RF bias may be applied in the He/H 2plasma treatment. In this case, however, hydrogen atoms penetrate into the interior of a substance exposed to plasma, and in particular, in a case where Cu used as a wiring material is exposed, there occurs a problem that Cu becomes brittle. Hence, RF bias needs to be optimized when a hydrogen gas is used.
- In regard to a component ratio of a H 2 gas and a noble gas, when a ratio of a H2 gas is increased, the reactivity becomes too high to remain controllable, and there is the possibility that a replacement-reaction of methyl groups takes place not only on the surface layer, but also in the interior, which undesirably increases a dielectric constant of MSQ. In order to avoid such an inconvenience, it is preferable to set a component ratio such that a few percent of a highly reactive gas, such as H2, is contained (in the case of H2 and He, H2 is 1 to 10% and He is 99 to 90%, for example, H2and He=4% and 96%). An ammonia gas may be a possible choice when the ability to react with a methyl group is considered. In this case, however, Cu used as a wiring material undergoes nitridation with ammonia, and an adverse effect on the reliability of interconnections is concerned. For this reason, the concentration of ammonia, RF bias, a processing time, etc. need to be optimized.
- Also, a material capable of improving adhesion through the plasma treatment using the above-specified gases can be any material containing organic constituents or any material containing a group having a large molecular structure. Besides MSQ, the material can be methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), etc., or a porous film of each. Also, these films can be formed through any method, and an arbitrary method, such as the CVD method and the coating method, can be used.
- FIG. 5A through FIG. 5C are schematic views showing the sequence in a case where the plasma treatment described above, which is capable of replacing a Si—CH 3 bond on the MSQ surface with a Si—H bond, is applied to a damascene process. When a via
hole 3 is formed in an insulationlayer including MSQ 1 deposited on asubstrate 2, the MSQ exposed surface on the main surface and on the inner wall of the viahole 3 is covered with methyl groups as shown in FIG. 5A. By applying the plasma treatment using a He/H2 mixed gas under these conditions, methyl groups are replaced by hydrogen as shown in FIG. 5B, and the surface thereby turns to hydrophilic, which improves adhesion to an inorganic material. By depositing abarrier metal 4 as shown in FIG. 5C under these conditions,MSQ 1 bonds to thebarrier metal 4 so firmly that even when a wiring metal is embedded in the viahole 3 through CMP, thebarrier metal 4 will be separated from neither the MSQ surface nor the inner wall of the viahole 3. It is thus possible to improve the reliability of the multi-level interconnection. - Although the plasma treatment using a He/H 2 mixed gas. or a He gas has been known, it should be noted that the effect of improving adhesion to the barrier metal by replacing a methyl group of a low dielectric film, such as MSQ, with hydrogen or by decomposing a methyl group to form a dangling bond through the plasma treatment is a novel fact obtained by the knowledge of the inventor of the present application.
- FIG. 6A through FIG. 6C are schematic views showing the sequence in a case where the plasma treatment described above, which is capable of breaking a Si—CH 3 bond on the MSQ surface to form a dangling bond, is applied to a damascene process. When a
wiring trench pattern 13 is formed in an insulationlayer including MSQ 1 deposited on asubstrate 2, the MSQ exposed surface on the main surface and the inner wall of thewiring trench pattern 13 is covered with methyl groups as shown in FIG. 6A. By applying the plasma treatment using a He gas with application of RF bias, Si—CH3 bonds are broken to form adangling bond layer 25 as shown in FIG. 6B. - A releasing degree of C from the
dangling bond layer 25 and a thickness thereof can be changed depending on the plasma treatment conditions. Hence, as shown in FIG. 6C, samples were prepared by depositing abarrier metal 4 and Cu used as awiring material 5 on thewiring trench pattern 13, and analysis was conducted as to scratches caused by separation resulted from CMP, by varying a releasing degree of C and the thickness. The number of scratch defects and an interconnect capacitance with respect to the concentration of C of thedangling bond layer 25 and the film thickness thereof were measured through the local EDX method, the result of which is set forth in Table 5 below.TABLE 5 C Film Number of Interconnect Concentration Thickness Scratches capacitance (atom %) (nm) (counts) (pF/mm) 15 0 1213 0.081 12 5 501 0.081 10 10 52 0.082 7 14 12 0.083 2 25 15 0.086 1 41 11 0.115 - It is confirmed from Table 5 above that the number of scratch defects due to adhesion was reduced noticeably as the concentration of C of the
dangling bond layer 25 was lowered. In particular, when the concentration of C was 7 atom % or below, a satisfactory result was obtained. It should be noted, however, that when the film thickness of thedangling bond layer 25 was 41 nm, an increase in interconnect capacitance was confirmed. Hence, it is preferable that the concentration of C of thedangling bond layer 25 is 2 atom % or above and the film thickness thereof is 25 nm or less. - Samples were prepared by forming a Ta single-layer, a TaN single-layer, a Ta/TaN lamination layer as the
barrier metal 4 in the wiring groove on which thedangling bond layer 25 had been formed, and evaluation was conducted in the same manner as above. The resulting numbers of scratch defects with respect to the respective barrier metals are set forth in Table 6 below.TABLE 6 C Film Number of Concentration Thickness Scratches Barrier Metal (atom %) (nm) (counts) Ta Single- layer 7 14 18 TaN Single- layer 7 14 13 Ta/ TaN 7 14 12 Lamination Layer Ta Single- layer 10 10 249 TaN Single- layer 10 10 54 Ta/ TaN 10 10 52 Lamination Layer - Table 6 above reveals that when the concentration of C of the
dangling bond layer 25 was 7 atom %, the number of scratch defects was satisfactorily small in all the barrier metal structures; by contrast, when the concentration of C of thedangling bond layer 25 was 10 atom %, the number of scratch defects was increased in the case of the Ta single-layer alone. It is thus understood that a barrier metal material that comes in contact with thedangling bond layer 25 is preferably TaN. Because Ta excels TaN in the wetting property and adhesion to Cu, the barrier metal preferably has a lamination structure of Ta/TaN. - Although the barrier metal having the Ta/TaN lamination structure has been known, it should be noted that the fact that the Ta/TaN lamination structure is optimal when forming a barrier metal on the wiring groove or on the via hole on which the dangling bond layer has been formed in the damascene process using a low dielectric film having a bond of Si and a group made of organic constituents is a novel fact obtained by the knowledge of the inventor of the present application.
- In order to describe the embodiment of the invention discussed above more in detail, the following description will describe, with reference to the accompanying drawings, concrete examples of a damascene process to which the structure and the plasma treatment of the invention are applied.
- Firstly, a dual damascene process according to a first example of the invention will be explained with reference to FIG. 7A through FIG. 9C. FIG. 7A through FIG. 9C are cross sections showing the step-by-step sequence of a via first process to which the structure and the plasma treatment of the invention are applied.
- Initially, as shown in FIG. 7A, after a
lower layer wiring 6 made of Cu, Cu alloy or the like is formed in asubstrate 2 through a known method, a firstetching stopper film 7, a firstinterlayer insulation film 8, a secondetching stopper film 9, and a secondinterlayer insulation film 10 are formed sequentially from bottom to top in certain thickness through the CVD method, the plasma CVD method, etc. A film that can achieve the effect of the plasma treatment of the invention can be any low dielectric film containing hydrophobic groups having a large molecular structure like MSQ that contains methyl groups, and it may be MHSQ, SiC, SiCN, SiOC, SiCOH, etc. or a porous film of each. The low dielectric film can be formed through any adequate means, such as CVD and coating. - The following description will describe a case where MSQ is used as the second
interlayer insulation film 10. It should be appreciated, however, that the low dielectric film can be used as the firstinterlayer insulation film 8 or as both the first and secondinterlayer insulation films interlayer insulation film 10, a problem may possibly occur in the CMP step of the wiring. In order to avoid such a problem, a cap insulation film may be formed on the secondinterlayer insulation film 10. - Subsequently, after a first
reflection preventing film 11 a to be used to control reflection of exposing light is deposited on the secondinterlayer insulation film 10 in a thickness of approximately 50 nm, chemically amplified resist to be used to form a via hole pattern is applied thereon in a thickness of approximately 600 nm, which is subjected to exposure and development through KrF photolithography. A first resistpattern 12 a is thereby formed. - Then, as shown in FIG. 7B, the first
reflection preventing film 11 a, the secondinterlayer insulation film 10, the secondetching stopper film 9, and the firstinterlayer insulation film 8 are etched away sequentially through known dry etching, and a viahole 3 penetrating through these films is thereby formed. Subsequently, the first resistpattern 12 a and the firstreflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed. - Then, as shown in FIG. 7C, after a second
reflection preventing film 11 b is deposited in a thickness of approximately 50 nm, a chemically amplified resist is applied thereon in a thickness of approximately 600 nm and baked followed by exposure and development through KrF photolithography. A second resistpattern 12 b to be used to form a wiring trench pattern is thereby formed. The exposed secondreflection preventing film 11 b is then removed through a dry etching method. - Then, the second
interlayer insulation film 10 is etched away using the secondetching stopper film 9 as an etching stopper, and awiring trench pattern 13 is thereby formed. Subsequently, the second resistpattern 12 b and the secondreflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed (see FIG. 8A). - Then, as shown in FIG. 8B, after the exposed first
etching stopper film 7 is removed through a dry etching method, the surface of thelower layer wiring 6 at the bottom of the viahole 3 is cleaned through sputtering using an Ar gas. - Under these conditions, the surface of the second interlayer insulation film (MSQ) 10 and the sidewalls of the
wiring trench pattern 13 and the viahole 3 are covered with methyl groups, and satisfactory adhesion cannot be attained by forming a barrier metal directly thereon. Hence,. as shown in FIG. 8C, the plasma treatment, which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is, while maintaining a vacuum. This plasma treatment is preferably a plasma treatment using a He/H2 mixed gas or a plasma treatment using a He gas with application of certain RF bias. For example, when the plasma treatment using a He/H2 mixed gas is performed, methyl groups of MSQ exposed on the main surface and the trench sidewall are replaced by hydrogen, and adhesion to the barrier metal is thereby improved. - It is preferable to perform the Ar sputtering, the He/H 2 plasma treatment, and the He plasma treatment under the conditions set forth below.
<Conditions for Ar Sputtering Treatment> Gas pressure: approximately 0.2 to 5 mTorr Gas kind: 100% of argon RF power source: approximately 200 W to 600 W RF bias source: approximately 200 W to 400 W Time: approximately 60 seconds <Conditions for He/H2 Plasma Treatment> Gas pressure: approximately 20 to 100 mTorr Gas kind: mixed gas of hydrogen and helium, preferably with a mixing percentage of H2 and He = 4% and 96% RF power source: approximately 200 W to 600 W Time: approximately 60 seconds <Conditions for He Plasma Treatment> Gas pressure: approximately 20 to 100 mTorr Gas kind: 100% of helium RF power source: approximately 200 W to 600 W RF bias source: approximately 200 W to 400 W Time: approximately 60 seconds - After the MSQ surface is reformed through the plasma treatment, as shown in FIG. 9A, a
barrier metal 4, such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum. Subsequently, aseed metal 19 of Cu to be used as the wiring material is formed in a film thickness of . approximately 100 nm to make it easier for Cu-plating to be grown. In this instance, it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %. - Then, as shown in FIG. 9B, Cu to be used as a
wiring material 5 is formed through plating, and thewiring trench pattern 13 and the viahole 3 are filled with Cu, after which, as shown in FIG. 9C, extra Cu and barrier metal are removed by polishing through CMP and the surface is planarized. A dual damascene structure is thus completed. - With the semiconductor device obtained through the above method, neither separation of the barrier metal at the MSQ interface nor starches on the MSQ surface described in the conventional examples are acknowledged, which proves that the plasma treatment of the invention is effective for a process using MSQ.
- A dual damascene process according a second example of the invention will now be explained with reference to FIG. 10A through FIG. 13B. FIG. 10A through FIG. 13B are cross sections showing the step-by-step sequence of a dual hard mask process to which the structure and the plasma treatment of the invention are applied.
- Initially, in the same manner as the first example above, as shown in FIG. 10A, after a
lower layer wiring 6 made of Cu, Cu alloy or the like is formed in asubstrate 2 through a known method, a firstetching stopper film 7, a firstinterlayer insulation film 8, a secondetching stopper film 9, and a secondinterlayer insulation film 10 are formed sequentially from bottom to top through the CVD method, the plasma CVD method, etc. Then, in this example, a firsthard mask film 16 and a secondhard mask film 17 to be used as an etching mask for a wiring trench pattern are deposited on these films. - This example will also describe a case where MSQ is used as the second
interlayer insulation film 10. It should be appreciated, however, that instead of or in addition to the secondinterlayer insulation film 10, at least one of the firstinterlayer insulation film 8, the firsthard mask film 16, and the secondhard mask film 17 may be a low dielectric film having a bond of Si and a group made of organic constituents, such as MSQ, MHSQ, SiC, SiCN, SiOC, SiCOH and OSG. - Subsequently, after a first reflection preventing film 11 ais formed on the second
hard mask film 17 in a thickness of approximately 50 nm, chemically amplified resist is applied thereon in a thickness of approximately 600 nm, which is subjected to exposure and development through KrF photolithography. A first resistpattern 12 a is thereby formed. - Then, as shown in FIG. 10B, the first
reflection preventing film 11 a and the secondhard mask film 17 are etched away through known dry etching, using the first resistpattern 12 a, and an opening to be used to form a wiring trench pattern through etching is thereby formed. Subsequently, the first resistpattern 12 a and the firstreflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed. - Then, as shown in FIG. 10C, after a second
reflection preventing film 11 b is formed in a thickness of approximately 50 nm, chemically amplified resist is applied thereon in a thickness of approximately 600 nm and baked followed by exposure and development through KrF photolithography. A second resistpattern 12 b having an opening within the etched region of the secondhard mask film 17 to be used to form a via hole is thereby formed. - Then, as shown in FIG. 11A, the second
reflection preventing film 11 b, the firsthard mask film 16, the secondinterlayer insulation film 10, the secondetching stopper film 9, and the firstinterlayer insulation film 8 are etched away through known dry etching, using the second resistpattern 12 b as a mask, and a viahole 3 penetrating through these films is thereby formed. - Then, as shown in FIG. 11B, the second resist
pattern 12 b and the secondreflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed. - Then, as shown in FIG. 11C, the first
hard mask film 16 and the secondinterlayer insulation film 10 are etched away through a known dry etching method, using the secondhard mask film 17 as a mask, and awiring trench pattern 13 is thereby formed. - Then, as shown in FIG. 12A, after the exposed first
etching stopper film 7 is removed through a dry etching method, the surface of thelower layer wiring 6 at the bottom of the viahole 3 is cleaned through sputtering using an Ar gas. Subsequently, as shown in FIG. 12B, the plasma treatment, which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is, while maintaining a vacuum. The method, the conditions, the gas kind, etc. of the plasma treatment are the same as those set forth in the first example above. - After the MSQ surface is reformed through the plasma treatment, as shown in FIG. 12C, a
barrier metal 4, such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is while maintaining a vacuum. Subsequently, aseed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown. In this instance, it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %. - Then, as shown in FIG. 13A, Cu to be used as a
wiring material 5 is formed through plating, and thewiring trench pattern 13 and the viahole 3 are filled with Cu, after which, as shown in FIG. 13B, extra Cu and barrier metal are removed by polishing through CMP and the surface is planarized. A dual damascene structure is thus completed. - In a case where organic films are used for all the interlayer insulation films, in the step of FIG. 11A, all of the second
reflection preventing film 11 b, the firsthard mask film 16, the secondinterlayer insulation film 10, and the secondetching stopper film 9 are etched away using the second resistpattern 12 b. Then, in the step of FIG. 1C, not only can thewiring trench pattern 13 be formed through etching of the firsthard mask film 16 and the secondinterlayer insulation film 10 using the secondhard mask film 17, but also the viahole 3 penetrating through to the firstetching stopper film 7 can be formed at the same time through etching of the firstinterlayer insulation film 8. - With the semiconductor device obtained in this manner, as with the first example above, neither separation of the barrier metal at the MSQ interface nor scratches on the MSQ surface are acknowledged, which proves that the structure and the plasma treatment of the invention are effective for a process using MSQ.
- A single damascene process according to a third example of the invention will now be explained with reference to FIG. 14A through FIG. 17C. FIG. 14A through FIG. 17C are cross sections showing the step-by-step sequence of the single damascene process to which the structure and the plasma treatment of the invention are applied.
- Initially, as shown in FIG. 14A, a first
etching stopper film 7 and a firstinterlayer insulation film 8 are formed sequentially from bottom to top in certain thickness atop alower layer wiring 6 through the CVD method, the plasma CVD method, etc. Then, after a firstreflection preventing film 11 a to be used to control reflection of exposing light is deposited on the firstinterlayer insulation film 8 in a thickness of approximately 50 nm, chemically amplified resist to be used to form a via hole pattern is applied thereon in a thickness of approximately 500 nm, which is subjected to exposure and development through ArF photolithography. A first resistpattern 12 a is thereby formed. - A film that can achieve the effect. of the plasma treatment of the invention can be any low dielectric film containing hydrophobic groups having a large molecular structure like MSQ that contains methyl groups, and it may be MHSQ, SiC, SiCN, SiOC, SiCOH, and OSG, etc. or a porous film of each. The low dielectric film can be formed through any adequate means, such as CVD and coating.
- The following description will describe a case where MSQ is used as both the first
interlayer insulation film 8 and a secondinterlayer insulation film 10. It should be appreciated, however, that the low dielectric film can be used as either of the firstinterlayer insulation film 8 and the secondinterlayer insulation film 10. Also, materials of films other than the low dielectric film are not especially limited. Any combination of materials such that can attain an etching selection ratio can be used, and materials can be selected from SiO2, SiN, SiON, SiC, SiCN, etc. as needed. - Then, as shown in FIG. 14B, the first reflection preventing film 11 aand the first
interlayer insulation film 8 are etched away sequentially through known dry etching, and a viahole 3 penetrating through these films is thereby formed. Subsequently, the first resistpattern 12 a and the firstreflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed. - Then, as shown in FIG. 14C, after the exposed first
etching stopper film 7 is removed through a dry etching method, the surface of thelower layer wiring 6 at the bottom of the viahole 3 is cleaned through sputtering using an Ar gas. Subsequently, the plasma treatment, which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is, while maintaining a vacuum. The method, the conditions, the gas kind, etc. of the plasma treatment are the same as those set forth in the first and second examples above. - This example will describe a case where the He plasma treatment is performed. After a dangling bond layer is formed on the MSQ surface through the He plasma treatment, as shown in FIG. 15A, a
barrier metal 4, such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum. Subsequently, aseed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown. In this instance, it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %. - Then, after Cu to be used as a
wiring material 5 is formed through plating and the viahole 3 is filled with Cu, as shown in FIG. 15B, extra Cu and barrier metal are removed by polishing through CMP and the surface is planarized. A via plug is thus completed.. Subsequently, as shown in FIG. 15C, a secondetching stopper film 9 and a secondinterlayer insulation film 10 are formed sequentially from bottom to top in certain thickness for the use of the wiring. - Then, as shown in FIG. 16A, after a second
reflection preventing film 11 b to be used to control reflection of exposing light is deposited on the secondinterlayer insulation film 10 in a thickness of approximately 50 nm, chemically amplified resist to be used to form a via hole pattern is. applied thereon in a thickness of approximately 400 nm, which is subjected to exposure and development through ArF photolithography. A second resistpattern 12 b is thereby formed. - Then, as shown in FIG. 16B, the second
reflection preventing film 11 b and the secondinterlayer insulation film 10 are etched away sequentially through known dry etching, and awiring trench pattern 13 penetrating through these films is thereby formed. Subsequently, the second resistpattern 12 b and the secondreflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed. - Then, as shown in FIG. 17A, after the exposed second
etching stopper film 9 is removed through a dry etching method, the surface of the via pattern at the bottom of thewiring trench pattern 13 is cleaned through sputtering using an Ar gas. Subsequently, the plasma treatment, which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that .is, while maintaining a vacuum. The method, the conditions, the gas kind, etc. are the same as those applied when forming the via plug. - This example will describe a case where the He plasma treatment is performed. After a dangling bond layer is formed on the MSQ surface through the He plasma treatment, as shown in FIG. 17B, a
barrier metal 4, such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum. Subsequently, aseed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown. In this instance, it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %. - Then, after Cu to be used as a
wiring material 5 is formed through plating and thewiring trench pattern 13 is filled with Cu, as shown in FIG. 17C, extra Cu and barrier metal are removed by polishing through CMP and the surface is planarized. A single damascene structure is thus completed. - With the semiconductor device obtained in this manner, as with the first and second examples above,. neither separation of the barrier metal at the MSQ interface. nor scratches on the MSQ surface are acknowledged, which proves that the structure and the plasma treatment of the invention are effective for a process using MSQ.
- A single damascene process according to a fourth example of the invention will now be explained with reference to FIG. 18A through FIG. 21C. FIG. 18A through FIG. 21C are cross sections showing the step-by-step sequence of the single damascene process to which the structure and the plasma treatment of the invention are applied.
- Initially, as shown in FIG. 18A, a first
etching stopper film 7, a firstinterlayer insulation film 8, and a firstcap insulation film 23 are formed sequentially from bottom to top in certain thickness atop alower layer wiring 6 through the CVD method, the plasma CVD method, etc. Then, after a firstreflection preventing film 11 a to be used to control reflection of exposing light is deposited on the firstcap insulation film 23 in a thickness of approximately 50 nm, chemically amplified resist to be used to form a via hole pattern is applied thereon in a thickness of approximately 500 nm, which is subjected to exposure and development through ArF photolithography. A first resistpattern 12 a is thereby formed. - A film that can achieve the effect of the plasma treatment of the invention can be any low dielectric film containing hydrophobic groups having a large molecular structure like MSQ that contains methyl groups, and it may be MHSQ, SiC, SiCN, SiOC, SiCOH, and OSG, etc. or a porous film of each. Also, the low dielectric film can be formed through any adequate means, such as CVD and coating.
- This example will described a case where SiOC is used as both the first
interlayer insulation film 8 and a secondinterlayer insulation film 10. It should be appreciated, however, that the low dielectric film can be used as either of the firstinterlayer insulation film 8 and the secondinterlayer insulation film 10. Also, materials of films other than the low dielectric film are not especially limited. Any combination of materials such that can attain an etching selection ratio can be used, and materials can be selected from SiO2, SiN, SiON, SiC, SiCN etc. as needed. - Then,. as shown in FIG. 18B, the first
reflection preventing film 11 a, the firstcap insulation film 23, and the firstinterlayer insulation film 8 are etched away sequentially through known dry etching, and a viahole 3 penetrating through these films is thereby formed. Subsequently, the first resistpattern 12 a and the firstreflection preventing film 11 a are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed. - Then, as shown in FIG. 18C, after the exposed first
etching stopper film 7 is removed through a dry etching method, the surface of thelower layer wiring 6 at the bottom of the viahole 3 is cleaned through sputtering using an Ar gas. Subsequently, the plasma treatment, which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is while maintaining a vacuum. The method, the conditions, the gas kind, etc. of the plasma treatment are the same as those set forth in the first through third examples above. - This example will describe a case where the He plasma treatment is performed. After a dangling bond layer is formed through the He plasma treatment on the side surface where SiOC is exposed, as shown in FIG. 19A, a
barrier metal 4, such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum. Subsequently, aseed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown. In this instance, it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %. - Then, after Cu to be used as a
wiring material 5 is formed through plating and the viahole 3 is filled with Cu, as shown in FIG. 19B, extra Cu and barrier metal are removed. by polishing through CMP and the surface is planarized. A via plug is thus completed. Subsequently, as shown in FIG. 19C, a secondetching stopper film 9, a secondinterlayer insulation film 10, and a secondcap insulation film 24 are formed sequentially from bottom to top in certain thickness for the use of the wiring. - Then, as shown in FIG. 20A, after a second
reflection preventing film 11 b to be used to control reflection of exposing light is deposited on the secondcap insulation film 24 in a thickness of approximately 50 nm, chemically amplified resist to be used to form a via hole pattern is applied thereon in a thickness of approximately 400 nm, which is subjected to exposure and development through ArF photolithography. A second resistpattern 12 b is thereby formed. - Then, as shown in FIG. 20B, the second
reflection preventing film 11 b, the secondcap insulation film 24, and the secondinterlayer insulation film 10 are etched away sequentially through known dry etching, and awiring trench pattern 13 penetrating through these films is thereby formed. Subsequently, the second resistpattern 12 b and the secondreflection preventing film 11 b are stripped away through oxygen plasma ashing and a wet treatment using an organic separating liquid, and a residue from the dry etching is removed. - Then, as shown in FIG. 21A, after the exposed second
etching stopper film 9 is removed through a dry etching method, the surface of the via pattern at the bottom of thewiring trench pattern 13 is cleaned through sputtering using an Ar gas. Subsequently, the plasma treatment, which is the characteristic of the invention, is performed in situ, that is, within the same chamber and device used for Ar sputtering or in vacuo, that is while maintaining a vacuum. The method, the conditions, the gas kind, etc. are the same as those applied when forming the via plug. - This example will describe a case where the He plasma treatment is performed. After a dangling bond layer is formed through the He plasma treatment on the side surface where SiOC is exposed, as shown in FIG. 21B, a
barrier metal 4, such as tantalum (Ta) and tantalum nitride (TaN), to be used to prevent diffusion of a wiring material and thereby to improve adhesion is formed, for example, in a thickness of approximately 30 nm in situ, that is, within the same chamber and device or in vacuo, that is, while maintaining a vacuum. Subsequently, aseed metal 19 of Cu to be used as the wiring material is formed in a film thickness of approximately 100 nm to make it easier for Cu-plating to be grown. In this instance, it is preferable to set the concentration of nitrogen in tantalum nitride (TaN) to a range from 10 atom % to 50 atom %. - Then, after Cu to be used as a
wiring material 5 is formed through plating and thewiring trench pattern 13 is filled with Cu, as shown in FIG. 21C, extra Cu and barrier metal are removed by polishing through CMP and the surface is planarized. A single damascene structure is thus completed. - With the semiconductor device obtained in this manner, as with the first through third examples above, separation of the barrier metal at the SiOC interface is not acknowledged, which proves that the structure and the plasma treatment of the invention are effective for a process using SiOC.
- The examples above described the cases where the structure and the plasma treatment using a He/H 2 mixed gas or a He gas of the invention are applied to the via first process and the dual hard mask process, which are included in the dual damascene process. It should be appreciated, however, that the invention is not limited to the examples above and can be applied to an arbitrary semiconductor process including the step of depositing a metal film, such as a barrier metal, on the exposed surface of a low dielectric film containing groups having a large molecular structure, such as methyl groups.
- As has been described, according to the manufacturing method of a semiconductor device of the invention, in the damascene process including a step of depositing a metal film, such as a barrier metal, on a trench or a via hole formed in an insulation layer including a low dielectric film, such as MSQ, MHSQ, SiC, SiCN, SiOC, and SICOH, it is possible to avoid a problem that the barrier metal is separated during CMP and scratches are left on the surface of the low dielectric insulation film, or film separation occurs at the barrier metal/low dielectric insulation film interface due to stress resulted from the multi-level interconnection. .
- The reason why is as follows. That is, by forming the structure of the invention through the plasma treatment using a He/H 2 mixed gas or the plasma treatment using a He gas with application of RF bias after the wiring trench . pattern or the via hole is formed as pre-step of depositing the barrier metal, methyl groups on the surface of the low dielectric film, such as MSQ, are replaced by hydrogen, or decomposed to be hydrophilic through reformation, and it is thus possible to improve adhesion to an inorganic material.
Claims (34)
1. A semiconductor device comprising:
an insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents;
a wiring material embedded, through a barrier metal, in one of a via hole and a wiring groove formed in said insulation layer; and
a layer formed between said low dielectric film and said barrier metal and has a relatively low concentration of organic constituents in comparison with said low dielectric film.
2. The semiconductor device according to claim 1 , wherein a concentration of carbon (C) of said layer having the relatively low concentration of organic constituents in comparison with said low dielectric interlayer film is 7 atom % or below.
3. The semiconductor device according to claim 1 , wherein a concentration of carbon (C) of said layer having the relatively low concentration of organic constituents in comparison with said low dielectric interlayer film is 7 atom % or below and 2 atom % or above.
4. The semiconductor device according to claim 1 , wherein said layer having a relatively low concentration of organic constituents in comparison with said low dielectric interlayer film has a film thickness of 25 nm or less.
5. The semiconductor device according to claim 1 , wherein said layer having a relatively low concentration of organic constituents in comparison with said low dielectric interlayer film has a bond of Si and hydrogen (H).
6. The semiconductor device according to claim 1 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.
7. The semiconductor device according to claim 1 , wherein said barrier metal is made of tantalum nitride (TaN) on a side of said low dielectric film and tantalum (Ta) on a side of said wiring material.
8. A manufacturing method of a semiconductor device comprising the steps of:
conducting a plasma treatment using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of a low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond; and then
embedding, through a barrier metal, a wiring material in one of a via hole and a wiring groove formed in an insulation layer including said low dielectric film having a bond of Si and a group made of organic constituents.
9. A manufacturing method of a semiconductor device, comprising the steps of:
forming at least a first interlayer insulation film and a second interlayer insulation film sequentially on a substrate in which a wiring pattern has been formed;
forming a via hole penetrating through said first interlayer insulation film and said second interlayer insulation film using a first resist pattern formed on said second interlayer insulation film;
removing said first resist pattern and then. forming a trench pattern through etching of said second interlayer insulation film using a second resist pattern formed on said second interlayer insulation film;
depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern;
depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and
removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
at least one of said first interlayer insulation film and said second interlayer insulation film is a low dielectric film having a bond of Si and a group made of organic constituents; and
a plasma treatment is performed before said barrier metal is deposited, using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of said low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.
10. A manufacturing method of a semiconductor device, comprising the steps of:
depositing at least a first interlayer insulation film, a second interlayer insulation film, and a hard mask material on a substrate in which a wiring pattern has been formed;
forming a hard mask through etching of said hard mask material using a first resist pattern formed on said hard mask material;
forming a via hole penetrating through said first interlayer insulation film and said second-interlayer insulation film using a second resist pattern formed on said hard mask;
removing said second resist pattern and then forming a trench pattern through etching of said second interlayer insulation film using said hard mask;
depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern; and
depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and
removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
at least one of said first interlayer insulation film, said second interlayer insulation film, and said hard mask is a low dielectric film having a bond of Si and a group made of organic constituents; and
a plasma treatment is performed before said barrier metal is deposited, using one of a gas. capable of replacing at least part of the group made of organic constituents on an exposed surface of said low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.
11. The manufacturing method of a semiconductor device according to claim 8 , wherein said plasma treatment and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.
12. The manufacturing method of a semiconductor device according to claim 9 , wherein said plasma treatment and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.
13. The manufacturing method of a semiconductor device according to claim 10 , wherein said plasma treatment and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.
14. The manufacturing method of a semiconductor device according to claim 8 , further comprising the step of performing sputtering using an Ar gas prior to said plasma treatment, wherein said Ar sputtering, said plasma treatment, and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.
15. The manufacturing method of a semiconductor device according to claim 9 , further comprising the step of performing sputtering using an Ar gas prior to said plasma treatment, wherein said Ar sputtering, said plasma treatment, and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.
16. The manufacturing method of a semiconductor device according to claim 10 , further comprising the step of performing sputtering using an Ar gas prior to said plasma treatment, wherein said Ar sputtering, said plasma treatment, and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.
17. The manufacturing method of a semiconductor device according to claim 8 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.
18. The manufacturing method of a semiconductor device according to claim 9 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.
19. The manufacturing method of a semiconductor device according to claim 10 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.
20. The manufacturing method of a semiconductor device according to claim 8 , wherein a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment.
21. The manufacturing method of a semiconductor device according to claim 9 , wherein a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment.
22. The manufacturing method of a semiconductor device according to claim 10 , wherein a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment.
23. The manufacturing method of a semiconductor device according to claim 8 , wherein one of a noble gas and a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment, and RF bias is applied during said plasma treatment.
24. The manufacturing method of a semiconductor device according to claim 9 , wherein one of a noble gas and a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment, and RF bias is applied during said plasma treatment.
25. The manufacturing method of a semiconductor device according to claim 10 , wherein one of a noble gas and a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment, and RF bias is applied during said plasma treatment.
26. The manufacturing method of a semiconductor device according to claim 20 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn..
27. The manufacturing method of a semiconductor. device according to claim 21 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.
28. The manufacturing method of a semiconductor device according to claim 22 , wherein-said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.
29. The manufacturing method of a semiconductor device according to claim 23 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.
30. The manufacturing method of a semiconductor device according to claim 24 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.
31. The manufacturing method of a semiconductor device according to claim 25 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.
32. The manufacturing method of a semiconductor device according to claim 23 , wherein, in a case where He is used as the gas for said plasma treatment, power of said RF bias is set to a range from 250 W to 400 W both inclusive.
33. The manufacturing method of a semiconductor. device according to claim 24 , wherein, in a case where He is used as the gas for said plasma treatment, power of said RF bias is set to. a range from 250 W to 400 W both inclusive.
34. The manufacturing method of a semiconductor device according to claim 25 , wherein, in a case where He is used as the gas for said plasma treatment, power of said RF bias is set to a range from 250 W to 400 W both inclusive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/359,393 US7563705B2 (en) | 2002-02-14 | 2006-02-23 | Manufacturing method of semiconductor device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002036312 | 2002-02-14 | ||
| JP2002-036312 | 2002-02-14 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/359,393 Division US7563705B2 (en) | 2002-02-14 | 2006-02-23 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20030155657A1 true US20030155657A1 (en) | 2003-08-21 |
Family
ID=27678081
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/365,437 Abandoned US20030155657A1 (en) | 2002-02-14 | 2003-02-13 | Manufacturing method of semiconductor device |
| US11/359,393 Expired - Fee Related US7563705B2 (en) | 2002-02-14 | 2006-02-23 | Manufacturing method of semiconductor device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/359,393 Expired - Fee Related US7563705B2 (en) | 2002-02-14 | 2006-02-23 | Manufacturing method of semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US20030155657A1 (en) |
| KR (1) | KR100516337B1 (en) |
| TW (1) | TWI242259B (en) |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040175922A1 (en) * | 2003-03-07 | 2004-09-09 | Motorola, Inc. | Method for forming a low-k dielectric structure on a substrate |
| US20050017364A1 (en) * | 2003-07-25 | 2005-01-27 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
| US20050085082A1 (en) * | 2003-10-21 | 2005-04-21 | Dougan James N. | Method of forming a low k dielectric in a semiconductor manufacturing process |
| US20050087517A1 (en) * | 2003-10-09 | 2005-04-28 | Andrew Ott | Adhesion between carbon doped oxide and etch stop layers |
| US20050170102A1 (en) * | 2004-01-29 | 2005-08-04 | Semiconductor Leading Edge Technologies, Inc. | Method for manufacturing semiconductor device |
| US20050245076A1 (en) * | 2003-10-03 | 2005-11-03 | Bojkov Christo P | Sealing and protecting integrated circuit bonding pads |
| US20060003571A1 (en) * | 2004-06-30 | 2006-01-05 | Hynix Semiconductor, Inc. | Method for forming contact hole in semiconductor device |
| US20060219660A1 (en) * | 2005-03-31 | 2006-10-05 | Tokyo Electron Limited | Etching method |
| US20070117405A1 (en) * | 2004-02-03 | 2007-05-24 | Nec Electronics Corporation | Method of manufacturing a semiconductor device |
| US7326641B2 (en) | 2003-12-04 | 2008-02-05 | Renesas Technology Corp. | Semiconductor device and method for manufacturing the same |
| US20080057717A1 (en) * | 2006-08-24 | 2008-03-06 | Fujitsu Limited | Semiconductor device manufacturing method |
| US20090317628A1 (en) * | 2007-07-20 | 2009-12-24 | Applied Materials, Inc. | Methods and appartus to prevent contamination of a photoresist layer on a substrate |
| US20100068881A1 (en) * | 2008-09-18 | 2010-03-18 | Kang Joo-Ho | Method of forming metallization in a semiconductor device using selective plasma treatment |
| US20120153483A1 (en) * | 2010-12-20 | 2012-06-21 | Akolkar Rohan N | Barrierless single-phase interconnect |
| US20130203250A1 (en) * | 2011-08-05 | 2013-08-08 | Tokyo Electron Limited | Semiconductor device manufacturing method |
| EP2159840A3 (en) * | 2008-08-29 | 2014-03-12 | Fujitsu Limited | Semiconductor device including an air-bridge wiring and manufacturing method thereof |
| US8865590B2 (en) | 2009-06-16 | 2014-10-21 | Tokyo Electron Limited | Film forming method, pretreatment device, and processing system |
| US20150091411A1 (en) * | 2008-04-23 | 2015-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a device with a cavity |
| US20170011994A1 (en) * | 2003-03-25 | 2017-01-12 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| CN109860102A (en) * | 2017-11-30 | 2019-06-07 | 台湾积体电路制造股份有限公司 | Interconnection structure and forming method thereof |
| US11011413B2 (en) | 2017-11-30 | 2021-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
| US20230073811A1 (en) * | 2019-08-22 | 2023-03-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier-less structures |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100593737B1 (en) | 2004-01-28 | 2006-06-28 | 삼성전자주식회사 | Wiring Method and Wiring Structure of Semiconductor Device |
| KR100539257B1 (en) * | 2004-04-07 | 2005-12-27 | 삼성전자주식회사 | Semiconductor structure for forming pattern and method for forming pattern |
| US7396769B2 (en) * | 2004-08-02 | 2008-07-08 | Lam Research Corporation | Method for stripping photoresist from etched wafer |
| US20060081965A1 (en) * | 2004-10-15 | 2006-04-20 | Ju-Ai Ruan | Plasma treatment of an etch stop layer |
| US7557043B2 (en) * | 2005-06-15 | 2009-07-07 | United Microelectronics Corp. | Method of fabricating the stacked structure and damascene process |
| JP2007180420A (en) * | 2005-12-28 | 2007-07-12 | Fujitsu Ltd | Method of manufacturing semiconductor device and magnetic head |
| JP4675258B2 (en) * | 2006-02-22 | 2011-04-20 | 富士通セミコンダクター株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US7927990B2 (en) * | 2007-06-29 | 2011-04-19 | Sandisk Corporation | Forming complimentary metal features using conformal insulator layer |
| US7884036B1 (en) * | 2007-07-12 | 2011-02-08 | Intermolecular, Inc. | Methods for treating substrates in preparation for subsequent processes |
| KR20100004181A (en) * | 2008-07-03 | 2010-01-13 | 삼성전자주식회사 | Slurry composition for a chemical mechanical polishing, method of preparing the slurry composition and method of polishing an object using the slurry composition |
| US8980751B2 (en) * | 2010-01-27 | 2015-03-17 | Canon Nanotechnologies, Inc. | Methods and systems of material removal and pattern transfer |
| US8420544B2 (en) | 2010-06-03 | 2013-04-16 | United Microelectronics Corp. | Method for fabricating interconnection structure with dry-cleaning process |
| JP2012004401A (en) * | 2010-06-18 | 2012-01-05 | Fujitsu Semiconductor Ltd | Method of manufacturing semiconductor device |
| KR101444527B1 (en) * | 2011-08-05 | 2014-09-24 | 도쿄엘렉트론가부시키가이샤 | Semiconductor device manufacturing method |
| CN104126220B (en) * | 2011-12-20 | 2017-06-20 | 英特尔公司 | Conformal cryogenic seal dielectric diffusion barrier |
| WO2014014907A1 (en) * | 2012-07-16 | 2014-01-23 | Mattson Technology, Inc. | Method for high aspect ratio photoresist removal in pure reducing plasma |
| US8871639B2 (en) * | 2013-01-04 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| US8765546B1 (en) | 2013-06-24 | 2014-07-01 | United Microelectronics Corp. | Method for fabricating fin-shaped field-effect transistor |
| US10008382B2 (en) * | 2015-07-30 | 2018-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a porous low-k structure |
| CN108807262B (en) * | 2017-05-05 | 2022-04-22 | 联芯集成电路制造(厦门)有限公司 | Method for improving interface between low dielectric material layer and silicon oxynitride layer |
| TWI799136B (en) * | 2022-02-15 | 2023-04-11 | 力晶積成電子製造股份有限公司 | Method of manufacturing semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028015A (en) * | 1999-03-29 | 2000-02-22 | Lsi Logic Corporation | Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption |
| US6479884B2 (en) * | 1999-05-13 | 2002-11-12 | International Business Machines Corporation | Interim oxidation of silsesquioxane dielectric for dual damascene process |
| US20020197852A1 (en) * | 2001-06-21 | 2002-12-26 | Ming-Shi Yeh | Method of fabricating a barrier layer with high tensile strength |
| US6518166B1 (en) * | 2001-04-23 | 2003-02-11 | Taiwan Semiconductor Manufacturing Company | Liquid phase deposition of a silicon oxide layer for use as a liner on the surface of a dual damascene opening in a low dielectric constant layer |
| US6531389B1 (en) * | 1999-12-20 | 2003-03-11 | Taiwan Semiconductor Manufacturing Company | Method for forming incompletely landed via with attenuated contact resistance |
| US6723634B1 (en) * | 2002-03-14 | 2004-04-20 | Advanced Micro Devices, Inc. | Method of forming interconnects with improved barrier layer adhesion |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10284600A (en) | 1997-03-31 | 1998-10-23 | Sony Corp | Semiconductor device and fabrication thereof |
| KR20010019643A (en) | 1999-08-28 | 2001-03-15 | 윤종용 | Method for manufacturing multilevel metal interconnections having low dielectric constant insulator |
| SG90747A1 (en) | 1999-09-02 | 2002-08-20 | Applied Materials Inc | Method of pre-cleaning dielectric layers of substrates |
| JP2001223269A (en) | 2000-02-10 | 2001-08-17 | Nec Corp | Semiconductor device and manufacturing method therefor |
| KR100749970B1 (en) | 2000-03-20 | 2007-08-16 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Semiconductor device and method of manufacturing same |
| US6759098B2 (en) * | 2000-03-20 | 2004-07-06 | Axcelis Technologies, Inc. | Plasma curing of MSQ-based porous low-k film materials |
| JP2002118112A (en) | 2000-10-05 | 2002-04-19 | Hitachi Ltd | Manufacturing method of semiconductor device having buried wiring structure |
| JP2002203852A (en) | 2001-01-05 | 2002-07-19 | Mitsubishi Electric Corp | Forming method of insulation film and the insulation film |
-
2003
- 2003-02-13 US US10/365,437 patent/US20030155657A1/en not_active Abandoned
- 2003-02-14 TW TW092103244A patent/TWI242259B/en not_active IP Right Cessation
- 2003-02-14 KR KR10-2003-0009317A patent/KR100516337B1/en active IP Right Grant
-
2006
- 2006-02-23 US US11/359,393 patent/US7563705B2/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028015A (en) * | 1999-03-29 | 2000-02-22 | Lsi Logic Corporation | Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption |
| US6479884B2 (en) * | 1999-05-13 | 2002-11-12 | International Business Machines Corporation | Interim oxidation of silsesquioxane dielectric for dual damascene process |
| US6531389B1 (en) * | 1999-12-20 | 2003-03-11 | Taiwan Semiconductor Manufacturing Company | Method for forming incompletely landed via with attenuated contact resistance |
| US6518166B1 (en) * | 2001-04-23 | 2003-02-11 | Taiwan Semiconductor Manufacturing Company | Liquid phase deposition of a silicon oxide layer for use as a liner on the surface of a dual damascene opening in a low dielectric constant layer |
| US20020197852A1 (en) * | 2001-06-21 | 2002-12-26 | Ming-Shi Yeh | Method of fabricating a barrier layer with high tensile strength |
| US6723634B1 (en) * | 2002-03-14 | 2004-04-20 | Advanced Micro Devices, Inc. | Method of forming interconnects with improved barrier layer adhesion |
Cited By (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6967158B2 (en) * | 2003-03-07 | 2005-11-22 | Freescale Semiconductor, Inc. | Method for forming a low-k dielectric structure on a substrate |
| US20040175922A1 (en) * | 2003-03-07 | 2004-09-09 | Motorola, Inc. | Method for forming a low-k dielectric structure on a substrate |
| US20170011994A1 (en) * | 2003-03-25 | 2017-01-12 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US10304726B2 (en) | 2003-03-25 | 2019-05-28 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US10121693B2 (en) | 2003-03-25 | 2018-11-06 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US9818639B2 (en) * | 2003-03-25 | 2017-11-14 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US9659867B2 (en) * | 2003-03-25 | 2017-05-23 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US7189643B2 (en) * | 2003-07-25 | 2007-03-13 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
| US20050017364A1 (en) * | 2003-07-25 | 2005-01-27 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
| US20050245076A1 (en) * | 2003-10-03 | 2005-11-03 | Bojkov Christo P | Sealing and protecting integrated circuit bonding pads |
| US7262126B2 (en) * | 2003-10-03 | 2007-08-28 | Texas Instruments Incorporated | Sealing and protecting integrated circuit bonding pads |
| US20050087517A1 (en) * | 2003-10-09 | 2005-04-28 | Andrew Ott | Adhesion between carbon doped oxide and etch stop layers |
| US20050085082A1 (en) * | 2003-10-21 | 2005-04-21 | Dougan James N. | Method of forming a low k dielectric in a semiconductor manufacturing process |
| US6902440B2 (en) * | 2003-10-21 | 2005-06-07 | Freescale Semiconductor, Inc. | Method of forming a low K dielectric in a semiconductor manufacturing process |
| WO2005045914A1 (en) * | 2003-10-21 | 2005-05-19 | Freescale Semiconductor, Inc. | Method of forming a low k dielectric in a semiconductor manufacturing process |
| CN100501937C (en) * | 2003-10-21 | 2009-06-17 | 飞思卡尔半导体公司 | Method of forming a low k dielectric in a semiconductor manufacturing process |
| US7326641B2 (en) | 2003-12-04 | 2008-02-05 | Renesas Technology Corp. | Semiconductor device and method for manufacturing the same |
| US20050170102A1 (en) * | 2004-01-29 | 2005-08-04 | Semiconductor Leading Edge Technologies, Inc. | Method for manufacturing semiconductor device |
| US20070117405A1 (en) * | 2004-02-03 | 2007-05-24 | Nec Electronics Corporation | Method of manufacturing a semiconductor device |
| US7615498B2 (en) * | 2004-02-03 | 2009-11-10 | Nec Electronics Corporation | Method of manufacturing a semiconductor device |
| US20060003571A1 (en) * | 2004-06-30 | 2006-01-05 | Hynix Semiconductor, Inc. | Method for forming contact hole in semiconductor device |
| US7402523B2 (en) * | 2005-03-31 | 2008-07-22 | Tokyo Electron Limited | Etching method |
| US20060219660A1 (en) * | 2005-03-31 | 2006-10-05 | Tokyo Electron Limited | Etching method |
| US20080057717A1 (en) * | 2006-08-24 | 2008-03-06 | Fujitsu Limited | Semiconductor device manufacturing method |
| US20090317628A1 (en) * | 2007-07-20 | 2009-12-24 | Applied Materials, Inc. | Methods and appartus to prevent contamination of a photoresist layer on a substrate |
| US9859818B2 (en) * | 2008-04-23 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro-device with a cavity |
| US20150091411A1 (en) * | 2008-04-23 | 2015-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a device with a cavity |
| US10171007B2 (en) | 2008-04-23 | 2019-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a device with a cavity |
| EP2159840A3 (en) * | 2008-08-29 | 2014-03-12 | Fujitsu Limited | Semiconductor device including an air-bridge wiring and manufacturing method thereof |
| US20100068881A1 (en) * | 2008-09-18 | 2010-03-18 | Kang Joo-Ho | Method of forming metallization in a semiconductor device using selective plasma treatment |
| US8865590B2 (en) | 2009-06-16 | 2014-10-21 | Tokyo Electron Limited | Film forming method, pretreatment device, and processing system |
| US20120153483A1 (en) * | 2010-12-20 | 2012-06-21 | Akolkar Rohan N | Barrierless single-phase interconnect |
| US8999841B2 (en) * | 2011-08-05 | 2015-04-07 | Tokyo Electron Limited | Semiconductor device manufacturing method |
| US20130203250A1 (en) * | 2011-08-05 | 2013-08-08 | Tokyo Electron Limited | Semiconductor device manufacturing method |
| CN109860102A (en) * | 2017-11-30 | 2019-06-07 | 台湾积体电路制造股份有限公司 | Interconnection structure and forming method thereof |
| KR20190064400A (en) * | 2017-11-30 | 2019-06-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Interconnect structures and methods of forming the same |
| US10867905B2 (en) | 2017-11-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
| US11011413B2 (en) | 2017-11-30 | 2021-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
| KR102281051B1 (en) | 2017-11-30 | 2021-07-26 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Interconnect structures and methods of forming the same |
| US11177208B2 (en) | 2017-11-30 | 2021-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
| US11545429B2 (en) | 2017-11-30 | 2023-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures having lines and vias comprising different conductive materials |
| US20230073811A1 (en) * | 2019-08-22 | 2023-03-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier-less structures |
| US11848190B2 (en) * | 2019-08-22 | 2023-12-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier-less structures |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200303600A (en) | 2003-09-01 |
| US20060141778A1 (en) | 2006-06-29 |
| KR100516337B1 (en) | 2005-09-22 |
| TWI242259B (en) | 2005-10-21 |
| KR20030068478A (en) | 2003-08-21 |
| US7563705B2 (en) | 2009-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7563705B2 (en) | Manufacturing method of semiconductor device | |
| US7378350B2 (en) | Formation of low resistance via contacts in interconnect structures | |
| US7612452B2 (en) | Method for manufacturing a semiconductor device and semiconductor device | |
| US7253105B2 (en) | Reliable BEOL integration process with direct CMP of porous SiCOH dielectric | |
| US7811926B2 (en) | Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics | |
| US8916232B2 (en) | Method for barrier interface preparation of copper interconnect | |
| US20070059919A1 (en) | Method of manufacturing semiconductor device | |
| US20070059913A1 (en) | Capping layer to reduce amine poisoning of photoresist layers | |
| KR20030089474A (en) | Method of manufacturing semiconductor device and semiconductor device | |
| EP1233449A2 (en) | A method of fabricating a semiconductor device | |
| US7709960B2 (en) | Dual liner capping layer interconnect structure | |
| JP4527948B2 (en) | Semiconductor device and manufacturing method thereof | |
| US7202160B2 (en) | Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same | |
| US20140216342A1 (en) | Processing system for combined metal deposition and reflow anneal for forming interconnect structures | |
| US20050106866A1 (en) | Method of manufacturing semiconductor device | |
| JP3768480B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20080015931A (en) | Prevention of copper delamination in semiconductor device | |
| US7067441B2 (en) | Damage-free resist removal process for ultra-low-k processing | |
| US20070155186A1 (en) | OPTIMIZED SiCN CAPPING LAYER | |
| JP2006073569A (en) | Semiconductor apparatus and its manufacturing method | |
| JP2009117673A (en) | Semiconductor device and manufacturing method thereof | |
| KR100648565B1 (en) | Method for fabricating a semiconductor device having multilevel wiring structure | |
| JP2006147895A (en) | Manufacturing method of semiconductor device | |
| JP2008235811A (en) | Method of manufacturing semiconductor device and the semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TONEGAWA, TAKASHI;ARITA, KOJI;USAMI, TATSUYA;AND OTHERS;REEL/FRAME:013768/0221 Effective date: 20030207 |
|
| STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |