JP3768480B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

【００３８】
表１より、ＡｒエッチングのみのプロセスやＡｒエッチング後にＨｅプラズマ処理を行うプロセスではバリアメタル／ＭＳＱ界面の密着性は十分ではなく、全てのサンプルでバリアメタル層とＣｕ層がバリアメタル／ＭＳＱ界面で剥離したが、Ａｒエッチング後にＨｅ／Ｈ₂プラズマ処理を行うプロセスではバリアメタル／ＭＳＱ界面の密着性は改善され、剥離は生じなかった。この結果から、Ｈ₂を含むガスを用いたプラズマ処理がＭＳＱの密着性改善に効果があることが分かる。
【００３９】
ここで、ＨｅはＨ₂とは異なり反応性は低いが、Ａｒに比べて原子量は小さいため、条件によってはＭＳＱのメチル基のみを除去できる可能性がある。そこで、Ｈｅプラズマ処理に際してＲＦバイアスを徐々に印加して、Ｈｅプラズマのエネルギー大きくしてクリーニングを行ったサンプルを作製し、同様にテープテストを行った。その結果を表２に示す。
【００４０】
【表２】

【００４１】
表２より、ＲＦバイアスを印加しない処理では密着性改善効果は認められないが、ＲＦバイアスを２５０Ｗ以上印加すると剥離が生じなくなっていることから密着性が改善されていることがわかる。これは、ＲＦバイアスを印加しない状態ではＨｅプラズマのエネルギーが小さく、メチル基を分解するには至っていないからと考えられ、反応性のない又は低いガス種を用いた場合でもＲＦバイアスを印加して適度のエネルギーを与えることによってメチル基の分解が可能であることを示している。なお、Ａｒの場合は、ＲＦバイアスを印加しても密着性は改善されないことから、適切なガスを選択しなければ効果が得られないことが分かる。
【００４２】
表１及び表２の結果から、ガス種として反応性の高いガスを含む混合ガス（Ｈｅ／Ｈ₂）又は希ガス（Ｈｅ）を用いることにより、ＭＳＱとバリアメタル界面の密着性が改善されることは分かるが、上記改善効果がＭＳＱ表面のメチル基の除去に起因しているかどうかは不明である。一般に、メチル基は疎水性であり、水素基やダングリングボンドは親水性であることから、メチル基有効に除去されればＭＳＱ表面の親水性の度合いが高まって濡れ性が向上し、接触角が低下することが予想される。そこで、表１と同様のプロセスでクリーニングを行ったサンプルを作製し、ＭＳＱ表面の水との接触角を測定した。その結果を表３及び表４に示す。
【００４３】
【表３】

【００４４】
【表４】

【００４５】
表３より、テープテストでは差が明確ではなかったが、Ａｒエッチングのみのプロセスに比べて、Ａｒエッチング後にＨｅプラズマ処理（ＲＦバイアスなし）を行うプロセスは接触角がわずかに低下しており、Ｈｅプラズマ処理自体に密着性改善効果があることが分かる。また、Ａｒエッチング後にＨｅ／Ｈ₂プラズマ処理を行うプロセスでは更に接触角が低下しており、Ｈ₂ガスの表面改質効果が高いことが分かる。また、表４より、Ｈｅプラズマ処理でもＲＦバイアスを印加することにより接触角が徐々に小さくなっており、特にＲＦバイアス・パワー２５０Ｗ以上ではＨｅ／Ｈ₂プラズマ処理よりも表面改質効果が高いことを示している。
【００４６】
このプラズマ処理による効果を図１を用いて説明すると、未処理の状態ではＭＳＱ表面はメチル基に覆われているが、例えば、ＭＳＱ表面をＨ₂プラズマに曝すことにより、図１（ａ）に示すようにＭＳＱ表面のＳｉ-ＣＨ₃結合がＳｉ-Ｈ結合に置き換わり、分子構造の大きいメチル基が水素に置換されることによってＳｉとバリアメタル金属との距離が短くなり結合力が向上するためと考えられる。また、Ｈｅプラズマ処理の場合は、ＲＦバイアスが大きくなるに従い、図１（ｂ）に示すように、ＭＳＱ表面のＳｉ-ＣＨ₃結合が破壊されてダングリングボンドとなり、Ｓｉとバリアメタルとの結合力が向上するためと考えられる。
【００４７】
以上の実験結果より、本発明の密着性改善効果を得るためには、ガス種としてメチル基を分子構造の小さい基、例えば水素に置換可能な反応性の高いガスを含有する混合ガス、又はＭＳＱを分子ごと分解することなく表面を覆うメチル基のみを分解可能なガスを用いればよく、Ｈｅ、Ｈｅ／Ｈ₂の他に、Ｈ₂とＮｅ、Ａｒ、Ｋｒ、Ｘｅ、Ｒｎ等の希ガスとの混合ガス、アンモニアを含むガス等を用いることができる。
【００４８】
なお、Ｈｅ／Ｈ₂プラズマ処理においてもＲＦバイアスを印加する方法が考えられるが、この場合、水素原子がプラズマに曝される物質の内部にまで浸透してしまい、特に配線材料であるＣｕが露出している状態ではＣｕが脆弱化するという問題が生じるため、水素ガスを用いる場合はＲＦバイアスを最適化する必要がある。
【００４９】
また、Ｈ₂ガスと希ガスの成分比は、Ｈ₂ガスの割合が大きくなると反応性が高くなって制御が困難になり、表面層のみならず内部までメチル基の置換反応が進行してＭＳＱの誘電率が大きくなる恐れがあることから、Ｈ₂等の反応性の高いガスを１〜１０％程度含む成分比（一例として、Ｈ₂とＨｅの場合はＨ₂：４％、Ｈｅ：９６％程度）とすることが好ましい。また、メチル基との反応性を考慮するとアンモニアガスも考えられるが、この場合はアンモニアにより配線材料であるＣｕが窒化されて配線信頼性への影響が懸念されるため、アンモニア濃度、ＲＦバイアス、処理時間等を最適化する必要がある。
【００５０】
また、上記ガスを用いたプラズマ処理により密着性の改善が可能な材料としては、有機成分を含む材料や分子構造の大きい基を含む材料であればよく、ＭＳＱの他に、メチレーテッドハイドロゲンシルセスキオキサン（methylated hydrogen silsesquioxane：ＭＨＳＱ）や炭化シリコン（ＳｉＣ）、炭窒化シリコン（ＳｉＣＮ）、炭素含有シリコン酸化膜（ＳｉＯＣ又はＳｉＣＯＨ）等でもよく、これらの膜をポーラス化したものであってもよい。また、これらの膜を成膜する方法は問わず、ＣＶＤ法、塗布法等、任意の方法を用いることができる。
【００５１】
ＭＳＱ表面のＳｉ-ＣＨ₃結合をＳｉ-Ｈ結合に置き換えることが可能な上記プラズマ処理をダマシンプロセスに適用した場合の概略工程を図２に示す。基板２上に成膜したＭＳＱ１を含む絶縁層にビアホール３を形成すると、表面やビアホール３内壁のＭＳＱ露出面は図２（ａ）に示すようにメチル基で覆われており、ここでＨｅ／Ｈ₂の混合ガスを用いたプラズマ処理を施すと、図２（ｂ）に示すようにメチル基が水素に置換されて表面が親水性になり、無機材料との密着性が向上する。この状態で図２（ｃ）に示すようにバリアメタル４を成膜すればＭＳＱ１とバリアメタル４とは強く結合し、ＣＭＰ法により配線金属をビアホール３内に埋め込んでもＭＳＱ表面やビアホール３内壁のバリアメタル４は剥がれることはなく、多層配線の接続信頼性を向上させることができる。
なお、Ｈｅ／Ｈ₂の混合ガスやＨｅガスを用いたプラズマ処理自体は公知であるが、このプラズマ処理により、ＭＳＱ等の低誘電率膜のメチル基を水素に置換したりメチル基を分解してダングリングボンドを生成し、バリアメタルとの密着性を改善できるという効果は、本願発明者の知見によって得られた新規な事実である。
【００５２】
ＭＳＱ表面のＳｉ-ＣＨ₃結合が破壊されてダングリングボンドを形成することが可能な上記プラズマ処理をダマシンプロセスに適用した場合の概略工程を図３に示す。基板２上に成膜したＭＳＱ１を含む絶縁層に配線トレンチパターン１３を形成すると、表面や配線トレンチパターン１３内壁のＭＳＱ露出面は図３（ａ）に示すようにメチル基で覆われており、ここでＨｅガスを用いてＲＦバイアスを印加したプラズマ処理を施すと、図３（ｂ）に示すようにＳｉ-ＣＨ₃結合が破壊されてダングリングボンド層２５が形成される。
【００５３】
前記ダングリングボンド層２５はプラズマ処理条件により、Ｃの脱離度及びその厚さを変えることができる。そこで図３（ｃ）に示すように、配線トレンチパターン１３にバリアメタル４及び配線材料５であるＣｕを形成したサンプルを準備して、Ｃの脱離度及びその厚さを変化させた場合の、ＣＭＰ法による剥がれ起因のスクラッチを調査した。表５に局所ＥＤＸ法により測定した前記ダングリングボンド層２５のＣ濃度と膜厚に対するスクラッチ欠陥数及び配線間容量の結果を示した。
【００５４】
【表５】

【００５５】
表５より、ダングリングボンド層２５のＣ濃度が低下すると顕著に密着性起因のスクラッチ欠陥が減少することが確認された。特にＣ濃度が７ａｔｍ％以下では良好な結果が得られている。ただ前記ダングリングボンド層２５の膜厚が４１ｎｍでは、配線間容量が上昇していることが確認されており、前記ダングリングボンド層２５のＣ濃度は２ａｔｍ％以上であり、膜厚は２５ｎｍ以下であることが好ましい。
【００５６】
前記ダングリングボンド層２５が形成された配線溝にバリアメタル４としてＴａ単層、ＴａＮ単層、Ｔａ／ＴａＮ積層を形成したサンプルを準備して上記と同様の評価を行なった。表６に各バリアメタルに対するスクラッチ欠陥数の結果を示した。
【００５７】
【表６】

【００５８】
表６より、ダングリングボンド層２５のＣ濃度が７ａｔｍ％の場合では、スクラッチ欠陥数はすべてのバリアメタル構造で良好であるのに対して、ダングリングボンド層２５のＣ濃度が１０ａｔｍ％の場合では、Ｔａ単層のみスクラッチ欠陥数が多く、ダングリングボンド層２５と接するバリアメタル材はＴａＮであることが好ましい。Ｃｕとの濡れ性及び密着性はＴａの方が良好であることから、バリアメタルはＴａ／ＴａＮの積層構造であることが好ましい。
【００５９】
なお、Ｔａ／ＴａＮ積層構造のバリアメタル自体は公知であるが、有機成分からなる基とＳｉとの結合をもつ低誘電率膜を用いたダマシンプロセスにおいて、ダングリングボンド層を形成した配線溝或いはビアホールにバリアメタルを形成する際にＴａ／ＴａＮ積層構造が最適であるという事実は、本願発明者の知見によって得られた新規な事実である。
【００６０】
【実施例】
上記した本発明の実施の形態についてさらに詳細に説明すべく、本発明構造及びプラズマ処理を適用したダマシンプロセスの具体的な実施例について図面を参照して説明する。
［実施例１］
まず、本発明の第１の実施例に係るデュアルダマシンプロセスについて、図４乃至図６を参照して説明する。図４乃至図６は、本発明の構造及びプラズマ処理を適用したビアファーストプロセスの手順を示す工程断面図であり、作図の都合上分図したものである。
【００６１】
まず、図４（ａ）に示すように、公知の方法により、基板２上にＣｕ、Ｃｕ合金等からなる下層配線６を形成した後、ＣＶＤ法、プラズマＣＶＤ法等を用いて、第１エッチングストップ膜７、第１層間絶縁膜８、第２エッチングストップ膜９、第２層間絶縁膜１０を順次、所定の膜厚で形成する。なお、本発明のプラズマ処理の効果が得られる膜としては、メチル基を含むＭＳＱのように分子構造が大きく疎水性を呈する基を含む低誘電率膜であればよく、ＭＨＳＱ、ＳｉＣ、ＳｉＣＮ、ＳｉＯＣ、ＳｉＣＯＨ等やこれらの膜をポーラス化した膜であってもよい。また、この低誘電率膜はＣＶＤや塗布等、どのような方法で成膜された膜であってもよい。
【００６２】
以下の説明では、第２層間絶縁膜１０としてＭＳＱを用いる場合について説明するが、第１層間絶縁膜８又はその両方に上記低誘電率膜を用いてもよい。また、低誘電率膜以外の膜の材料は特に限定されず、エッチングの選択比が得られる材料の組み合わせであればよく、ＳｉＯ₂、ＳｉＮ、ＳｉＯＮ等の中から適宜選択することができる。また、第２層間絶縁膜１０としてＳｉＯ₂以外の材料を用いた場合は、配線のＣＭＰ工程で問題が生じる場合もあるため、その場合は第２層間絶縁膜１０上にキャップ絶縁膜を形成してもよい。
【００６３】
その後、第２層間絶縁膜１０の上に、露光の光の反射を抑制するための反射防止膜１１ａを５０ｎｍ程度堆積した後、ビアホールパターンを形成するための化学増幅型レジストを６００ｎｍ程度塗布し、ＫｒＦフォトリソグラフィーによる露光、現像を行い、第１レジストパターン１２ａを形成する。
【００６４】
次に、図４（ｂ）に示すように、公知のドライエッチングにより反射防止膜１１ａ、第２層間絶縁膜１０、第２エッチングストップ膜９、第１層間絶縁膜８を順次エッチングして、それらを貫通するビアホール３を形成する。その後、酸素プラズマアッシング及び有機剥離液を用いたウェット処理によりレジストパターン１２ａと反射防止膜１１ａとを剥離し、ドライエッチングの残留物を除去する。
【００６５】
次に、図４（ｃ）に示すように、反射防止膜１１ｂを５０ｎｍ程度堆積した後、その上に化学増幅型レジストを６００ｎｍ程度塗布し、ベークを行った後、ＫｒＦフォトリソグラフィーによる露光、現像により配線トレンチパターン形成用の第２レジストパターン１２ｂを形成し、ドライエッチング法により露出した第２反射防止膜１１ｂを除去する。
【００６６】
次に、第２エッチングストップ膜９をエッチングストッパとして第２層間絶縁膜１０をエッチングして配線トレンチパターン１３を形成し、酸素プラズマアッシング及び有機剥離液を用いたウェット処理により第２レジストパターン１２ｂと第２反射防止膜１１ｂとを剥離し、ドライエッチングの残留物を除去する（図５（ａ）参照）。
【００６７】
次に、図５（ｂ）に示すように、露出した第１エッチングストップ膜７をドライエッチング法により除去した後、Ａｒガスを用いたスパッタにより、ビアホール３底部の下層配線６表面のクリーニングを行う。
【００６８】
この状態では、第２層間絶縁膜（ＭＳＱ）１０表面や配線トレンチパターン１３、ビアホール３の側壁はメチル基で覆われており、その上にバリアメタルを形成しても良好な密着性が得られない。そこで、図５（ｃ）に示すように、Ａｒスパッタと同一のチャンバ、装置内又は真空を維持した状態で本発明の特徴であるプラズマ処理を施す。このプラズマ処理としては、Ｈｅ／Ｈ₂の混合ガスを用いたプラズマ処理や、Ｈｅガスを用い所定のＲＦバイアスを印加したプラズマ処理が好ましく、例えば、Ｈｅ／Ｈ₂の混合ガスを用いたプラズマ処理を施すと、表面及びトレンチ側壁に露出したＭＳＱのメチル基が水素に置換されて、バリアメタルとの密着性が向上する。
【００６９】
上記Ａｒスパッタ処理、Ｈｅ／Ｈ₂プラズマ処理、Ｈｅプラズマ処理としては下記に示す条件で行うことが好ましい。
【００７０】
［Ａｒプラズマ処理の条件］
ガス圧：約０．２〜５ｍＴｏｒｒ
ガス種：アルゴン１００％
ＲＦパワーソース：約２００Ｗ〜６００Ｗ
ＲＦバイアスソース：約２００Ｗ〜４００Ｗ
時間：約６０秒
【００７１】
［Ｈ₂／Ｈｅプラズマ処理の条件］
ガス圧：約２０〜１００ｍＴｏｒｒ
ガス種：水素とヘリウムの混合ガス、好ましくは水素４％ヘリウム９６％の混合比を用いる
ＲＦパワーソース：約２００Ｗ〜６００Ｗ
時間：約６０秒
【００７２】
［Ｈｅプラズマ処理の条件］
ガス圧：約２０〜１００ｍＴｏｒｒ
ガス種：ヘリウム１００％
ＲＦパワーソース：約２００Ｗ〜６００Ｗ
ＲＦバイアスソース：約２００Ｗ〜４００Ｗ
時間：約６０秒
【００７３】
上記プラズマ処理でＭＳＱ表面を改質した後、同一チャンバ、装置内又は真空を維持した状態で、図６（ａ）に示すように、配線材料の拡散を防止し、密着性の向上を図るためのタンタル（Ｔａ）、窒化タンタル（ＴａＮ）等のバリアメタル４を、例えば３０ｎｍ程度の厚さで形成し、続いて、配線材料となるＣｕのめっき成長を容易にするためのＣｕのシードメタル１９を１００ｎｍ程度の膜厚で形成する。この時、窒化タンタル（ＴａＮ）中の窒素濃度は１０ａｔｏｍ％〜５０ａｔｏｍ％に設定されていることが望ましい。
【００７４】
その後、図６（ｂ）に示すように、配線材料５となるＣｕをめっき法により形成して配線トレンチパターン１３、ビアホール３内をＣｕで埋設した後、図６（ｃ）に示すように、ＣＭＰ法を用いて余分なＣｕを研磨して表面を平坦化することにより、デュアルダマシン構造が完成する。
【００７５】
上記方法で形成した半導体装置では、従来例で示したようなＭＳＱ界面でのバリアメタルの剥がれやＭＳＱ表面のスクラッチは認められず、本発明の構造及びプラズマ処理がＭＳＱを用いたプロセスに効果があることを確認した。
［実施例２］
次に、本発明の第２の実施例に係るデュアルダマシンプロセスについて、図７乃至図１０を参照して説明する。図７乃至図１０は、本発明の構造及びプラズマ処理を適用したデュアルハードマスクプロセスの手順を示す工程断面図であり、作図の都合上分図したものである。
【００７６】
まず、図７（ａ）に示すように、前記した第１の実施例と同様に、公知の方法により、基板２上にＣｕ、Ｃｕ合金等からなる下層配線６を形成した後、ＣＶＤ法、プラズマＣＶＤ法等を用いて、第１エッチングストップ膜７、第１層間絶縁膜８、第２エッチングストップ膜９、第２層間絶縁膜１０を順次形成する。次に、本実施例では、その上に配線トレンチパターンのエッチングマクスとなる第１ハードマスク膜１６及び第２ハードマスク膜１７を堆積する。
【００７７】
なお、本実施例でも、第２層間絶縁膜１０としてＭＳＱを用いる場合について説明するが、第２層間絶縁膜１０に代えて、又は第２層間絶縁膜１０と共に、第１層間絶縁膜８、第１ハードマスク膜１６、第２ハードマスク膜１７の少なくとも一つにＭＳＱやＭＨＳＱ、ＳｉＣ、ＳｉＣＮ、ＳｉＯＣ、ＳｉＣＯＨ等の有機成分からなる基とＳｉとの結合を含む低誘電率膜を用いてもよい。
【００７８】
その後、第２ハードマスク膜１７上に、反射防止膜１１ａを５０ｎｍ程度、化学増幅型レジストを６００ｎｍ程度塗布し、ＫｒＦフォトリソグラフィーによる露光、現像を行い、第１レジストパターン１２ａを形成する。
【００７９】
次に、図７（ｂ）に示すように、公知のドライエッチングにより、第１レジストパターン１２ａを用いて第１反射防止膜１１ａおよび第２ハードマスク膜１７をエッチングして、配線トレンチパターンをエッチングするための開口を形成する。その後、酸素プラズマアッシング及び有機剥離液を用いたウェット処理によりレジストパターン１２ａと反射防止膜１１ａとを剥離し、ドライエッチングの残留物を除去する。
【００８０】
次に、図７（ｃ）に示すように、第２反射防止膜１１ｂを５０ｎｍ程度、化学増幅型レジストを６００ｎｍ程度塗布し、ベークを行った後、ＫｒＦフォトリソグラフィーによる露光、現像により、第２ハードマスク膜１７のエッチング領域内側に開口を有するビアホール形成用の第２レジストパターン１２ｂを形成する。
【００８１】
次に、図８（ａ）に示すように、第２レジストパターン２ｂをマスクとして公知のドライエッチングにより、第２反射防止膜１１ｂ、第１ハードマスク膜１６、第２層間絶縁膜１０、第２エッチングストップ膜９、第１層間絶縁膜８をエッチングし、それらを貫通するビアホール３を形成する。
【００８２】
その後、図８（ｂ）に示すように、酸素プラズマアッシング及び有機剥離液を用いたウェット処理により、第２レジストパターン１２ｂと第２反射防止膜１１ｂとを剥離し、ドライエッチングの残留物を除去する。
【００８３】
次に、図８（ｃ）に示すように、第２ハードマスク膜１７をマスクとして公知のドライエッチング法を用いて、第１ハードマスク膜１６及び第２層間絶縁膜１０をエッチングして、配線トレンチパターン１３を形成する。
【００８４】
次に、図９（ａ）に示すように、露出した第１エッチングストップ膜７をドライエッチング法により除去した後、Ａｒガスを用いたスパッタにより、ビアホール３底部の下層配線６表面のクリーニングを行い、続いて、図９（ｂ）に示すように、Ａｒスパッタと同一のチャンバ、装置内又は真空を維持した状態で本発明の特徴であるプラズマ処理を施す。このプラズマ処理の方法、条件、ガス種等は前記した第１の実施例と同様である。
【００８５】
上記プラズマ処理でＭＳＱ表面を改質した後、同一チャンバ、装置内又は真空を維持した状態で、図９（ｃ）に示すように、配線材料の拡散を防止し、密着性の向上を図るためのタンタル（Ｔａ）、窒化タンタル（ＴａＮ）等のバリアメタル４を、例えば３０ｎｍ程度の厚さで形成し、続いて、配線材料となるＣｕのめっき成長を容易にするためのＣｕのシードメタル１９を１００ｎｍ程度の膜厚で形成する。この時、窒化タンタル（ＴａＮ）中の窒素濃度は１０ａｔｏｍ％〜５０ａｔｏｍ％に設定されていることが望ましい。
【００８６】
その後、図１０（ａ）に示すように、配線材料５となるＣｕをめっき法により形成し、配線トレンチパターン１３及びビアホール３内をＣｕで埋設した後、図１０（ｂ）に示すように、ＣＭＰ法を用いて余分なＣｕを研磨して表面を平坦化することにより、デュアルダマシン構造が完成する。
【００８７】
なお、層間絶縁膜を全て有機膜で形成した場合には、図８（ａ）の工程で第２レジストパターン１２ｂを用いて、第２反射防止膜１１ｂ、第１ハードマスク膜１６、第２層間絶縁膜１０、第２エッチングストップ膜９までエッチングし、図８（ｃ）の工程で、第２ハードマスク膜１７を用いて、第１ハードマスク膜１６、第２層間絶縁膜１０をエッチングして配線トレンチパターン１３を形成すると同時に、第１層間絶縁膜８をエッチングして第１エッチングストップ膜７まで貫通するビアホール３を形成する構成とすることもできる。
【００８８】
このようにして形成した半導体装置は、前記した第１の実施例と同様に、ＭＳＱ界面でのバリアメタルの剥がれやＭＳＱ表面のスクラッチは認められず、本発明の構造及びプラズマ処理がＭＳＱを用いたプロセスに効果があることを確認した。
［実施例３］
まず、本発明の第３の実施例に係るシングルダマシンプロセスについて、図１１乃至図１４を参照して説明する。図１１乃至図１４は、本発明の構造及びプラズマ処理を適用したシングルダマシンプロセスの手順を示す工程断面図であり、作図の都合上分図したものである。
【００８９】
まず、図１１（ａ）に示すように、下層配線６上に、ＣＶＤ法、プラズマＣＶＤ法等を用いて、第１エッチングストップ膜７、第１層間絶縁膜８を順次、所定の膜厚で形成する。その後、第１層間絶縁膜８の上に、露光の光の反射を抑制するための反射防止膜１１ａを５０ｎｍ程度堆積した後、ビアホールパターンを形成するための化学増幅型レジストを５００ｎｍ程度塗布し、ＡｒＦフォトリソグラフィーによる露光、現像を行い、第１レジストパターン１２ａを形成する。
【００９０】
なお、本発明のプラズマ処理の効果が得られる膜としては、メチル基を含むＭＳＱのように分子構造が大きく疎水性を呈する基を含む低誘電率膜であればよく、ＭＨＳＱ、ＳｉＣ、ＳｉＣＮ、ＳｉＯＣ、ＳｉＣＯＨ等やこれらの膜をポーラス化した膜であってもよい。また、この低誘電率膜はＣＶＤや塗布等、どのような方法で成膜された膜であってもよい。
【００９１】
以下の説明では、第１層間絶縁膜８及び第２層間絶縁膜１０としてＭＳＱを用いる場合について説明するが、第１層間絶縁膜８又はその両方に上記低誘電率膜を用いてもよい。また、低誘電率膜以外の膜の材料は特に限定されず、エッチングの選択比が得られる材料の組み合わせであればよく、ＳｉＯ₂、ＳｉＮ、ＳｉＯＮ、ＳｉＣ、ＳｉＣＮ等の中から適宜選択することができる。
【００９２】
次に、図１１（ｂ）に示すように、公知のドライエッチングにより反射防止膜１１ａ、第１層間絶縁膜８を順次エッチングして、それらを貫通するビアホール３を形成する。その後、酸素プラズマアッシング及び有機剥離液を用いたウェット処理によりレジストパターン１２ａと反射防止膜１１ａとを剥離し、ドライエッチングの残留物を除去する。
【００９３】
次に、図１１（ｃ）に示すように、露出した第１エッチングストップ膜７をドライエッチング法により除去した後、Ａｒガスを用いたスパッタにより、ビアホール３底部の下層配線６表面のクリーニングを行った後、Ａｒスパッタと同一のチャンバ、装置内又は真空を維持した状態で本発明の特徴であるプラズマ処理を施す。このプラズマ処理の方法、条件、ガス種等は前記した第１及び２の実施例と同様である。
【００９４】
本実施例ではＨｅプラズマ処理を適用した場合について説明する。Ｈｅプラズマ処理でＭＳＱ表面にダングリングボンド層を形成した後、同一チャンバ、装置内又は真空を維持した状態で、図１２（ａ）に示すように、配線材料の拡散を防止し、密着性の向上を図るためのタンタル（Ｔａ）、窒化タンタル（ＴａＮ）等のバリアメタル４を、例えば３０ｎｍ程度の厚さで形成し、続いて、配線材料となるＣｕのめっき成長を容易にするためのＣｕのシードメタル１９を１００ｎｍ程度の膜厚で形成する。この時、窒化タンタル（ＴａＮ）中の窒素濃度は１０ａｔｏｍ％〜５０ａｔｏｍ％に設定されていることが望ましい。
【００９５】
その後、配線材料５となるＣｕをめっき法により形成して、ビアホール３内をＣｕで埋設した後、図１２（ｂ）に示すように、ＣＭＰ法を用いて余分なＣｕを研磨して表面を平坦化することにより、ビアプラグが完成する。その後、図１２（ｃ）に示すように上層配線用として第２エッチングストップ膜９、第２層間絶縁膜１０を所定の膜厚で順次形成する。
次に図１３（ａ）に示すように、第２層間絶縁膜１０の上に、露光の光の反射を抑制するための反射防止膜１１ｂを５０ｎｍ程度堆積した後、ビアホールパターンを形成するための化学増幅型レジストを４００ｎｍ程度塗布し、ＡｒＦフォトリソグラフィーによる露光、現像を行い、第２レジストパターン１２ｂを形成する。
【００９６】
次に、図１３（ｂ）に示すように、公知のドライエッチングにより反射防止膜１１ｂ、第２層間絶縁膜１０を順次エッチングして、それらを貫通する配線トレンチパターン１３を形成する。その後、酸素プラズマアッシング及び有機剥離液を用いたウェット処理によりレジストパターン１２ｂと反射防止膜１１ｂとを剥離し、ドライエッチングの残留物を除去する。
【００９７】
次に、図１４（ａ）に示すように、露出した第２エッチングストップ膜９をドライエッチング法により除去した後、Ａｒガスを用いたスパッタにより、配線トレンチパターン１３底部のビアパターン表面のクリーニングを行った後、Ａｒスパッタと同一のチャンバ、装置内又は真空を維持した状態で本発明の特徴であるプラズマ処理を施す。このプラズマ処理の方法、条件、ガス種等は前記したビアプラグ形成時と同様である。
【００９８】
本実施例ではＨｅプラズマ処理を適用した場合について説明する。Ｈｅプラズマ処理でＭＳＱ表面にダングリングボンド層を形成した後、同一チャンバ、装置内又は真空を維持した状態で、図１４（ｂ）に示すように、配線材料の拡散を防止し、密着性の向上を図るためのタンタル（Ｔａ）、窒化タンタルＴａＮ等のバリアメタル４を、例えば３０ｎｍ程度の厚さで形成し、続いて、配線材料となるＣｕのめっき成長を容易にするためのＣｕのシードメタル１９を１００ｎｍ程度の膜厚で形成する。この時、窒化タンタル（ＴａＮ）中の窒素濃度は１０ａｔｏｍ％〜５０ａｔｏｍ％に設定されていることが望ましい。
【００９９】
その後、配線材料５となるＣｕをめっき法により形成して、配線トレンチパターン１３内をＣｕで埋設した後、図１４（ｃ）に示すように、ＣＭＰ法を用いて余分なＣｕを研磨して表面を平坦化することにより、シングルダマシン構造を完成する。
【０１００】
このようにして形成した半導体装置は、前記した第１及び２の実施例と同様に、ＭＳＱ界面でのバリアメタルの剥がれやＭＳＱ表面のスクラッチは認められず、本発明の構造及びプラズマ処理がＭＳＱを用いたプロセスに効果があることを確認した。
［実施例４］
まず、本発明の第４の実施例に係るシングルダマシンプロセスについて、図１５乃至図１８を参照して説明する。図１５乃至図１８は、本発明の構造及びプラズマ処理を適用したシングルダマシンプロセスの手順を示す工程断面図であり、作図の都合上分図したものである。
【０１０１】
まず、図１５（ａ）に示すように、下層配線６上に、ＣＶＤ法、プラズマＣＶＤ法等を用いて、第１エッチングストップ膜７、第１層間絶縁膜８、第１キャップ絶縁膜２３を順次、所定の膜厚で形成する。その後、第１キャップ絶縁膜２３の上に、露光の光の反射を抑制するための反射防止膜１１ａを５０ｎｍ程度堆積した後、ビアホールパターンを形成するための化学増幅型レジストを５００ｎｍ程度塗布し、ＡｒＦフォトリソグラフィーによる露光、現像を行い、第１レジストパターン１２ａを形成する。
【０１０２】
なお、本発明のプラズマ処理の効果が得られる膜としては、メチル基を含むＭＳＱのように分子構造が大きく疎水性を呈する基を含む低誘電率膜であればよく、ＭＨＳＱ、ＳｉＣ、ＳｉＣＮ、ＳｉＯＣ、ＳｉＣＯＨ等やこれらの膜をポーラス化した膜であってもよい。また、この低誘電率膜はＣＶＤや塗布等、どのような方法で成膜された膜であってもよい。
【０１０３】
本実施例では、第１層間絶縁膜８及び第２層間絶縁膜１０としてＳｉＯＣを用いる場合について説明するが、第１層間絶縁膜８又はその両方に上記低誘電率膜を用いてもよい。また、低誘電率膜以外の膜の材料は特に限定されず、エッチングの選択比が得られる材料の組み合わせであればよく、ＳｉＯ₂、ＳｉＮ、ＳｉＯＮ、ＳｉＣ、ＳｉＣＮ等の中から適宜選択することができる。
【０１０４】
次に、図１５（ｂ）に示すように、公知のドライエッチングにより反射防止膜１１ａ、第1キャップ絶縁膜２３、第１層間絶縁膜８を順次エッチングして、それらを貫通するビアホール３を形成する。その後、酸素プラズマアッシング及び有機剥離液を用いたウェット処理によりレジストパターン１２ａと反射防止膜１１ａとを剥離し、ドライエッチングの残留物を除去する。
【０１０５】
次に、図１５（ｃ）に示すように、露出した第１エッチングストップ膜７をドライエッチング法により除去した後、Ａｒガスを用いたスパッタにより、ビアホール３底部の下層配線６表面のクリーニングを行った後、Ａｒスパッタと同一のチャンバ、装置内又は真空を維持した状態で本発明の特徴であるプラズマ処理を施す。このプラズマ処理の方法、条件、ガス種等は前記した第１及至３の実施例と同様である。
【０１０６】
本実施例ではＨｅプラズマ処理を適用した場合について説明する。Ｈｅプラズマ処理でＳｉＯＣの露出した側面にダングリングボンド層を形成した後、同一チャンバ、装置内又は真空を維持した状態で、図１６（ａ）に示すように、配線材料の拡散を防止し、密着性の向上を図るためのタンタル（Ｔａ）、窒化タンタル（ＴａＮ）等のバリアメタル４を、例えば３０ｎｍ程度の厚さで形成し、続いて、配線材料となるＣｕのめっき成長を容易にするためのＣｕのシードメタル１９を１００ｎｍ程度の膜厚で形成する。この時、窒化タンタル（ＴａＮ）中の窒素濃度は１０ａｔｏｍ％〜５０ａｔｏｍ％に設定されていることが望ましい。
【０１０７】
その後、配線材料５となるＣｕをめっき法により形成して、ビアホール３内をＣｕで埋設した後、図１６（ｂ）に示すように、ＣＭＰ法を用いて余分なＣｕを研磨して表面を平坦化することにより、ビアプラグが完成する。その後、図１６（ｃ）に示すように上層配線用として第２エッチングストップ膜９、第２層間絶縁膜１０、第２キャップ絶縁膜２４を所定の膜厚で順次形成する。
次に図１７（ａ）に示すように、第２キャップ絶縁膜２４の上に、露光の光の反射を抑制するための反射防止膜１１ｂを５０ｎｍ程度堆積した後、ビアホールパターンを形成するための化学増幅型レジストを４００ｎｍ程度塗布し、ＡｒＦフォトリソグラフィーによる露光、現像を行い、第２レジストパターン１２ｂを形成する。
次に、図１７（ｂ）に示すように、公知のドライエッチングにより反射防止膜１１ｂ、第２キャップ絶縁膜２４、第２層間絶縁膜１０を順次エッチングして、それらを貫通する配線トレンチパターン１３を形成する。その後、酸素プラズマアッシング及び有機剥離液を用いたウェット処理によりレジストパターン１２ｂと反射防止膜１１ｂとを剥離し、ドライエッチングの残留物を除去する。
【０１０８】
次に、図１８（ａ）に示すように、露出した第２エッチングストップ膜９をドライエッチング法により除去した後、Ａｒガスを用いたスパッタにより、配線トレンチパターン１３底部のビアパターン表面のクリーニングを行った後、Ａｒスパッタと同一のチャンバ、装置内又は真空を維持した状態で本発明の特徴であるプラズマ処理を施す。このプラズマ処理の方法、条件、ガス種等は前記したビアプラグ形成時と同様である。
【０１０９】
本実施例ではＨｅプラズマ処理を適用した場合について説明する。Ｈｅプラズマ処理でＳｉＯＣの露出した側面にダングリングボンド層を形成した後、同一チャンバ、装置内又は真空を維持した状態で、図１８（ｂ）に示すように、配線材料の拡散を防止し、密着性の向上を図るためのタンタル（Ｔａ）、窒化タンタル（ＴａＮ）等のバリアメタル４を、例えば３０ｎｍ程度の厚さで形成し、続いて、配線材料となるＣｕのめっき成長を容易にするためのＣｕのシードメタル１９を１００ｎｍ程度の膜厚で形成する。この時、窒化タンタル（ＴａＮ）中の窒素濃度は１０ａｔｏｍ％〜５０ａｔｏｍ％に設定されていることが望ましい。
【０１１０】
その後、配線材料５となるＣｕをめっき法により形成して、配線トレンチパターン１３内をＣｕで埋設した後、図１８（ｃ）に示すように、ＣＭＰ法を用いて余分なＣｕを研磨して表面を平坦化することにより、シングルダマシン構造を完成する。
【０１１１】
このようにして形成した半導体装置は、前記した第１及至３の実施例と同様に、ＳｉＯＣ界面でのバリアメタルの剥がれは認められず、本発明の構造及びプラズマ処理がＳｉＯＣを用いたプロセスに効果があることを確認した。
【０１１２】
なお、上記各実施例では、本発明の構造及びＨｅ／Ｈ₂の混合ガス又はＨｅガスを用いたプラズマ処理を、デュアルダマシンプロセスであるビアファーストプロセスやデュアルハードマスクプロセス、及びシングルダマシンプロセスに適用した場合について説明したが、本発明は上記実施例に限定されるものではなく、メチル基等の分子構造の大きい基を含む低誘電率膜の露出面にバリアメタル等の金属膜の成膜を行う工程を含む任意の半導体プロセスに適用することができる。
【０１１３】
【発明の効果】
以上説明したように、本発明の半導体装置の製造方法によれば、ＭＳＱ、ＭＨＳＱ、ＳｉＣ、ＳｉＣＮ、ＳｉＯＣ、ＳｉＣＯＨ等の低誘電率膜を含む絶縁層に形成したトレンチやビアホールにバリアメタル等の金属膜を成膜する工程を含むダマシンプロセスにおいて、ＣＭＰ時にバリアメタルが剥がれて上記低誘電率絶縁膜表面にスクラッチが発生したり、多層化によるストレスに起因して、バリアメタル／低誘電率絶縁膜界面での膜剥がれが生じるという問題を回避することができる。
【０１１４】
その理由は、配線トレンチパターンやビアホール形成後、バリアメタルの成膜の前工程として、Ｈｅ／Ｈ₂の混合ガスを用いたプラズマ処理やＨｅガスを用いＲＦバイアスを印加したプラズマ処理を実施し、本発明の構造を形成することにより、ＭＳＱ等の低誘電率膜表面のメチル基を水素に置換又は分解して親水性に改質し、無機材料との密着性を向上させることができるからである。
【図面の簡単な説明】
【図１】本発明のプラズマ処理のメカニズムを模式的に示す図である。
【図２】本発明のプラズマ処理を含む製造工程の一部を示す工程断面図である。
【図３】本発明の構造及びプラズマ処理を含む製造工程の一部を示す工程断面図である。
【図４】本発明の第１の実施例に係るビアファーストプロセスの手順を示す工程断面図である。
【図５】本発明の第１の実施例に係るビアファーストプロセスの手順を示す工程断面図である。
【図６】本発明の第１の実施例に係るビアファーストプロセスの手順を示す工程断面図である。
【図７】本発明の第２の実施例に係るデュアルハードマスクプロセスの手順を示す工程断面図である。
【図８】本発明の第２の実施例に係るデュアルハードマスクプロセスの手順を示す工程断面図である。
【図９】本発明の第２の実施例に係るデュアルハードマスクプロセスの手順を示す工程断面図である。
【図１０】本発明の第２の実施例に係るデュアルハードマスクプロセスの手順を示す工程断面図である。
【図１１】本発明の第３の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１２】本発明の第３の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１３】本発明の第３の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１４】本発明の第３の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１５】本発明の第４の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１６】本発明の第４の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１７】本発明の第４の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１８】本発明の第４の実施例に係るシングルダマシンプロセスの手順を示す工程断面図である。
【図１９】従来のビアファーストプロセスの手順を示す工程断面図である。
【図２０】従来のビアファーストプロセスの手順を示す工程断面図である。
【図２１】従来のビアファーストプロセスの手順を示す工程断面図である。
【符号の説明】
１ ＭＳＱ
２ 基板
３ ビアホール
４ バリアメタル
５ 配線材料
６ 下層配線
７ 第１エッチングストップ膜
８ 第１層間絶縁膜
９ 第２エッチングストップ膜
１０ 第２層間絶縁膜（ＭＳＱ）
１１ａ 第１反射防止膜
１１ｂ 第２反射防止膜
１２ａ 第１レジストパターン
１２ｂ 第２レジストパターン
１３ 配線トレンチパターン
１４ Ａｒ
１５ Ｈｅ／Ｈ₂プラズマ
１６ 第１ハードマスク膜
１７ 第２ハードマスク膜
１８ 第２層間絶縁膜
１９ シードメタル
２０ 剥がれ
２１ スクラッチ
２２ Ｈｅプラズマ
２３ 第１キャップ絶縁膜
２４ 第２キャップ絶縁膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly to a barrier metal in a damascene process using a low dielectric constant film having a bond between Si and a group composed of an organic component such as MSQ and the low dielectric constant film. The present invention relates to an interface structure and a surface treatment method thereof.
[0002]
[Prior art]
In recent years, with the high integration of semiconductor devices and the reduction in chip size, miniaturization of wiring and multilayer wiring have been promoted, and as a method of forming a multilayer wiring structure, Cu is simultaneously embedded in via holes and wiring trench patterns. A so-called damascene process is generally performed in which a wiring is formed by flattening by a CMP (Chemical Mechanical Polishing) method. In this damascene process, it is possible to increase the density of wiring patterns. However, if the wiring patterns are close to each other, a problem of wiring delay due to parasitic capacitance between the wiring patterns occurs. Therefore, reduction of wiring capacitance is an important issue in order to improve wiring delay.
[0003]
As a method for reducing the wiring capacitance, the conventionally used SiO 2 layer is used as an interlayer insulating film. ₂ A method of using a material having a low dielectric constant instead of the insulating film of the system has been studied. Here, a conventional damascene process using a low dielectric constant film as an interlayer insulating film will be described with reference to the drawings. 19 to 21 are process cross-sectional views showing the procedure of a via first process which is one form of a conventional damascene process.
[0004]
First, as shown in FIG. 19A, a first etching stop film 7 that prevents diffusion of Cu and serves as an etching stopper for a via hole is formed on a substrate 2 on which a lower wiring 6 made of Cu is formed. ₂ A first interlayer insulating film 8 comprising: a second etching stop film 9 serving as an etching stopper for a wiring trench pattern; hydrogen silsesquioxane (hereinafter referred to as HSQ); and methyl silsesquioxane (hereinafter referred to as MSQ). The second interlayer insulating film 18 made of a low dielectric constant film is sequentially deposited. Then, a first antireflection film 11a and a photoresist are sequentially applied on the second interlayer insulating film 18, and a first resist pattern 12a for forming the via hole 3 is formed by exposure and development.
[0005]
Next, as shown in FIG. 19B, the first antireflection film 11a, the second interlayer insulating film 18, and the second etching stop film 9 are formed using a known dry etching technique using the first resist pattern 12a as a mask. The first interlayer insulating film 8 is sequentially etched to form a via hole 3 penetrating therethrough.
[0006]
Next, after removing the first resist pattern 12a and the first antireflection film 11a, as shown in FIG. 19C, a second antireflection film 11b and a photoresist are sequentially applied, and exposed and developed to form a wiring trench. A second resist pattern 12b for etching the pattern is formed. Thereafter, the second antireflection film 11b and the second interlayer insulating film 18 are sequentially etched using a known dry etching technique to form a wiring trench pattern 13 (see FIG. 20A).
[0007]
Then, as shown in FIG. 20B, after removing the first etching stop film 7 on the upper part of the lower layer wiring 6, as shown in FIG. 20C, a barrier metal 4 serving as a base of the wiring material is formed. Then, a wiring material 5 such as Cu is embedded in the wiring trench pattern 13 and the via hole 3, and the surface is flattened by a CMP method to form a dual damascene structure (see FIGS. 21A and 21B).
[0008]
In the above-described conventional damascene process, when HSQ is used as the second interlayer insulating film 18, since HSQ is an inorganic low dielectric constant film, a barrier metal, silicon oxide film, silicon, which is also an inorganic material, is used. Adhesion with the nitride film was good, and there was no problem that these inorganic materials were peeled off at the HSQ interface. However, when a low dielectric constant film having a bond made of an organic component such as MSQ and Si is used as the second interlayer insulating film 18, the adhesion with an inorganic material, particularly a barrier metal, is poor, and FIG. As shown in (b), the barrier metal is peeled off from the MSQ low dielectric constant film during CMP, and scratches 21 are generated on the surface of the MSQ low dielectric constant film, or stress is generated due to multilayering, resulting in poor adhesion. There was a problem that film peeling 20 occurred at the / MSQ interface. However, since the MSQ-based low dielectric constant film has a low dielectric constant compared to HSQ, it is promising as a next-generation interlayer film. Therefore, it is very important to resolve the adhesion between the MSQ-based low dielectric constant film and the barrier metal interface. .
[0009]
Thus, the adhesion between the barrier metal 4 differs between the HSQ and the MSQ. The HSQ has a structure in which oxygen or hydrogen is bonded to a silicon atom, whereas the MSQ has a methyl group to lower the dielectric constant. It is considered that the organic component having a large molecular structure as described above is included, and the organic component at the MSQ interface hinders the bond between the barrier metal 4 such as tantalum (Ta) or tantalum nitride (TaN) and Si.
[0010]
Therefore, in order to prevent such peeling, a structure for protecting the groove sidewall after the groove formation has been studied. For example, in Patent Document 1, the groove pattern formed in the low dielectric constant interlayer film is formed on Si. _Three N _Four And SiO ₂ A method of forming the side wall to protect the side wall is disclosed. Also, a method of performing ozone treatment, UV ozone treatment or oxygen plasma treatment after the MSQ film formation has been studied, and Patent Document 2 discloses that the surface of the interlayer insulating film is excessively irradiated with a charged beam ionized with oxygen gas. A method for modifying a silicon oxide film or silicon dioxide film containing silicon is disclosed.
[0011]
[Patent Document 1]
JP-A-10-284600 (FIGS. 1 to 3)
[Patent Document 2]
JP 2001-223269 A (FIGS. 5 to 7)
[0012]
[Problems to be solved by the invention]
However, in the method of Patent Document 1, an increase in dielectric constant is unavoidable when a thick film is formed, and a deterioration in adhesion due to a pinhole is unavoidable when a thin film is formed. In order to prevent the peeling due to the low adhesion, a method for improving the adhesion by performing various surface treatments on the surface of the MSQ after film formation has been studied. For example, in the manufacture of a semiconductor device, cleaning by sputtering using Ar gas is performed in various processes, and the surface of the lower layer wiring 6 at the bottom of the via hole 3 is cleaned after forming the wiring trench pattern 13 and before forming the barrier metal 4. In some cases, an Ar sputtering process is performed in order to make it easier. However, since the Ar sputtering process only etches the material to be sputtered, the MSQ surface modification effect is not recognized.
[0013]
On the other hand, in the method of performing ozone treatment, UV ozone treatment, or oxygen plasma treatment described in Patent Document 2, moisture penetrates into the film, the dielectric constant of the insulating film increases, and the film surface is left to produce a residue. A problem occurs.
[0014]
In order to reduce the wiring capacitance in this way, it is essential to use a low dielectric constant film containing an organic component such as MSQ as an interlayer insulating film. However, the low dielectric constant film and an inorganic material, particularly a barrier metal, The deterioration of reliability due to poor adhesion is serious, and there is a development of a structure that can improve the adhesion between the low dielectric constant film and the barrier metal, and a process that can modify the surface of the low dielectric constant film. It has been demanded. This problem is not limited to the above-mentioned via first dual damascene process, other damascene processes such as a dual hard mask process and single damascene, and other processes using a low dielectric constant film having a bond between an organic component group and Si. It occurs in the same way.
[0015]
The present invention has been made in view of the above problems, and its main purpose is the interface between a low dielectric constant film having a bond between Si and a group consisting of organic components such as MSQ in a damascene process and a barrier metal. Structure of a semiconductor device capable of improving the adhesion of the metal and its manufacturing method, in particular, removing organic components from the interface between the low dielectric constant interlayer film and the barrier metal, thereby improving the adhesion with an inorganic material such as a barrier metal An object of the present invention is to provide a structure of a semiconductor device and a method for manufacturing the semiconductor device.
[0017]
In order to achieve the above object, the structure of the semiconductor device of the present invention is a via hole formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, or a wiring groove through a barrier metal. In the semiconductor device including the step of embedding the wiring material, the region of the low dielectric constant film in contact with the barrier metal is a region having a concentration of organic component relatively lower than that in the low dielectric constant interlayer film. The carbon (C) concentration of the low concentration region layer is 7 atm% or less. It is a feature.
[0018]
In the semiconductor device of the present invention, the carbon (C) concentration of the layer in which the organic component concentration is relatively lower than that of the low dielectric constant interlayer film is preferably 7 atm% or less and preferably 2 atm% or more. .
[0019]
In order to achieve the above object, the structure of the semiconductor device of the present invention is a via hole formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, or a wiring groove through a barrier metal. In the semiconductor device including the step of embedding the wiring material, the region of the low dielectric constant film in contact with the barrier metal is a region having a concentration of organic component relatively lower than that in the low dielectric constant interlayer film. And the low concentration region layer is 25 nm or less. It is characterized by.
[0020]
In the semiconductor device of the present invention, the layer having the organic component concentration relatively lower than the low dielectric constant interlayer film may have a Si—H bond.
[0021]
In the semiconductor device of the present invention, the low dielectric constant film may be methyl silsesquioxane (MSQ), methylated hydrosilsesquioxane (MHSQ), silicon carbide (SiC), carbon-containing silicon oxide film (SiOC). Or SiCOH), silicon carbonitride (SiCN), or a porous film of these films.
[0022]
In order to achieve the above object, the structure of the semiconductor device of the present invention is a via hole formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, or a wiring groove through a barrier metal. In the semiconductor device including the step of embedding a wiring material, the region of the low dielectric constant film in contact with the barrier metal has a region having a concentration of organic components relatively lower than that in the low dielectric constant interlayer film. The barrier metal is formed of tantalum nitride (TaN) on the low dielectric constant film side and tantalum (Ta) on the wiring material side. It is a feature.
[0023]
Also, in the method of manufacturing a semiconductor device of the present invention, a wiring material is embedded in a via hole or a wiring groove formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, through a barrier metal. In the method for manufacturing a semiconductor device including a step, before the barrier metal film formation, from the gas capable of substituting at least part of the group consisting of the organic component on the exposed surface of the low dielectric constant film with hydrogen, or from the organic component Plasma treatment using a gas capable of decomposing at least part of the group to form dangling bonds The barrier metal is formed such that tantalum nitride (TaN) is formed on the low dielectric constant film and then tantalum (Ta) is formed on the wiring material side. Is.
[0024]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: sequentially forming at least a first interlayer insulating film and a second interlayer insulating film on a substrate on which a wiring pattern is formed; Using the first resist pattern formed on the film, forming a via hole that penetrates the first interlayer insulating film and the second interlayer insulating film; and removing the first resist pattern; Etching the second interlayer insulating film using the second resist pattern formed on the second interlayer insulating film to form a trench pattern; the second interlayer insulating film; the via hole; The steps of forming a barrier metal film on the inner wall of the trench pattern and embedding the wiring material in the via hole and the trench pattern by CMP after depositing the wiring material are reduced. In the method of manufacturing a semiconductor device, at least one of the first interlayer insulating film and the second interlayer insulating film is formed of a low dielectric constant film having a bond between an organic component group and Si, and the barrier Before metal film formation, dangling is performed by decomposing at least a part of the group consisting of organic components on the exposed low-dielectric film surface with a gas capable of substituting at least a part of the group consisting of organic components with hydrogen or the group consisting of the organic components. Plasma treatment using a gas capable of forming a bond is performed.
[0025]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: depositing at least a first interlayer insulating film, a second interlayer insulating film, and a hard mask material on a substrate on which a wiring pattern is formed; Etching the hard mask material with a first resist pattern formed on the material to form a hard mask, and using the second resist pattern formed on the hard mask with the first resist pattern Forming a via hole penetrating the interlayer insulating film and the second interlayer insulating film; and removing the second resist pattern; then etching the second interlayer insulating film using the hard mask to form a trench Forming a pattern, forming a barrier metal on the second interlayer insulating film and on the inner wall of the via hole and the trench pattern, and a wiring material And depositing the wiring material in the via hole and the trench pattern by a CMP method. In the method of manufacturing a semiconductor device, the first interlayer insulating film, the second interlayer insulating film, or the hard At least one of the masks is made of a low dielectric constant film having a bond between an organic component group and Si, and at least a part of the organic component group on the exposed surface of the low dielectric constant film before forming the barrier metal. Plasma treatment using a gas capable of substituting hydrogen with a gas or a gas capable of forming a dangling bond by decomposing at least a part of the organic component group.
[0026]
In the present invention, the plasma treatment and the film formation of the barrier metal are performed in the same apparatus or in a state of maintaining a vacuum, or a sputtering treatment step using Ar gas is performed before the plasma treatment. The Ar sputtering, the plasma treatment, and the film formation of the barrier metal can be performed in the same apparatus or in a state where a vacuum is maintained.
[0027]
In the present invention, the low dielectric constant film may be methyl silsesquioxane (MSQ), methylated hydrosilsesquioxane (MHSQ), silicon carbide (SiC), carbon-containing silicon oxide film (SiOC or SiCOH). ), Silicon carbonitride (SiCN), or a porous material of these films.
[0028]
In the present invention, a mixed gas of hydrogen and a rare gas is used as the plasma processing gas, or a rare gas is used as the plasma processing gas and an RF bias is applied during the plasma processing. It is preferable.
[0029]
In the present invention, the rare gas preferably contains any one of He, Ne, Ar, Kr, Xe, and Rn.
[0030]
In the present invention, when He is used as the plasma processing gas, the RF bias power may be set to about 250 W or more and about 400 W or less.
[0031]
As described above, the present invention provides an adhesion between the low dielectric constant film and the barrier metal in a damascene process having an insulating layer including a low dielectric constant film having a bond of Si and an organic component group such as MSQ. By providing a structure that can ensure the resistance, the barrier metal is peeled off during CMP and scratches are generated in the low dielectric constant film, and the film is peeled off at the barrier metal / low dielectric constant film interface due to stress due to multilayering. And the reliability of the damascene process using the low dielectric constant film can be improved.
[0032]
In addition, the present invention provides a pre-process for forming a barrier metal after forming a trench pattern and a via hole in an insulating layer including a low dielectric constant film having a bond between Si and an organic component group such as MSQ. ₂ By performing plasma treatment using a mixed gas of He and He, He gas, etc., the organic component (methyl group in the case of MSQ) on the surface of the low dielectric constant film is replaced with hydrogen, or the organic component is decomposed. Thus, dangling bonds can be formed, and the adhesion between the low dielectric constant film and the barrier metal can be improved. As a result, it is possible to prevent the barrier metal from being peeled off at the time of CMP and causing scratches on the surface of the low dielectric constant film, and the film peeling at the barrier metal / low dielectric constant film interface due to the stress due to multilayering. The reliability of the damascene process using the low dielectric constant film can be improved.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
As shown in the prior art, sputtering using Ar gas is widely used for cleaning the surface layer in the manufacture of semiconductor devices, and impurities and foreign matters adhering to the surface of the material to be sputtered are removed by Ar sputtering treatment. However, the adhesion between the low dielectric constant film and the barrier metal is not improved even if Ar sputtering treatment is performed on the low dielectric constant film having a bond of Si and a group composed of an organic component such as MSQ.
[0034]
This is because the Ar used for sputtering is large in size and has a large energy due to the RF bias. Therefore, the MSQ molecules themselves, which are made of only methyl groups covering the MSQ surface, are sputtered, and new MSQ molecules are formed on the sputter surface. Appears and the methyl group covers the surface again. Therefore, in order to effectively remove only the methyl group of MSQ, it is considered that a gas having a small atomic weight and having a substitution reactivity with the methyl group may be used. Therefore, the following experiment was performed using a mixed gas of a highly reactive gas and a rare gas or a single rare gas (specifically, a mixed gas of He and He and He gas) as a representative gas species.
[0035]
First, a sample in which a tantalum (Ta), tantalum nitride (TaN) layer and a Cu layer were formed as barrier metals on a MSQ film by sputtering was prepared. The film structure is Cu100nm / Ta15nm / TaN15nm / MSQ300nm. After performing the following cleaning process in the pre-cleaning chamber, Ta and TaN layers are formed in the PVD chamber for barrier metal, and then Cu A Cu layer was formed in a PVD chamber for use. The wafers were transferred between the chambers in a vacuum (10-7 torr or less) to prevent contamination of the MSQ surface.
[0036]
As a cleaning process, only etching using Ar gas is performed, and after etching using Ar gas, He / H is performed in the same chamber. ₂ A process for performing plasma treatment using a mixed gas and a process for performing plasma treatment using He gas in the same chamber after etching using Ar gas were performed, and cleaning was performed in each process. A tape test using an adhesive tape was performed on the sample. The results are shown in Table 1.
[0037]
[Table 1]

[0038]
From Table 1, the adhesion of the barrier metal / MSQ interface is not sufficient in the process of only Ar etching or the process of performing the He plasma treatment after the Ar etching, and the barrier metal layer and the Cu layer are in the barrier metal / MSQ interface in all the samples. Although peeled, He / H after Ar etching ₂ In the plasma treatment process, the adhesion at the barrier metal / MSQ interface was improved and no peeling occurred. From this result, H ₂ It can be seen that the plasma treatment using a gas containing gas is effective in improving the adhesion of MSQ.
[0039]
Where He is H ₂ Unlike the case of Ar, the reactivity is low, but since the atomic weight is smaller than Ar, depending on the conditions, there is a possibility that only the methyl group of MSQ can be removed. Therefore, an RF bias was gradually applied during the He plasma treatment to prepare a sample that was cleaned by increasing the energy of He plasma, and a tape test was conducted in the same manner. The results are shown in Table 2.
[0040]
[Table 2]

[0041]
From Table 2, it can be seen that the effect of improving the adhesion is not observed in the treatment without applying the RF bias, but the adhesion is improved because peeling does not occur when the RF bias is applied at 250 W or more. This is thought to be because the energy of the He plasma is small when no RF bias is applied, and the methyl group has not been decomposed. Even when a non-reactive or low gas species is used, the RF bias is applied. It shows that the methyl group can be decomposed by applying appropriate energy. In the case of Ar, since the adhesion is not improved even if an RF bias is applied, it can be seen that the effect cannot be obtained unless an appropriate gas is selected.
[0042]
From the results of Tables 1 and 2, the gas mixture (He / H) containing a highly reactive gas as a gas species. ₂ ) Or noble gas (He), it can be seen that the adhesion between the MSQ and the barrier metal interface is improved, but it is unclear whether the above improvement is due to the removal of methyl groups on the MSQ surface. . In general, methyl groups are hydrophobic, and hydrogen groups and dangling bonds are hydrophilic. Therefore, if the methyl groups are removed effectively, the hydrophilicity of the MSQ surface increases and wettability is improved. Is expected to decline. Therefore, a sample cleaned by the same process as in Table 1 was prepared, and the contact angle of the MSQ surface with water was measured. The results are shown in Tables 3 and 4.
[0043]
[Table 3]

[0044]
[Table 4]

[0045]
From Table 3, although the difference was not clear in the tape test, the contact angle slightly decreased in the process of performing the He plasma treatment (without RF bias) after the Ar etching compared to the process of only the Ar etching. It can be seen that the plasma treatment itself has an effect of improving adhesion. Also, after Ar etching, He / H ₂ In the process of performing plasma treatment, the contact angle is further reduced. ₂ It turns out that the surface modification effect of gas is high. Also, from Table 4, the contact angle is gradually reduced by applying the RF bias even in the He plasma treatment, and especially when the RF bias power is 250 W or more, He / H. ₂ It shows that the surface modification effect is higher than the plasma treatment.
[0046]
The effect of this plasma treatment will be described with reference to FIG. 1. In an untreated state, the MSQ surface is covered with methyl groups. ₂ By exposure to plasma, the Si-CH on the MSQ surface as shown in FIG. _Three This is probably because the bond is replaced with a Si—H bond, and a methyl group having a large molecular structure is replaced with hydrogen, thereby shortening the distance between Si and the barrier metal metal and improving the bonding force. In the case of He plasma treatment, as the RF bias increases, as shown in FIG. _Three It is considered that the bond is broken to form a dangling bond and the bonding force between Si and the barrier metal is improved.
[0047]
From the above experimental results, in order to obtain the adhesion improvement effect of the present invention, a mixed gas containing a highly reactive gas capable of substituting a methyl group with a group having a small molecular structure, for example, hydrogen, as a gas species, or MSQ It is sufficient to use a gas capable of decomposing only the methyl group covering the surface without decomposing all the molecules, He, He / H ₂ Besides, H ₂ And a mixed gas of a rare gas such as Ne, Ar, Kr, Xe, and Rn, a gas containing ammonia, or the like can be used.
[0048]
He / H ₂ In plasma processing, a method of applying an RF bias is conceivable. In this case, however, hydrogen atoms permeate into the substance exposed to the plasma, and Cu is particularly exposed in a state where Cu as a wiring material is exposed. Therefore, when hydrogen gas is used, it is necessary to optimize the RF bias.
[0049]
H ₂ The component ratio of gas and noble gas is H ₂ As the gas ratio increases, the reactivity increases and control becomes difficult, and the substitution reaction of the methyl group proceeds not only to the surface layer but also to the inside, which may increase the dielectric constant of the MSQ. ₂ A component ratio including about 1 to 10% of a highly reactive gas (for example, H ₂ H for He and He ₂ : 4%, He: about 96%). In consideration of reactivity with methyl groups, ammonia gas is also considered. In this case, Cu, which is a wiring material, is nitrided by ammonia, and there is a concern about influence on wiring reliability. Therefore, ammonia concentration, RF bias, It is necessary to optimize the processing time and the like.
[0050]
In addition, the material whose adhesion can be improved by the plasma treatment using the gas may be a material containing an organic component or a material containing a group having a large molecular structure. In addition to MSQ, methylated hydrogensil Sesquioxane (methylated hydrogen silsesquioxane: MHSQ), silicon carbide (SiC), silicon carbonitride (SiCN), carbon-containing silicon oxide film (SiOC or SiCOH), etc. may be used. Good. In addition, any method such as a CVD method or a coating method can be used regardless of a method for forming these films.
[0051]
Si-CH on MSQ surface _Three FIG. 2 shows a schematic process in the case where the above plasma treatment capable of replacing the bond with the Si—H bond is applied to the damascene process. When the via hole 3 is formed in the insulating layer containing the MSQ 1 formed on the substrate 2, the surface and the MSQ exposed surface of the inner wall of the via hole 3 are covered with methyl groups as shown in FIG. H ₂ When the plasma treatment using this mixed gas is performed, the methyl group is replaced with hydrogen as shown in FIG. 2B, the surface becomes hydrophilic, and the adhesion to the inorganic material is improved. In this state, if the barrier metal 4 is formed as shown in FIG. 2C, the MSQ 1 and the barrier metal 4 are strongly coupled, and even if the wiring metal is buried in the via hole 3 by the CMP method, the surface of the MSQ or the inner wall of the via hole 3 is formed. The barrier metal 4 is not peeled off, and the connection reliability of the multilayer wiring can be improved.
He / H ₂ Plasma treatment using a mixed gas or He gas is known, but by this plasma treatment, the dangling bond is generated by substituting the methyl group of the low dielectric constant film such as MSQ with hydrogen or by decomposing the methyl group. And the effect that adhesiveness with a barrier metal can be improved is a novel fact obtained by the knowledge of the present inventor.
[0052]
Si-CH on MSQ surface _Three FIG. 3 shows a schematic process in the case where the above plasma treatment capable of forming a dangling bond by breaking the bond is applied to the damascene process. When the wiring trench pattern 13 is formed in the insulating layer containing MSQ1 formed on the substrate 2, the MSQ exposed surface of the surface and the inner wall of the wiring trench pattern 13 is covered with a methyl group as shown in FIG. Here, when a plasma treatment with an RF bias applied using He gas is performed, as shown in FIG. _Three The bond is broken and the dangling bond layer 25 is formed.
[0053]
The dangling bond layer 25 can change the degree of C desorption and its thickness depending on the plasma processing conditions. Therefore, as shown in FIG. 3C, a sample in which Cu as the barrier metal 4 and the wiring material 5 is formed in the wiring trench pattern 13 is prepared, and the degree of desorption of C and the thickness thereof are changed. Then, scratches due to peeling by the CMP method were investigated. Table 5 shows the results of the number of scratch defects and the capacitance between wirings with respect to the C concentration and film thickness of the dangling bond layer 25 measured by the local EDX method.
[0054]
[Table 5]

[0055]
From Table 5, it was confirmed that when the C concentration of the dangling bond layer 25 is decreased, scratch defects due to adhesion are remarkably reduced. In particular, good results are obtained when the C concentration is 7 atm% or less. However, when the film thickness of the dangling bond layer 25 is 41 nm, it is confirmed that the capacitance between wirings is increased. The C concentration of the dangling bond layer 25 is 2 atm% or more and the film thickness is 25 nm or less. It is preferable that
[0056]
Samples in which a Ta single layer, a TaN single layer, and a Ta / TaN stack were formed as the barrier metal 4 in the wiring groove in which the dangling bond layer 25 was formed were prepared and evaluated in the same manner as described above. Table 6 shows the results of the number of scratch defects for each barrier metal.
[0057]
[Table 6]

[0058]
From Table 6, when the C concentration of the dangling bond layer 25 is 7 atm%, the number of scratch defects is good in all barrier metal structures, whereas the C concentration of the dangling bond layer 25 is 10 atm%. Then, only the Ta single layer has a large number of scratch defects, and the barrier metal material in contact with the dangling bond layer 25 is preferably TaN. Since Ta has better wettability and adhesion with Cu, the barrier metal preferably has a Ta / TaN laminated structure.
[0059]
Although a barrier metal itself having a Ta / TaN laminated structure is known, in a damascene process using a low dielectric constant film having a bond between an organic component group and Si, a wiring groove in which a dangling bond layer is formed or The fact that the Ta / TaN laminated structure is optimal when forming the barrier metal in the via hole is a novel fact obtained by the knowledge of the present inventor.
[0060]
【Example】
In order to describe the above-described embodiment of the present invention in more detail, a specific example of a damascene process to which the structure of the present invention and plasma treatment are applied will be described with reference to the drawings.
[Example 1]
First, a dual damascene process according to the first embodiment of the present invention will be described with reference to FIGS. 4 to 6 are process sectional views showing the procedure of the via first process to which the structure of the present invention and the plasma treatment are applied, and are divided for convenience of drawing.
[0061]
First, as shown in FIG. 4A, after a lower layer wiring 6 made of Cu, Cu alloy or the like is formed on the substrate 2 by a known method, the first etching is performed using a CVD method, a plasma CVD method or the like. A stop film 7, a first interlayer insulating film 8, a second etching stop film 9, and a second interlayer insulating film 10 are sequentially formed with a predetermined film thickness. In addition, as a film | membrane from which the effect of the plasma processing of this invention is obtained, what is necessary is just a low dielectric constant film | membrane containing the group which has a molecular structure large and exhibits hydrophobicity like MSQ containing a methyl group, MHSQ, SiC, SiCN, SiOC, SiCOH or the like or a porous film of these films may be used. The low dielectric constant film may be a film formed by any method such as CVD or coating.
[0062]
In the following description, the case where MSQ is used as the second interlayer insulating film 10 will be described. However, the low dielectric constant film may be used for the first interlayer insulating film 8 or both. Further, the material of the film other than the low dielectric constant film is not particularly limited, and may be a combination of materials that can provide an etching selection ratio. ₂ , SiN, SiON, or the like. The second interlayer insulating film 10 is made of SiO. ₂ When a material other than the above is used, a problem may occur in the CMP process of the wiring. In this case, a cap insulating film may be formed on the second interlayer insulating film 10.
[0063]
Thereafter, an antireflection film 11a for suppressing reflection of light for exposure is deposited on the second interlayer insulating film 10 by about 50 nm, and then a chemically amplified resist for forming a via hole pattern is applied by about 600 nm. Exposure and development are performed by KrF photolithography to form the first resist pattern 12a.
[0064]
Next, as shown in FIG. 4B, the antireflection film 11a, the second interlayer insulating film 10, the second etching stop film 9, and the first interlayer insulating film 8 are sequentially etched by publicly known dry etching. A via hole 3 penetrating through is formed. Thereafter, the resist pattern 12a and the antireflection film 11a are peeled off by oxygen plasma ashing and wet treatment using an organic stripping solution, and the dry etching residue is removed.
[0065]
Next, as shown in FIG. 4C, after depositing about 50 nm of the antireflection film 11b, about 600 nm of chemically amplified resist is applied thereon, and after baking, exposure and development by KrF photolithography are performed. Then, a second resist pattern 12b for forming a wiring trench pattern is formed, and the second antireflection film 11b exposed by a dry etching method is removed.
[0066]
Next, the second interlayer insulating film 10 is etched using the second etching stop film 9 as an etching stopper to form a wiring trench pattern 13, and the second resist pattern 12b and the second resist pattern 12b are formed by oxygen plasma ashing and wet treatment using an organic stripping solution. The second antireflection film 11b is peeled off, and the dry etching residue is removed (see FIG. 5A).
[0067]
Next, as shown in FIG. 5B, after the exposed first etching stop film 7 is removed by dry etching, the surface of the lower layer wiring 6 at the bottom of the via hole 3 is cleaned by sputtering using Ar gas. .
[0068]
In this state, the surface of the second interlayer insulating film (MSQ) 10, the wiring trench pattern 13, and the sidewalls of the via hole 3 are covered with methyl groups, and good adhesion can be obtained even if a barrier metal is formed thereon. Absent. Therefore, as shown in FIG. 5C, the plasma processing, which is a feature of the present invention, is performed in the same chamber, apparatus, or vacuum as in Ar sputtering. As this plasma treatment, He / H ₂ A plasma treatment using a mixed gas or a plasma treatment using a He gas and applying a predetermined RF bias is preferable. For example, He / H ₂ When the plasma treatment using this mixed gas is performed, the methyl group of the MSQ exposed on the surface and the trench sidewall is replaced with hydrogen, and the adhesion to the barrier metal is improved.
[0069]
Ar sputtering treatment, He / H ₂ The plasma treatment and the He plasma treatment are preferably performed under the following conditions.
[0070]
[Ar plasma treatment conditions]
Gas pressure: about 0.2-5mTorr
Gas type: Argon 100%
RF power source: About 200W to 600W
RF bias source: about 200W to 400W
Time: about 60 seconds
[0071]
[H ₂ / He plasma treatment conditions]
Gas pressure: about 20-100mTorr
Gas type: a mixed gas of hydrogen and helium, preferably a mixture ratio of hydrogen 4% helium 96%
RF power source: About 200W to 600W
Time: about 60 seconds
[0072]
[He plasma treatment conditions]
Gas pressure: about 20-100mTorr
Gas type: 100% helium
RF power source: About 200W to 600W
RF bias source: about 200W to 400W
Time: about 60 seconds
[0073]
After the MSQ surface is modified by the above plasma treatment, in order to prevent the diffusion of the wiring material and improve the adhesion as shown in FIG. A barrier metal 4 such as tantalum (Ta) or tantalum nitride (TaN) is formed to a thickness of, for example, about 30 nm, and subsequently a Cu seed metal 19 for facilitating the growth of Cu plating as a wiring material. Is formed with a film thickness of about 100 nm. At this time, the nitrogen concentration in tantalum nitride (TaN) is preferably set to 10 atom% to 50 atom%.
[0074]
Thereafter, as shown in FIG. 6B, Cu to be the wiring material 5 is formed by a plating method, and the wiring trench pattern 13 and the via hole 3 are buried with Cu, and as shown in FIG. The dual damascene structure is completed by polishing the excess Cu using the CMP method and planarizing the surface.
[0075]
In the semiconductor device formed by the above method, the peeling of the barrier metal at the MSQ interface and the scratch on the MSQ surface as shown in the conventional example are not recognized, and the structure and plasma treatment of the present invention are effective in the process using MSQ. I confirmed that there was.
[Example 2]
Next, a dual damascene process according to the second embodiment of the present invention will be described with reference to FIGS. 7 to 10 are process sectional views showing the procedure of the dual hard mask process to which the structure of the present invention and the plasma treatment are applied, and are divided for convenience of drawing.
[0076]
First, as shown in FIG. 7A, similarly to the first embodiment described above, a lower layer wiring 6 made of Cu, Cu alloy or the like is formed on the substrate 2 by a known method, and then a CVD method, A first etching stop film 7, a first interlayer insulating film 8, a second etching stop film 9, and a second interlayer insulating film 10 are sequentially formed using a plasma CVD method or the like. Next, in this embodiment, a first hard mask film 16 and a second hard mask film 17 which are etching masks of the wiring trench pattern are deposited thereon.
[0077]
In this embodiment, the case where MSQ is used as the second interlayer insulating film 10 will be described. However, instead of the second interlayer insulating film 10 or together with the second interlayer insulating film 10, the first interlayer insulating film 8, Even if at least one of the first hard mask film 16 and the second hard mask film 17 is a low dielectric constant film containing a bond of Si and a group made of an organic component such as MSQ, MHSQ, SiC, SiCN, SiOC, and SiCOH. Good.
[0078]
After that, on the second hard mask film 17, an antireflection film 11a is applied to about 50 nm and a chemically amplified resist is applied to about 600 nm, and exposure and development are performed by KrF photolithography to form a first resist pattern 12a.
[0079]
Next, as shown in FIG. 7B, the first antireflection film 11a and the second hard mask film 17 are etched using the first resist pattern 12a by known dry etching to etch the wiring trench pattern. An opening is formed. Thereafter, the resist pattern 12a and the antireflection film 11a are peeled off by oxygen plasma ashing and wet treatment using an organic stripping solution, and the dry etching residue is removed.
[0080]
Next, as shown in FIG. 7C, the second antireflection film 11b is applied to about 50 nm and a chemically amplified resist is applied to about 600 nm. After baking, the second antireflection film 11b is exposed and developed by KrF photolithography. A second resist pattern 12b for forming a via hole having an opening inside the etching region of the hard mask film 17 is formed.
[0081]
Next, as shown in FIG. 8A, the second antireflection film 11b, the first hard mask film 16, the second interlayer insulating film 10, and the second antireflection film 11b are formed by known dry etching using the second resist pattern 2b as a mask. The etching stop film 9 and the first interlayer insulating film 8 are etched, and the via hole 3 penetrating them is formed.
[0082]
Thereafter, as shown in FIG. 8 (b), the second resist pattern 12b and the second antireflection film 11b are stripped by oxygen plasma ashing and wet processing using an organic stripping solution, and the dry etching residue is removed. To do.
[0083]
Next, as shown in FIG. 8C, the first hard mask film 16 and the second interlayer insulating film 10 are etched by using a known dry etching method using the second hard mask film 17 as a mask to form wiring. A trench pattern 13 is formed.
[0084]
Next, as shown in FIG. 9A, after the exposed first etching stop film 7 is removed by dry etching, the surface of the lower layer wiring 6 at the bottom of the via hole 3 is cleaned by sputtering using Ar gas. Subsequently, as shown in FIG. 9B, the plasma processing which is a feature of the present invention is performed in the same chamber, apparatus, or vacuum state as Ar sputtering. The plasma processing method, conditions, gas type, and the like are the same as in the first embodiment.
[0085]
After modifying the MSQ surface by the above plasma treatment, in order to prevent the diffusion of the wiring material and improve the adhesion, as shown in FIG. A barrier metal 4 such as tantalum (Ta) or tantalum nitride (TaN) is formed to a thickness of, for example, about 30 nm, and subsequently a Cu seed metal 19 for facilitating the growth of Cu plating as a wiring material. Is formed with a film thickness of about 100 nm. At this time, the nitrogen concentration in tantalum nitride (TaN) is preferably set to 10 atom% to 50 atom%.
[0086]
Thereafter, as shown in FIG. 10 (a), Cu to be the wiring material 5 is formed by plating, and the wiring trench pattern 13 and the via hole 3 are buried with Cu, and as shown in FIG. 10 (b), The dual damascene structure is completed by polishing the excess Cu using the CMP method and planarizing the surface.
[0087]
When the interlayer insulating film is entirely formed of an organic film, the second antireflection film 11b, the first hard mask film 16, and the second interlayer are formed using the second resist pattern 12b in the step of FIG. The insulating film 10 and the second etching stop film 9 are etched, and the first hard mask film 16 and the second interlayer insulating film 10 are etched using the second hard mask film 17 in the step of FIG. At the same time when the wiring trench pattern 13 is formed, the first interlayer insulating film 8 may be etched to form the via hole 3 penetrating to the first etching stop film 7.
[0088]
In the semiconductor device formed in this way, as in the first embodiment described above, no peeling of the barrier metal at the MSQ interface and no scratch on the MSQ surface are observed, and the structure and plasma treatment of the present invention uses MSQ. The process was effective.
[Example 3]
First, a single damascene process according to a third embodiment of the present invention will be described with reference to FIGS. 11 to 14 are process sectional views showing the procedure of the single damascene process to which the structure of the present invention and the plasma treatment are applied, and are divided for convenience of drawing.
[0089]
First, as shown in FIG. 11A, a first etching stop film 7 and a first interlayer insulating film 8 are sequentially formed at a predetermined thickness on the lower wiring 6 by using a CVD method, a plasma CVD method, or the like. Form. Thereafter, an antireflection film 11a for suppressing the reflection of exposure light is deposited on the first interlayer insulating film 8 by about 50 nm, and then a chemically amplified resist for forming a via hole pattern is applied by about 500 nm. The first resist pattern 12a is formed by performing exposure and development by ArF photolithography.
[0090]
In addition, as a film | membrane from which the effect of the plasma processing of this invention is obtained, what is necessary is just a low dielectric constant film | membrane containing the group which has a molecular structure large and exhibits hydrophobicity like MSQ containing a methyl group, MHSQ, SiC, SiCN, SiOC, SiCOH or the like or a porous film of these films may be used. The low dielectric constant film may be a film formed by any method such as CVD or coating.
[0091]
In the following description, the case where MSQ is used as the first interlayer insulating film 8 and the second interlayer insulating film 10 will be described, but the low dielectric constant film may be used for the first interlayer insulating film 8 or both. Further, the material of the film other than the low dielectric constant film is not particularly limited, and may be a combination of materials that can provide an etching selection ratio. ₂ , SiN, SiON, SiC, SiCN, or the like.
[0092]
Next, as shown in FIG. 11B, the antireflection film 11a and the first interlayer insulating film 8 are sequentially etched by known dry etching to form a via hole 3 penetrating them. Thereafter, the resist pattern 12a and the antireflection film 11a are peeled off by oxygen plasma ashing and wet treatment using an organic stripping solution, and the dry etching residue is removed.
[0093]
Next, as shown in FIG. 11C, after the exposed first etching stop film 7 is removed by a dry etching method, the surface of the lower wiring 6 at the bottom of the via hole 3 is cleaned by sputtering using Ar gas. After that, plasma processing, which is a feature of the present invention, is performed in the same chamber as in Ar sputtering, in the apparatus, or in a state of maintaining a vacuum. The plasma processing method, conditions, gas type, and the like are the same as those in the first and second embodiments.
[0094]
In this embodiment, a case where He plasma treatment is applied will be described. After forming a dangling bond layer on the MSQ surface by He plasma treatment, in the same chamber, in the apparatus or in a vacuum state, as shown in FIG. A barrier metal 4 such as tantalum (Ta) or tantalum nitride (TaN) for improvement is formed with a thickness of, for example, about 30 nm, and subsequently Cu for facilitating the plating growth of Cu as a wiring material. The seed metal 19 is formed with a film thickness of about 100 nm. At this time, the nitrogen concentration in tantalum nitride (TaN) is preferably set to 10 atom% to 50 atom%.
[0095]
Thereafter, Cu to be the wiring material 5 is formed by a plating method, and the inside of the via hole 3 is filled with Cu, and then, as shown in FIG. By planarizing, a via plug is completed. Thereafter, as shown in FIG. 12C, a second etching stop film 9 and a second interlayer insulating film 10 are sequentially formed with a predetermined film thickness for the upper layer wiring.
Next, as shown in FIG. 13A, an antireflection film 11b for suppressing reflection of exposure light is deposited on the second interlayer insulating film 10 to a thickness of about 50 nm, and then a via hole pattern is formed. A chemically amplified resist is applied to about 400 nm, and exposure and development are performed by ArF photolithography to form a second resist pattern 12b.
[0096]
Next, as shown in FIG. 13B, the antireflection film 11b and the second interlayer insulating film 10 are sequentially etched by known dry etching to form a wiring trench pattern 13 penetrating them. Thereafter, the resist pattern 12b and the antireflection film 11b are peeled off by oxygen plasma ashing and wet treatment using an organic peeling solution, and the dry etching residue is removed.
[0097]
Next, as shown in FIG. 14A, after the exposed second etching stop film 9 is removed by dry etching, the via pattern surface at the bottom of the wiring trench pattern 13 is cleaned by sputtering using Ar gas. After performing, the plasma processing which is the feature of the present invention is performed in the same chamber, apparatus, or vacuum state as Ar sputtering. The plasma processing method, conditions, gas type, and the like are the same as those in forming the via plug.
[0098]
In this embodiment, a case where He plasma treatment is applied will be described. After the dangling bond layer is formed on the MSQ surface by He plasma treatment, in the same chamber, in the apparatus or in a vacuum state, as shown in FIG. A barrier metal 4 such as tantalum (Ta) or tantalum nitride TaN for improvement is formed with a thickness of, for example, about 30 nm, and subsequently a Cu seed for facilitating the growth of Cu plating as a wiring material. The metal 19 is formed with a film thickness of about 100 nm. At this time, the nitrogen concentration in tantalum nitride (TaN) is preferably set to 10 atom% to 50 atom%.
[0099]
Thereafter, Cu to be the wiring material 5 is formed by a plating method, and the wiring trench pattern 13 is filled with Cu, and then, as shown in FIG. 14C, the excess Cu is polished by using the CMP method. A single damascene structure is completed by planarizing the surface.
[0100]
In the semiconductor device formed in this way, as in the first and second embodiments, the barrier metal peeling at the MSQ interface and the scratch on the MSQ surface are not observed. It has been confirmed that the process using is effective.
[Example 4]
First, a single damascene process according to a fourth embodiment of the present invention will be described with reference to FIGS. 15 to 18 are process cross-sectional views showing the procedure of a single damascene process to which the structure of the present invention and plasma treatment are applied, and are divided for convenience of drawing.
[0101]
First, as shown in FIG. 15A, the first etching stop film 7, the first interlayer insulating film 8, and the first cap insulating film 23 are formed on the lower wiring 6 by using a CVD method, a plasma CVD method, or the like. Sequentially with a predetermined film thickness. Thereafter, an antireflection film 11a for suppressing the reflection of exposure light is deposited on the first cap insulating film 23 by about 50 nm, and then a chemically amplified resist for forming a via hole pattern is applied by about 500 nm. The first resist pattern 12a is formed by performing exposure and development by ArF photolithography.
[0102]
In addition, as a film | membrane from which the effect of the plasma processing of this invention is obtained, what is necessary is just a low dielectric constant film | membrane containing the group which has a molecular structure large and exhibits hydrophobicity like MSQ containing a methyl group, MHSQ, SiC, SiCN, SiOC, SiCOH or the like or a porous film of these films may be used. The low dielectric constant film may be a film formed by any method such as CVD or coating.
[0103]
In this embodiment, the case where SiOC is used as the first interlayer insulating film 8 and the second interlayer insulating film 10 will be described. However, the low dielectric constant film may be used for the first interlayer insulating film 8 or both. Further, the material of the film other than the low dielectric constant film is not particularly limited, and may be a combination of materials that can provide an etching selection ratio. ₂ , SiN, SiON, SiC, SiCN, or the like.
[0104]
Next, as shown in FIG. 15B, the antireflection film 11a, the first cap insulating film 23, and the first interlayer insulating film 8 are sequentially etched by known dry etching to form a via hole 3 penetrating them. To do. Thereafter, the resist pattern 12a and the antireflection film 11a are peeled off by oxygen plasma ashing and wet treatment using an organic stripping solution, and the dry etching residue is removed.
[0105]
Next, as shown in FIG. 15C, after the exposed first etching stop film 7 is removed by dry etching, the surface of the lower layer wiring 6 at the bottom of the via hole 3 is cleaned by sputtering using Ar gas. After that, plasma processing, which is a feature of the present invention, is performed in the same chamber as in Ar sputtering, in the apparatus, or in a state where a vacuum is maintained. The plasma processing method, conditions, gas type, and the like are the same as those in the first to third embodiments.
[0106]
In this embodiment, a case where He plasma treatment is applied will be described. After the dangling bond layer is formed on the exposed side surface of SiOC by He plasma treatment, the diffusion of the wiring material is prevented as shown in FIG. A barrier metal 4 such as tantalum (Ta) or tantalum nitride (TaN) for improving adhesion is formed with a thickness of, for example, about 30 nm, and subsequently facilitates plating growth of Cu serving as a wiring material. A Cu seed metal 19 is formed to a thickness of about 100 nm. At this time, the nitrogen concentration in tantalum nitride (TaN) is preferably set to 10 atom% to 50 atom%.
[0107]
Thereafter, Cu to be the wiring material 5 is formed by a plating method, and the inside of the via hole 3 is filled with Cu, and then, as shown in FIG. By planarizing, a via plug is completed. Thereafter, as shown in FIG. 16C, a second etching stop film 9, a second interlayer insulating film 10, and a second cap insulating film 24 are sequentially formed with a predetermined film thickness for upper layer wiring.
Next, as shown in FIG. 17A, an antireflection film 11b for suppressing reflection of exposure light is deposited on the second cap insulating film 24 to a thickness of about 50 nm, and then a via hole pattern is formed. A chemically amplified resist is applied to about 400 nm, and exposure and development are performed by ArF photolithography to form a second resist pattern 12b.
Next, as shown in FIG. 17B, the antireflection film 11b, the second cap insulating film 24, and the second interlayer insulating film 10 are sequentially etched by publicly known dry etching, and the wiring trench pattern 13 penetrating them. Form. Thereafter, the resist pattern 12b and the antireflection film 11b are stripped by oxygen plasma ashing and wet processing using an organic stripper, and the dry etching residue is removed.
[0108]
Next, as shown in FIG. 18A, after the exposed second etching stop film 9 is removed by dry etching, the surface of the via pattern at the bottom of the wiring trench pattern 13 is cleaned by sputtering using Ar gas. After performing, the plasma processing which is the feature of the present invention is performed in the same chamber, apparatus, or vacuum state as Ar sputtering. The plasma processing method, conditions, gas type, and the like are the same as those in forming the via plug.
[0109]
In this embodiment, a case where He plasma treatment is applied will be described. After forming a dangling bond layer on the exposed side surface of SiOC by He plasma treatment, in the same chamber, in the apparatus or in a vacuum state, as shown in FIG. A barrier metal 4 such as tantalum (Ta) or tantalum nitride (TaN) for improving adhesion is formed with a thickness of, for example, about 30 nm, and subsequently facilitates plating growth of Cu serving as a wiring material. A Cu seed metal 19 is formed to a thickness of about 100 nm. At this time, the nitrogen concentration in tantalum nitride (TaN) is preferably set to 10 atom% to 50 atom%.
[0110]
Thereafter, Cu to be the wiring material 5 is formed by plating, and the wiring trench pattern 13 is filled with Cu, and then, as shown in FIG. A single damascene structure is completed by planarizing the surface.
[0111]
In the semiconductor device formed in this way, as in the first to third embodiments described above, no peeling of the barrier metal at the SiOC interface was observed, and the structure and plasma treatment of the present invention were applied to a process using SiOC. It was confirmed that there was an effect.
[0112]
In each of the above embodiments, the structure of the present invention and the He / H ₂ The case where the plasma treatment using the mixed gas or He gas is applied to the dual damascene process, the via first process, the dual hard mask process, and the single damascene process has been described. However, the present invention is limited to the above-described embodiment. The present invention can be applied to any semiconductor process including a step of forming a metal film such as a barrier metal on an exposed surface of a low dielectric constant film including a group having a large molecular structure such as a methyl group.
[0113]
【The invention's effect】
As described above, according to the method of manufacturing a semiconductor device of the present invention, a barrier metal or the like is formed in a trench or a via hole formed in an insulating layer including a low dielectric constant film such as MSQ, MHSQ, SiC, SiCN, SiOC, and SiCOH. In a damascene process that includes a step of forming a metal film, the barrier metal is peeled off during CMP, causing scratches on the surface of the low dielectric constant insulating film, and barrier metal / low dielectric constant insulation due to stress due to multilayering. The problem of film peeling at the film interface can be avoided.
[0114]
The reason for this is that, after the formation of the wiring trench pattern and the via hole, as a pre-process for forming the barrier metal, He / H ₂ A plasma treatment using a mixed gas of the above and a plasma treatment using He gas and applying an RF bias are performed to form a structure of the present invention, whereby the methyl group on the surface of a low dielectric constant film such as MSQ is replaced with hydrogen. This is because it can be decomposed and modified to be hydrophilic to improve the adhesion to an inorganic material.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing the plasma processing mechanism of the present invention.
FIG. 2 is a process cross-sectional view showing a part of a manufacturing process including plasma processing according to the present invention.
FIG. 3 is a process cross-sectional view showing a part of the manufacturing process including the structure and plasma treatment of the present invention.
FIG. 4 is a process sectional view showing the procedure of the via first process according to the first embodiment of the present invention.
FIG. 5 is a process sectional view showing the procedure of the via first process according to the first embodiment of the invention.
FIG. 6 is a process sectional view showing the procedure of the via first process according to the first embodiment of the invention.
FIG. 7 is a process sectional view showing a procedure of a dual hard mask process according to a second embodiment of the present invention.
FIG. 8 is a process sectional view showing a procedure of a dual hard mask process according to a second embodiment of the present invention.
FIG. 9 is a process cross-sectional view illustrating a procedure of a dual hard mask process according to a second embodiment of the present invention.
FIG. 10 is a process cross-sectional view illustrating a procedure of a dual hard mask process according to a second embodiment of the present invention.
FIG. 11 is a process sectional view showing the procedure of a single damascene process according to a third embodiment of the present invention.
FIG. 12 is a process sectional view showing the procedure of a single damascene process according to a third embodiment of the present invention.
FIG. 13 is a process sectional view showing the procedure of a single damascene process according to a third embodiment of the present invention.
FIG. 14 is a process sectional view showing the procedure of a single damascene process according to a third embodiment of the present invention.
FIG. 15 is a process cross-sectional view illustrating the procedure of a single damascene process according to a fourth embodiment of the present invention.
FIG. 16 is a process cross-sectional view illustrating the procedure of a single damascene process according to a fourth embodiment of the present invention.
FIG. 17 is a process sectional view showing the procedure of a single damascene process according to the fourth embodiment of the present invention;
FIG. 18 is a process sectional view showing the procedure of a single damascene process according to the fourth embodiment of the present invention.
FIG. 19 is a process cross-sectional view illustrating a procedure of a conventional via first process.
FIG. 20 is a process cross-sectional view illustrating a procedure of a conventional via first process.
FIG. 21 is a process sectional view showing the procedure of a conventional via first process.
[Explanation of symbols]
1 MSQ
2 Substrate
3 Beer hall
4 Barrier metal
5 Wiring material
6 Lower layer wiring
7 First etching stop film
8 First interlayer insulating film
9 Second etching stop film
10 Second interlayer insulating film (MSQ)
11a First antireflection film
11b Second antireflection film
12a First resist pattern
12b Second resist pattern
13 Wiring trench pattern
14 Ar
15 He / H ₂ plasma
16 First hard mask film
17 Second hard mask film
18 Second interlayer insulating film
19 Seed Metal
20 Peel
21 scratch
22 He plasma
23 First cap insulating film
24 Second cap insulating film

Claims (19)

In a semiconductor device having a structure in which a wiring material is embedded via a barrier metal in a via hole formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, or the wiring groove, In the region of the low dielectric constant film that is in contact with the barrier metal, there is a layer that is a region having a relatively lower organic component concentration than the inside of the low dielectric constant interlayer film . A semiconductor device characterized in that the carbon (C) concentration in the region layer is 7 atm% or less . In a semiconductor device having a structure in which a wiring material is embedded via a barrier metal in a via hole formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, or the wiring groove, In the region of the low dielectric constant film that is in contact with the barrier metal, there is a layer that is a region having a relatively lower organic component concentration than the inside of the low dielectric constant interlayer film . A semiconductor device having a region layer of 25 nm or less . In a semiconductor device having a structure in which a wiring material is embedded via a barrier metal in a via hole formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, or the wiring groove, a region in contact with the barrier metal of the low dielectric constant film, the low dielectric constant interlayer film inside than the organic component concentration have a region of relatively low concentration, the barrier metal, the low dielectric constant film side tantalum nitride ( TaN), and the wiring material side is formed of tantalum (Ta) . In a semiconductor device having a structure in which a wiring material is embedded via a barrier metal in a via hole formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, or the wiring groove, In the region of the low dielectric constant film that is in contact with the barrier metal, there is a layer that is a region having a relatively lower organic component concentration than the inside of the low dielectric constant interlayer film . The region layer has a carbon (C) concentration of 7 atm% or less, the region layer is 25 nm or less, the barrier metal is tantalum nitride (TaN) on the low dielectric constant film side, and tantalum (Ta) on the wiring material side. A semiconductor device formed of 4. The semiconductor device according to claim 2 , wherein a carbon (C) concentration of a layer in which the organic component concentration is relatively lower than that of the low dielectric constant interlayer film is 7 atm% or less. 4. The semiconductor device according to claim 3 , wherein the layer whose organic component concentration is relatively lower than that of the low dielectric constant interlayer film is 25 nm or less. Carbon (C) Concentration of the organic component concentration layer wherein a relatively lower concentration than the low-dielectric-constant interlayer film is not more than 7 atm%, according to claim 1 to 6, characterized in that and 2 atm% or more The semiconductor device according to any one of the above. 8. The semiconductor device according to claim 1, wherein the layer having the organic component concentration relatively lower than the low dielectric constant interlayer film has a Si-H bond. The low dielectric constant film is methyl silsesquioxane (MSQ), methylated hydrosilsesquioxane (MHSQ), silicon carbide (SiC), carbon-containing silicon oxide film (SiOC or SiCOH), silicon carbonitride (SiCN). 9) or a porous material of these films. 9. The semiconductor device according to claim 1 , wherein the film is made porous. In a method for manufacturing a semiconductor device, including a step of burying a wiring material through a barrier metal in a via hole or a wiring groove formed in an insulating layer including a low dielectric constant film having a bond between an organic component group and Si, Before the barrier metal film is formed, a gas capable of substituting at least a part of the organic component group on the exposed surface of the low dielectric constant film with hydrogen or at least a part of the organic component group is decomposed and dung. There line plasma treatment using a formable gas ring bonds, then the barrier metal was formed tantalum nitride (TaN) on the low dielectric constant film, so that tantalum (Ta) to the wiring material side A method for manufacturing a semiconductor device, comprising: forming a semiconductor device.   A step of sequentially forming at least a first interlayer insulating film and a second interlayer insulating film on a substrate on which a wiring pattern is formed, and a first resist pattern formed on the second interlayer insulating film are used. Forming a via hole penetrating through the first interlayer insulating film and the second interlayer insulating film, and removing the first resist pattern and then forming a first via hole formed on the second interlayer insulating film. And etching the second interlayer insulating film using the resist pattern 2 to form a trench pattern, and forming a barrier metal on the second interlayer insulating film, the via hole, and the inner wall of the trench pattern. And a method of manufacturing a semiconductor device including at least a step of embedding the wiring material in the via hole and the trench pattern by CMP after depositing the wiring material. In addition, at least one of the first interlayer insulating film or the second interlayer insulating film is made of a low dielectric constant film having a bond between an organic component group and Si, and is exposed before the formation of the barrier metal. A gas capable of substituting at least a part of the organic component group on the surface of the low dielectric constant film with hydrogen or a gas capable of forming a dangling bond by decomposing at least a part of the organic component group is used. A method for manufacturing a semiconductor device, comprising performing plasma processing.   A step of depositing at least a first interlayer insulating film, a second interlayer insulating film, and a hard mask material on a substrate on which a wiring pattern is formed, and a first resist pattern formed on the hard mask material are used. Etching the hard mask material to form a hard mask, and using the second resist pattern formed on the hard mask, the first interlayer insulating film and the second interlayer insulating film are formed. A step of forming a via hole penetrating; a step of removing the second resist pattern; and etching the second interlayer insulating film using the hard mask to form a trench pattern; and the second interlayer A barrier metal film is formed on the insulating film and on the inner wall of the via hole and the trench pattern, and after depositing a wiring material, the via hole is formed by CMP. And at least one of the first interlayer insulating film, the second interlayer insulating film, and the hard mask is made of an organic component. A gas having a low dielectric constant film having a bond between a group and Si, and capable of substituting at least a part of the group consisting of an organic component on the exposed surface of the low dielectric constant film with hydrogen before forming the barrier metal, or A method for manufacturing a semiconductor device, wherein plasma treatment is performed using a gas capable of decomposing at least a part of the organic component group to form a dangling bond. 13. The method of manufacturing a semiconductor device according to claim 10, wherein the plasma treatment and the film formation of the barrier metal are performed in the same apparatus or in a state where a vacuum is maintained. A sputtering treatment step using Ar gas is performed before the plasma treatment, and the Ar sputtering, the plasma treatment, and the film formation of the barrier metal are performed in the same apparatus or in a vacuum state. A method for manufacturing a semiconductor device according to claim 10 . The low dielectric constant film is methyl silsesquioxane (MSQ), methylated hydrosilsesquioxane (MHSQ), silicon carbide (SiC), carbon-containing silicon oxide film (SiOC or SiCOH), silicon carbonitride (SiCN). The method for manufacturing a semiconductor device according to any one of claims 10 to 14 , wherein the film is made of any one of these films made porous. 16. The method for manufacturing a semiconductor device according to claim 10 , wherein a mixed gas of hydrogen and a rare gas is used as the plasma treatment gas. 16. The semiconductor device according to claim 10 , wherein a rare gas or a mixed gas of hydrogen and a rare gas is used as the plasma treatment gas, and an RF bias is applied during the plasma treatment. Production method. 18. The method of manufacturing a semiconductor device according to claim 16 , wherein the rare gas includes any one of He, Ne, Ar, Kr, Xe, and Rn. 18. The method of manufacturing a semiconductor device according to claim 17 , wherein, when He is used as the plasma processing gas, the RF bias power is set to about 250 W or more and about 400 W or less.

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