JP2008235811A - Method of manufacturing semiconductor device and the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the yield of wiring by preventing faulty connection, while increasing the EM resistance and SM resistance during the formation of a multilayer wiring structure by damascene process. <P>SOLUTION: A semiconductor device is formed by the steps of applying silicon-containing gas onto copper wiring which is formed on a semiconductor substrate and is made of a material containing copper as a main component, and forming a silicon-containing layer on a surface of the copper wiring (S102); forming a diffusion preventing film on the copper wiring (S104); forming an interlayer insulating film containing Si, O, and C on the diffusion preventing film (S106); forming a recessed portion on the interlayer insulating film so as to reach the diffusion preventing film (S108); forming a reformed layer, having a higher oxygen concentration than the other regions on a surface of the interlayer insulating film exposed to the sidewall of the recessed portion (S110); removing the diffusion preventing film to expose a surface of the copper wiring (S112); and forming wiring, by embedding a conductive material in the recessed portion (S114). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, with miniaturization and speeding up of semiconductor devices, copper (Cu) wiring having a low resistance has been used. The copper wiring is formed by a damascene method. In the damascene method, first, an interlayer insulating film is formed on a lower wiring. Next, a resist film having a predetermined pattern is formed on the interlayer insulating film, and the interlayer insulating film is selectively etched using the resist film as a mask to form recesses such as via holes and wiring grooves reaching the lower layer wiring. Thereafter, copper is embedded in the recess. Subsequently, the copper exposed to the outside of the recess is removed by CMP (Chemical Mechanical Polishing). By repeating this procedure, a multilayer wiring structure is formed.

  Further, the damascene method includes a dual damascene method in which a via hole and a wiring groove are simultaneously formed, and a single damascene method in which a via hole and a wiring groove are separately formed. One of the dual damascene methods is a via first method in which a wiring pattern is formed after forming a via pattern in an insulating film for forming a copper wiring.

  Patent Document 1 (Japanese Patent Laid-Open No. 2005-45176) and Patent Document 2 (Japanese Patent Laid-Open No. 2003-309170) describe a technique for forming a multilayer wiring structure by such a damascene method.

  In Patent Document 1, an interlayer insulating film containing Si, C, and O is formed on a SiC barrier film formed on a wiring, an opening reaching the SiC barrier film is formed in the interlayer insulating film, and the opening is formed. Plasma treatment using a gas containing hydrogen is performed on the side surface of the interlayer insulating film exposed toward the surface to form an altered layer on the side surface, and then the SiC barrier film is etched to reach the opening to the wiring. A method for manufacturing a semiconductor device in which a conductive material is embedded in the opening is described. It is said that an altered layer can be formed by increasing the Si or C concentration on the side surface of the interlayer insulating film by plasma treatment to improve the selectivity with the SiC barrier film. Thereby, side etching of the interlayer insulating film can be prevented during the subsequent etching of the SiC barrier film.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 2003-309170) discloses a barrier after forming a via hole in order to improve the adhesion between an organic low dielectric constant film such as MSQ and an inorganic material such as a barrier metal. Prior to forming the metal film, a technique is described in which plasma treatment using He gas is performed to reduce the concentration of organic components on the surface and to improve hydrophilicity so as to improve adhesion to the barrier metal. ing. Here, an example is described in which plasma treatment using He gas is performed after an opening reaching the lower layer wiring or via is formed in the interlayer insulating film and the etching stop film (diffusion prevention film) therebelow.

Further, Patent Document 3 (Japanese Patent Laid-Open No. 2004-228445) and Patent Document 4 (Japanese Patent Laid-Open No. 2004-214267) disclose electromigration (EM) resistance and stress migration (SM) of wiring using copper as a wiring material. In order to increase the resistance, a semiconductor device is described in which the surface of the wiring is irradiated with silane so that the silicon atom concentration on the surface of the copper wiring becomes rich.
JP 2005-45176 A JP 2003-309170 A JP 2004-228445 A JP 2004-214267 A

  However, as described in Patent Document 3 and Patent Document 4, according to the study of the present inventor, in the configuration in which the silicon-containing gas is formed on the surface of the copper wiring by irradiating the silicon-containing gas on the surface of the copper wiring, It has become clear that an etching failure occurs when a recess reaching the copper wiring is formed in order to form the film. The upper layer wiring is formed by forming a diffusion prevention film and an interlayer insulation film on the lower layer copper wiring, etching the diffusion prevention film and the interlayer insulation film to form a recess, and exposing the lower copper wiring surface. The It has been clarified that when this copper wiring surface is exposed, the omission of etching deteriorates and etching failure occurs. It has also been clarified that such etching defects occur when an insulating film containing carbon such as a SiOC film is used as an interlayer insulating film. When such deterioration of etching loss occurs, connection failure occurs. As a result of various studies, the present inventors have found that when etching an interlayer insulating film, a substance such as carbon is generated from the interlayer insulating film, which inhibits the etching, which is the cause of such etching failure. As a result, the present invention was conceived.

According to the present invention,
Forming a silicon-containing layer on the copper wiring by irradiating a silicon-containing gas on a copper wiring formed of a material mainly composed of copper formed on a semiconductor substrate;
Forming a diffusion barrier film on the copper wiring;
Forming an interlayer insulating film containing Si, O, and C on the diffusion preventing film;
Forming a recess reaching the diffusion barrier film in the interlayer insulating film;
Forming a modified layer having a higher oxygen concentration than other regions on the surface of the interlayer insulating film exposed on the side wall of the recess;
Removing the diffusion barrier film to expose the copper wiring surface;
Forming a wiring by embedding a conductive material in the recess;
A method for manufacturing a semiconductor device is provided.

  Here, the silicon-containing layer may be selectively formed on the surface of the copper wiring, or may be formed by diffusing Si throughout the copper wiring. In any case, a silicon-containing layer is formed on the surface portion of the copper wiring. With such a configuration, when the diffusion prevention film is removed by etching, a modified layer is formed on the sidewall of the interlayer insulating film in the recess, so that gas such as carbon is generated from the interlayer insulating film. Can be prevented. Thereby, the formation of an etching inhibitor due to the reaction between the silicon-containing layer on the copper wiring and the gas can also be prevented, and the loss of the diffusion preventing film can be prevented from being deteriorated. As a result, when forming a multilayer wiring structure by the damascene method, it is possible to improve connection yield and improve the yield of wiring while improving the EM resistance and SM resistance, and to improve the reliability of the semiconductor device.

  Such a drop-out deterioration of the diffusion preventive film occurs specifically in a configuration in which a film containing Si, O, and C is used as an interlayer insulating film and a silicon-containing layer is formed in a copper wiring. In order to prevent such a drop-out deterioration, it is necessary to form a modified layer in the interlayer insulating film before etching the diffusion prevention film.

According to the present invention,
A semiconductor substrate;
A lower copper wiring formed on the semiconductor substrate and having a silicon-containing layer formed thereon;
A diffusion barrier film formed on the lower copper wiring;
An interlayer insulating film formed on the diffusion barrier film and containing Si, O, and C;
An upper layer wiring formed in the interlayer insulating film and the diffusion prevention film and connected to the lower layer copper wiring;
Including
Projections containing silicon are formed on the surface of the silicon-containing layer,
The interlayer insulating film is provided with a semiconductor device in which a modified layer having a higher oxygen concentration than other regions is provided in a region in contact with the upper wiring.

  According to the manufacturing method of the present invention described above, even when a protrusion containing silicon is formed on the surface of the copper wiring, it is possible to prevent the deterioration of the diffusion preventing film formed thereon. Thereby, the semiconductor device having the above configuration can be obtained stably.

  According to the present invention, when a multi-layer wiring structure is formed by the damascene method, it is possible to improve the EM resistance and SM resistance while preventing connection failure and improving the wiring yield.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a flowchart showing a manufacturing procedure of a semiconductor device according to the present embodiment. Hereinafter, a case where the upper layer wiring is formed by dual damascene will be described as an example.

  In the present embodiment, first, a lower layer copper wiring is formed on a semiconductor substrate (S100). Subsequently, the silicon-containing layer is formed by irradiating the surface of the lower copper wiring with a silicon-containing gas (S102).

  Next, a diffusion preventing film and an interlayer insulating film are formed on the lower copper wiring (S104 and S106). Here, the interlayer insulating film can be a film containing Si, O, and C, such as a SiOC film. Thereafter, a recess which is a dual damascene wiring groove reaching the diffusion barrier film is formed in the interlayer insulating film (S108). At this time, the diffusion preventing film remains on the lower copper wiring.

  Subsequently, a modified layer having a higher oxygen concentration than other regions is formed on the surface of the interlayer insulating film exposed on the side wall of the recess (S110). Next, the diffusion prevention film is removed by etching using the interlayer insulating film as a mask (S112). Thereby, the lower layer copper wiring is exposed. Thereafter, the recess is filled with a conductive material to form upper layer wiring and vias (S114).

  In this way, when the diffusion prevention film is removed by etching, the sidewall of the interlayer insulating film is covered with the modified layer, so that generation of a gas such as carbon from the interlayer insulating film can be prevented. it can. Thereby, the formation of an etching inhibitor due to the reaction between the silicon-containing layer on the copper wiring and the gas can be prevented, and the loss of the diffusion preventing film can be prevented from being deteriorated. As a result, when forming a multi-layer wiring structure by the damascene method, it is possible to improve the yield of wiring by preventing poor connection and improving the reliability of the semiconductor device while improving the EM resistance and SM resistance.

2 to 4 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device 100 according to the present embodiment.
First, a first interlayer insulating film 106 is formed on an insulating film 104 formed on a semiconductor substrate 102 which is a silicon substrate, for example. The insulating film 104 can have a stacked structure of a plurality of insulating films. Further, an element such as a transistor can be formed over the semiconductor substrate 102. Although not shown here, the first interlayer insulating film 106 includes a diffusion preventing film similar to the diffusion preventing film 112 described later, a low dielectric constant film similar to the second interlayer insulating film 114 described later, and a later described. A stacked structure of the protective insulating film 116 and the same protective insulating film can be employed.

  Subsequently, a lower copper wiring 108 is formed in the first interlayer insulating film 106. The lower layer copper wiring 108 is formed as follows, for example. First, a wiring trench is formed in the first interlayer insulating film 106. Subsequently, a barrier metal film is formed on the entire surface of the first interlayer insulating film 106, and a barrier metal film is formed on the side wall of the wiring trench. Next, a copper film is formed on the entire surface of the first interlayer insulating film 106, and the inside of the wiring trench is filled with the copper film. Thereafter, the copper film and the barrier metal film exposed outside the wiring trench are removed by CMP. Thereby, the lower layer copper wiring 108 is formed.

Next, the surface of the lower layer copper wiring 108 is irradiated with a silicon-containing gas (FIG. 2A). Here, as the silicon-containing gas, for example, silane (SiH ₄ ) gas can be used. Further, the irradiation with the silicon-containing gas can be performed in a plasma CVD apparatus. Specifically, for example, the gas flow rate of silane gas: 10 to 500 sccm, the gas flow rate of N ₂ gas: 100 to 5000 sccm, the processing pressure: 20 Torr, the processing temperature of about 350 ° C., the processing time: 5 seconds to 100 seconds. Can do. By setting the processing time to about 30 seconds or more, EM and SM resistance can be improved. Further, prior to the irradiation with the silicon-containing gas, a reduction treatment for removing oxide on the surface of the lower layer copper wiring 108 may be performed.

  As a result, a silicon-containing layer 110 is formed on the surface of the lower copper interconnect 108 (FIG. 2B). Here, a configuration in which the silicon-containing layer 110 is selectively formed on the surface of the lower layer copper wiring 108 is shown. However, by irradiating the silicon-containing gas, Si diffuses into the lower layer copper wiring 108, and the lower layer copper wiring 108 A silicon-containing layer 110 that is an alloy layer of Si and Cu may be formed throughout 108. Subsequently, a diffusion prevention film 112 is formed on the first interlayer insulating film 106 and the lower copper wiring 108. Diffusion prevention film 112 can be made of, for example, SiCN, SiC, or SiN. Further, the diffusion preventing film 112 is formed on the lower copper wiring 108 via the silicon-containing layer 110.

  Next, a second interlayer insulating film 114 is formed on the diffusion prevention film 112. In the present embodiment, the second interlayer insulating film 114 can be formed of a low dielectric constant film having a relative dielectric constant of 3.3 or less, more preferably 2.9 or less, for example. The second interlayer insulating film 114 can be formed of a film containing Si, O, and C. Specifically, the second interlayer insulating film 114 is made of, for example, porous SiOC (SiOCH), methylsilsesquioxane (MSQ), hydrogenated methylsilsesquioxane (MHSQ), organic polysiloxane, or a film thereof. It can comprise by what did. In addition, any method such as a CVD method or a coating method can be used regardless of a method for forming these films.

Thereafter, a protective insulating film 116 is formed over the second interlayer insulating film 114. The protective insulating film 116 can be made of, for example, SiO ₂ or the like. The low dielectric constant film is generally weaker in chemical resistance and mechanical strength than the SiO ₂ film conventionally used as an insulating film between wirings. For this reason, when a low dielectric constant film material is used as the interlayer insulating film, the interlayer insulating film is also removed in the CMP process, which causes an increase in wiring resistance and variations. The protective insulating film 116 is provided for the purpose of protecting the interlayer insulating film in the CMP process. Therefore, the protective insulating film 116 is made of a material having a mechanical strength higher than that of the material constituting the second interlayer insulating film 114 below the protective insulating film 116. Thus, the structure shown in FIG. 2C is obtained.

  Subsequently, a dual damascene wiring trench 118 is formed in the second interlayer insulating film 114 and the protective insulating film 116 (FIG. 3A). As a formation procedure of the dual damascene wiring trench 118, there are a via first method, a trench first method, a middle first method, a dual hard mask method, and the like, and any formation procedure can be used in this embodiment. Hereinafter, as an example, a procedure of forming by the via first method will be described.

  First, a via resist film having a via pattern for forming vias is formed on the protective insulating film 116. An antireflection film may be formed between the protective insulating film 116 and the via resist film. Next, using the via resist film as a mask, the protective insulating film 116 and the second interlayer insulating film 114 are sequentially and selectively dry etched to form via holes in the protective insulating film 116 and the second interlayer insulating film 114. Here, the diffusion prevention film 112 is not etched. Thereafter, the via resist film is removed by ashing such as oxygen plasma ashing. When the antireflection film is formed, the antireflection film is also removed. In addition, after the ashing, the inside of the via hole can be cleaned using a stripping solution or the like.

  Next, a wiring resist film is formed on the protective insulating film 116, and the via hole is filled with the wiring resist film. Subsequently, the wiring resist film, the protective insulating film 116, and the second interlayer insulating film 114 are selectively etched. Thereafter, the wiring resist film is removed by ashing such as oxygen plasma ashing. Thus, a dual damascene wiring trench 118 is formed, and the second interlayer insulating film 114 is exposed on the sidewall of the dual damascene wiring trench 118 (FIG. 3A). Further, after the ashing, the inside of the dual damascene wiring groove 118 can be cleaned using a stripping solution or the like.

Subsequently, the modified layer 120 having a higher oxygen concentration than other regions is formed on the surface of the second interlayer insulating film 114 exposed on the side walls of the dual damascene wiring trench 118. In this embodiment, the modified layer 120 is irradiated with He plasma from the entire surface of the protective insulating film 116 (FIG. 3B), and the second interlayer insulating film 114 exposed in the dual damascene wiring trench 118 is formed. It can be formed by reforming (FIG. 3C). Here, the He plasma irradiation can be performed in a plasma CVD apparatus. Specifically, for example, it can be performed under the following conditions.
Processing pressure: 0.5 mTorr to 10 Torr, more preferably 10 to 100 mTorr
RF power source: 0 W to 3000 W, more preferably 300 W to 1000 W
RF bias source: 0 W to 3000 W, more preferably 0 W to 1000 W
Temperature: 150-450 ° C, more preferably 300 ° C-350 ° C
Time: 15 to 1800 seconds, more preferably 45 to 60 seconds

  By performing such He plasma irradiation treatment, the oxygen concentration of the second interlayer insulating film 114 exposed on the sidewalls of the dual damascene wiring trench 118 is increased, and the modified layer 120 is formed. It was confirmed by X-ray photoelectron spectroscopy (XPS) that the oxygen concentration of the second interlayer insulating film 114 was increased by the He plasma irradiation treatment.

Next, using the protective insulating film 116 and the second interlayer insulating film 114 as a hard mask, the diffusion prevention film 112 is dry etched to expose the surface of the lower copper wiring 108 in the dual damascene wiring trench 118 (FIG. 4A). ). As the etching gas, for example, a fluorocarbon-based gas such as CF ₄ can be used. As a result, the dual damascene wiring trench 118 reaches the lower layer copper wiring 108. Note that immediately before the diffusion prevention film 112 is etched, the inside of the dual damascene wiring trench 118 can be cleaned using an organic stripping solution such as SSX-L4 (manufactured by Kanto Chemical), Ar plasma, or the like. As a result, it is possible to remove residual substances and the like that degrade the pullability of the dual damascene wiring trench 118.

FIG. 5 is an enlarged cross-sectional view in which the lower copper wiring 108 and the silicon-containing layer 110 of the semiconductor device 100 are enlarged.
FIG. 5A shows a state before the diffusion prevention film 112 is formed. When the silicon-containing layer 110 is formed on the surface of the lower-layer copper wiring 108, a silicon-containing layer protrusion 110a due to abnormal growth or the like is formed on the surface of the silicon-containing layer 110 depending on the silane irradiation conditions. FIG. 9 shows an observation view by a TEM photograph in which the protrusion 110a is formed. Although the silicon-containing layer 110 cannot be clearly confirmed in this figure, it can be confirmed by XPS that silicon is contained in the surface of the lower layer copper wiring 108.

  FIG. 5B shows a dual damascene process in which a diffusion prevention film 112, a second interlayer insulation film 114, and a protective insulation film 116 (not shown here) are formed on the first interlayer insulation film 106 and the lower layer copper wiring 108. It is a figure which shows the state in which the wiring groove | channel 118 was formed. If the protrusion 110a is formed on the surface of the silicon-containing layer 110, the step is reflected in the diffusion preventing film 112, and the surface is uneven.

  When the surface of the diffusion prevention film 112 is uneven as described above, the ease of etching varies depending on the location when the diffusion prevention film 112 is etched. Further, the diffusion prevention film 112 is also slightly etched during the etching of the protective insulating film 116 and the second interlayer insulating film 114, but the ease of etching varies depending on the location. Therefore, a difference in thickness occurs depending on the location. In particular, when the dual damascene wiring trench 118 is formed by the dual damascene via first method, after the via hole reaching the diffusion prevention film 112 is formed, further etching is performed to form the wiring trench. Is likely to occur. Therefore, a part where the diffusion preventing film 112 is removed and the silicon-containing layer 110 is exposed and a part where the diffusion preventing film 112 remains thick are generated. If the etching process of the silicon-containing layer 110 is continued in this state, the exposed silicon-containing layer 110 and a gas such as carbon generated from the second interlayer insulating film 114 react to form an etching inhibitor. It is considered that the detachability of the diffusion preventing film 112 is deteriorated.

  In this embodiment mode, since the second interlayer insulating film 114 can be protected by the modified layer 120 during the etching of the diffusion prevention film 112, the formation of an etching inhibitor can be prevented, and the release property can be prevented. Can be prevented.

FIG. 6 is a diagram showing via dimensions when etching is performed on the SiOC film under the same conditions except that CF ₄ and oxygen gas are used as the etching gas and the oxygen gas flow rate is changed. As shown in the figure, the larger the oxygen gas flow rate in the etching gas, the larger the dimension of the via and the easier the etching. If the oxygen concentration in the SiOC film is high, the oxygen concentration becomes high during etching. For this reason, it is considered that the same phenomenon occurs when the flow rate of oxygen gas in the etching gas is increased. In other words, in this embodiment, when the modified layer 120 having a higher oxygen concentration than other regions is formed on the surface of the second interlayer insulating film 114 exposed on the side wall of the dual damascene wiring trench 118, the diffusion preventing film 112 is etched. Side etching of the second interlayer insulating film 114 is likely to occur. However, as described above, when the silicon-containing layer 110 is formed on the surface of the lower layer copper wiring 108, a gas such as carbon is generated from the second interlayer insulating film 114 and reacts with the silicon-containing layer 110 for etching. It is important to prevent the formation of inhibitors. Therefore, in this embodiment, the modified layer 120 is formed to prevent the diffusion preventing film 112 from being deteriorated even if the ease of side etching of the second interlayer insulating film 114 is somewhat sacrificed. I have to.

  Returning to FIG. 4, thereafter, a wiring material is embedded in the dual damascene wiring trench 118. Specifically, for example, a barrier metal film is formed in the wiring pattern by sputtering or atomic layer deposition (ALD). The barrier metal film can be, for example, Ta / TaN, Ti, TiN, TiSiN, Ta, TaN, or TaSiN. Subsequently, the dual damascene wiring trench 118 is filled with a copper film. The copper film can be formed by, for example, a plating method. Further, the copper film may be configured to include a metal other than copper, such as Ag. Next, the copper film and the barrier metal film exposed outside the dual damascene wiring trench 118 are removed by CMP. Thereby, the upper layer copper wiring 122 is formed (FIG. 4B). Further, after that, a silicon-containing layer can be formed on the surface of the upper copper wiring 122 in the same manner as the silicon-containing layer 110 formed on the lower copper wiring 108. Thereby, the EM resistance and SM resistance of the upper layer copper wiring 122 can also be increased. By repeating the above steps, the semiconductor device 100 having a multilayer wiring structure is formed.

(Measurement Example 1)
A semiconductor device was manufactured under the following conditions, and a via defect rate was measured. Unless otherwise specified, the same procedure as described with reference to FIGS. 2 to 4 is used in the above embodiment. In any example, a SiCN film was used as the diffusion preventing film 112, a SiOC film was used as the second interlayer insulating film 114, and a SiO ₂ film was used as the protective insulating film 116.

(Example 1): With silane irradiation for forming the silicon-containing layer 110 (same conditions as in the first embodiment, silane irradiation time is 45 seconds), with He plasma treatment for forming the modified layer 120 (hereinafter referred to as “the modified layer 120”) Conditions)
(Example 2): With silane irradiation to form the silicon-containing layer 110 (same conditions as in the first example, silane irradiation time is 45 seconds), without He plasma treatment to form the modified layer 120 (example) 3) Neither silane irradiation for forming the silicon-containing layer 110 nor He plasma treatment for forming the modified layer 120 (He plasma irradiation conditions)
Processing pressure: 8 Torr
RF power source: 440W
RF bias source: 0W
Temperature: 350 ° C
Time: 30 seconds

The results are shown in FIG. Data for each case are shown twice. Assuming that there are 100 chips on the wafer and there is a chain of 1M vias on the chip, the via defect rate assumes that the number of chips in which the 1M chain is defective is the number of via defects. The probability that one via is defective was calculated as follows.
Via failure rate = number of via failures / (1M x 100 chips) x 1000000000 [ppb]

  Further, in Example 1, the modified layer 120 having a higher oxygen concentration than other regions of the second interlayer insulating film 114 is formed in the region in contact with the upper copper wiring 122 of the second interlayer insulating film 114 by XPS. It has been confirmed that.

(Measurement example 2)
In the configuration in which the silicon-containing layer was formed on the surface of the lower copper wiring, the relationship between the silane irradiation time when forming the silicon-containing layer and the via defect rate when the modified layer was not formed was examined. Except that the He plasma treatment for forming the modified layer 120 is not performed, the semiconductor device is manufactured according to the same procedure as described with reference to FIGS. did. An SiCN film was formed as the diffusion preventing film 112, an SiOC film was formed as the second interlayer insulating film 114, and an SiO ₂ film was formed as the protective insulating film 116.

The silane irradiation conditions for forming the silicon-containing layer 110 were as follows: the silane irradiation time was 25 seconds, 30 seconds, 35 seconds, 45 seconds, and 50 seconds.
Silane gas flow rate: 100-500 sccm
Gas flow rate of N ₂ gas: 1000~10000sccm
Processing pressure: 1-10 Torr
Processing temperature: 100-350 ° C

  The results are shown in FIG. The horizontal axis represents the silane irradiation time (second (sec)), and the vertical axis represents the via defect rate (ppp). The via defect rate was measured by the same method as in the first measurement example. It has been shown that the via defect rate increases as the silane irradiation time increases. This is because, as the silane irradiation time is longer, the protrusions 110a as described with reference to FIG. 5 are more likely to be generated, and this tends to generate an etching inhibitor. Conceivable.

  The present invention has been described based on the embodiments and examples. It is to be understood by those skilled in the art that the embodiments and examples are merely examples, and various modifications are possible and that such modifications are within the scope of the present invention.

  Further, in the above embodiment, the lower layer copper wiring 108 is shown as an example, but the present invention can also be applied to the case where a dual damascene structure wiring is formed on a via. That is, the present invention can also be applied when the lower layer copper wiring 108 is a via.

  Further, in the above embodiment, the structure in which the protective insulating film 116 is formed over the second interlayer insulating film 114 is shown. However, when the second interlayer insulating film 114 is formed of a material having CMP resistance, the semiconductor device 100 may be configured not to include the protective insulating film 116.

  In the above embodiment, the example in which the diffusion preventing film 112 is removed after the dual damascene wiring trench 118 is formed is shown. However, the present invention is applied to the case where the via hole or the wiring trench is formed by the single damascene method. You can also Also in such a case, after forming the via hole or the wiring groove reaching the diffusion prevention film, the modified layer is formed, and then the diffusion prevention film is removed, thereby preventing the deterioration of the diffusion prevention film. be able to.

  Further, for example, in the case of removing the diffusion prevention film before forming the wiring trench by the via-first method of the dual damascene method, the interlayer insulation exposed in the via hole is formed after forming the via hole reaching the diffusion prevention film. It is possible to form a modified layer on the film surface and then remove the diffusion barrier film. In this case, after removing the diffusion preventing film, the interlayer insulating film can be selectively etched to form a wiring groove, thereby forming a dual damascene wiring groove.

It is a flowchart which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is the expanded sectional view which expanded the part of the lower layer copper wiring and silicon content layer of a semiconductor device. It is a figure which shows the relationship between the oxygen concentration in a SiOC film | membrane, and the ease of being etched when a fluorocarbon type gas is used as etching gas. It is a figure which shows the relationship between the presence or absence of a silicon containing layer, the presence or absence of a modified layer, and a via defect rate. FIG. 4 is a diagram showing the relationship between the silane irradiation time and the via defect rate when forming a silicon-containing layer when a modified layer is not formed in a configuration in which a silicon-containing layer is formed on the surface of a lower copper wiring. is there. It is a figure which shows the state in which the protrusion was formed on the lower layer copper wiring.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Semiconductor substrate 104 Insulating film 106 1st interlayer insulating film 108 Lower layer copper wiring 110 Silicon-containing layer 110a Protrusion 112 Diffusion prevention film 114 Second interlayer insulating film 116 Protective insulating film 118 Dual damascene wiring groove 120 Modification Layer 122 Upper layer copper wiring

Claims (7)

Forming a silicon-containing layer on the copper wiring by irradiating a silicon-containing gas on a copper wiring formed of a material mainly composed of copper formed on a semiconductor substrate;
Forming a diffusion barrier film on the copper wiring;
Forming an interlayer insulating film containing Si, O, and C on the diffusion preventing film;
Forming a recess reaching the diffusion barrier film in the interlayer insulating film;
Forming a modified layer having a higher oxygen concentration than other regions on the surface of the interlayer insulating film exposed on the side wall of the recess;
Removing the diffusion barrier film to expose the copper wiring surface;
Forming a wiring by embedding a conductive material in the recess;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein in the step of forming the modified layer, the modified layer is formed by modifying the interlayer insulating film by irradiating He plasma in the recess. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the diffusion prevention film is any one of SiCN, SiC, or SiN. In the manufacturing method of the semiconductor device in any one of Claim 1 to 3,
The method for manufacturing a semiconductor device, wherein the interlayer insulating film is SiOC (SiOCH), methyl silsesquioxane (MSQ), hydrogenated methyl silsesquioxane (MHSQ), organic polysiloxane, or a film obtained by porousizing these films. . In the manufacturing method of the semiconductor device in any one of Claim 1 to 4,
The step of forming the recess includes a step of selectively etching the interlayer insulating film to form a via hole reaching the diffusion prevention film in the interlayer insulating film, and a step of selectively etching the interlayer insulating film to form a wiring trench. And forming a dual damascene structure wiring pattern on the interlayer insulating film. In the manufacturing method of the semiconductor device in any one of Claim 1 to 5,
A method for manufacturing a semiconductor device, further comprising a step of cleaning the inside of the recess after the step of forming the modified layer and before the step of exposing the surface of the copper wiring. A semiconductor substrate;
A lower copper wiring formed on the semiconductor substrate and having a silicon-containing layer formed thereon;
A diffusion barrier film formed on the lower copper wiring;
An interlayer insulating film formed on the diffusion barrier film and containing Si, O, and C;
An upper layer wiring formed in the interlayer insulating film and the diffusion prevention film and connected to the lower layer copper wiring;
Including
Projections containing silicon are formed on the surface of the silicon-containing layer,
The interlayer insulating film is a semiconductor device in which a modified layer having a higher oxygen concentration than other regions is provided in a region in contact with the upper wiring.

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