JP2004207604A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve adhesion between an SiOC film (low-k film) and an SiO<SB>2</SB>film (cap film) without reducing the resolution of resist and the increase of leakage current between wires. <P>SOLUTION: An improvement layer 3 is formed between the SiOC film 2 and the SiO<SB>2</SB>film 4, and the film thickness of the improvement layer 3 is set to ≥10nm in the range in which the carbon concentration is 10-90% of that of the SiO<SB>2</SB>film 4. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device using an insulating film containing silicon, oxygen and carbon as an interlayer insulating film and a method for manufacturing the same.
[0002]
[Prior art]
As the integration and speed of semiconductor devices become higher and higher, there is a need to reduce the capacitance between wirings and between layers. Therefore, the development of technologies for lowering the resistance of metal wirings and lowering the dielectric constant of interlayer insulating films is progressing. In.
[0003]
As a technique for lowering the dielectric constant of an interlayer insulating film, the introduction of a SiOC film, which is one of low-k films, having a lower dielectric constant (≦ 3) than a conventionally used SiO ₂ film is known. ing.
[0004]
Since low-k films such as SiOC films generally have lower mechanical strength and plasma resistance than the above-described SiO ₂ film, there is a concern that damage may occur in the low-k film during the manufacturing process. Have been. As a method for preventing the occurrence of this type of damage, a cap process has been proposed in which a SiO ₂ film (cap film) is formed on a SiOC film by a CVD process, and the SiOC film is protected by the SiO ₂ film.
[0005]
Here, if the SiO ₂ film is formed directly on the SiOC film, the adhesion between the SiOC film and the SiO ₂ film is low, so that the SiO ₂ film is converted from the SiOC film in a later process (for example, a CMP process in a damascene process). The problem of peeling occurs.
[0006]
Therefore, in order to improve the adhesion between the SiOC film and the SiO ₂ film, the surface of the SiOC film is treated with a plasma generated from a gas such as N ₂ / H ₂ or N ₂ O to adhere to the surface of the SiOC film. Attempts have been made to form a modified layer (intermediate layer) for improving the properties, and then form an SiO ₂ film on the SiOC film via the modified layer.
[0007]
However, when this type of plasma processing is performed, various problems occur due to active species (radicals and ions) of nitrogen and oxygen in the plasma.
[0008]
For example, in the case of a dual damascene process in which vias are formed, nitrogen is introduced into the SiOC film, and then, in a step of forming a via hole in the SiOC film, nitrogen in the SiOC film escapes from the side surface of the via hole, and The nitrogen concentration increases, and an alkaline substance such as NH ₂ containing nitrogen and hydrogen is generated. This kind of alkaline substance causes a hindrance to the resolution of a chemically amplified resist that becomes a resist pattern for a wiring groove. This is because the acid generated in the exposed part of the chemically amplified resist is neutralized and dissolution is inhibited.
[0009]
Although the same problem exists in the dual damascene process for forming the wiring groove tip, the wiring groove is wide and the nitrogen concentration in the wiring groove is unlikely to increase. Therefore, a substance having alkalinity such as NH ₂ is not easily generated, and does not cause a serious problem.
[0010]
By adopting the dual damascene process of forming the wiring groove, there is no need to worry about the reduction of the resolution of the chemically amplified resist, but the dual damascene process of forming the wiring groove is replaced with the dual damascene process of forming the via. However, not all problems can be solved by adopting a dual damascene process for forming a wiring groove tip.
[0011]
In addition, C in the SiOC film is reduced deep from the surface by oxygen (radicals, ions) in the plasma, and moisture is easily absorbed in the reduced portion. That is, the hygroscopicity of the SiOC film increases. As a result, there arises a problem that leakage current and capacitance between wirings increase. Further, the reduction of C in the SiOC film from the surface to the depth leads to an increase in the thickness of the modified layer. The modified layer has lower insulation than the SiOC film. Therefore, the leak current between the wirings and the like also increase with an increase in the thickness of the modified layer.
[0012]
[Problems to be solved by the invention]
As described above, in order to improve the adhesion between the SiOC film and the SiO ₂ film, the surface of the SiOC film is treated with a plasma containing nitrogen. A problem arises in that the resolution of the chemically amplified resist decreases.
[0013]
Further, when the surface of the SiOC film is treated with plasma containing oxygen in order to improve the adhesion between the SiOC film and the SiO ₂ film, a problem arises in that the leak current between wirings increases.
[0014]
The present invention has been made in consideration of the above circumstances, and has as its object to reduce the resolution of a resist, increase the leakage current between wirings, or both, without causing an SiOC film and SiO An object of the present invention is to provide a semiconductor device capable of improving adhesion to _two films and a method for manufacturing the same.
[0015]
[Means for Solving the Problems]
The outline of typical inventions among the inventions disclosed in the present application will be briefly described as follows.
[0016]
That is, in order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, containing silicon, oxygen, and carbon, and silicon provided on the insulating film. An oxide film, provided between the insulating film and the silicon oxide film, wherein the carbon concentration is lower than the carbon concentration in the insulating film, and the carbon concentration is at least 10% of the carbon concentration in the insulating film. And a nitrogen-free intermediate layer having a film thickness of 10 nm or more in a portion of 90% or less.
[0017]
According to the present invention, by providing an intermediate layer having a predetermined thickness or more between the insulating film containing silicon, oxygen and carbon and the silicon oxide film thereon, the film of the insulating film and the silicon oxide film can be formed. Peeling can be prevented, and since the intermediate layer does not contain nitrogen, a decrease in resolution of the resist can be prevented.
[0018]
Further, another semiconductor device according to the present invention includes a semiconductor substrate, an insulating film provided on the semiconductor substrate and containing silicon, oxygen, and carbon; a silicon oxide film provided on the insulating film; Provided between the film and the silicon oxide film, wherein the carbon concentration is lower than the carbon concentration in the insulating film, and the carbon concentration is in a range of 10% to 90% of the carbon concentration in the insulating film. And a nitrogen-free intermediate layer having a thickness of 50 nm or less at a certain portion.
[0019]
According to the present invention, by providing an intermediate layer having the predetermined thickness or less between the insulating film containing silicon, oxygen, and carbon and the silicon oxide film thereon, the leakage current due to the decrease in insulation of the intermediate layer is provided. In addition, since the intermediate layer does not contain nitrogen, a decrease in the resolution of the resist can be prevented.
[0020]
Further, another semiconductor device according to the present invention includes a semiconductor substrate, an insulating film provided on the semiconductor substrate and containing silicon, oxygen, and carbon; a silicon oxide film provided on the insulating film; Provided between the film and the silicon oxide film, wherein the carbon concentration is lower than the carbon concentration in the insulating film, and the carbon concentration is in a range of 10% to 90% of the carbon concentration in the insulating film. And a nitrogen-free intermediate layer having a thickness of 10 nm or more and 50 nm or less at a certain portion.
[0021]
According to the present invention, by providing an intermediate layer having the above-mentioned predetermined thickness range between an insulating film containing silicon, oxygen and carbon and a silicon oxide film thereon, a film of the insulating film and the silicon oxide film is provided. An increase in leakage current due to peeling and a decrease in insulation of the intermediate layer can be prevented, and a decrease in resolution of the resist can be prevented because the intermediate layer does not contain nitrogen.
[0022]
The method for manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film containing silicon, oxygen and carbon on a semiconductor substrate, a step of modifying the surface of the insulating film with a nitrogen-free plasma, Forming a silicon oxide film on the film.
[0023]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0025]
FIG. 1 is a sectional view showing a step of forming a Cu wiring layer of a semiconductor device according to one embodiment of the present invention.
[0026]
FIG. 1A is a cross-sectional view in which a SiOC film 2 as a low-k film (a relative dielectric constant lower than that of a SiO ₂ film, for example, k ≦ 3) is formed on a silicon substrate 1 on which elements are integrated and formed. Is shown. For example, methylsiloxane is used as a raw material of the SiOC film 2, and a method of forming the SiOC film 2 is, for example, a coating method. Up to this point, it is the same as the conventional one.
[0027]
Next, as shown in FIG. 1B, the surface of the SiOC film 2 is subjected to a plasma treatment using a plasma of a rare gas (group 0 element gas) such as He gas or Ar gas, for example. A modified layer (intermediate layer) 3 is formed on the surface of the film 2, and then a SiO ₂ film 4 as a cap film is formed on the modified layer 3, for example, nitrogen such as TEOS / O ₂ or SiH ₄ / O _2. It is formed by a plasma CVD process using a raw material not containing. The input power at the time of the plasma processing is, for example, in a range of 50 W or more and less than 750 W.
[0028]
The modified layer 3 is for improving the adhesion between the SiOC film 2 and the SiO ₂ film 4. The modified layer 3 contains silicon, oxygen, and carbon, and the carbon concentration is lower than the carbon concentration of the SiOC film 2. The lower limit of the thickness of the portion of the modified layer 3 where the C concentration is in the range of 10 to 90% of the C concentration in the SiOC film 2 is 10 nm. The reason why the thickness is 10 nm is that when the C concentration is less than 10 nm, the adhesion is insufficiently improved and the film is peeled off.
[0029]
FIG. 2 shows the C concentration profile of the SiOC film 2 / modified layer 3 / SiO ₂ film 4 when the film is peeled off and when the film is not peeled off. The C concentration profile is standardized by the C concentration of the SiOC film 2. As shown in FIG. 2, it was confirmed that film peeling occurred when the film thickness was less than 10 nm and did not occur when the film thickness was 10 nm or more.
[0030]
The upper limit of the thickness of the portion of the modified layer 3 where the C concentration is in the range of 10 to 90% of the C concentration in the SiOC film 2 is 50 nm. The reason why the thickness is 50 nm is from the viewpoint of suppressing an increase in leak current, as described later.
[0031]
Since the modified layer 3 is formed by subjecting the surface of the SiOC film 2 to plasma treatment, it is difficult to specify the interface between the modified layer 3 and the SiOC film 2. Therefore, it is difficult to define the entire thickness of the modified layer 3. Therefore, in the present embodiment, the above-described thickness regulation is adopted as a preferable thickness of the modified layer 3.
[0032]
Further, in the above-mentioned film thickness regulation, the film thickness range is 10 nm to 50 nm, but only one of the lower limit and the upper limit may be satisfied as necessary. When only the lower limit is satisfied, the adhesion between the SiOC film 2 and the SiO ₂ film 4 can be improved without lowering the resolution of the resist. The adhesion between the SiOC film 2 and the SiO ₂ film 4 can be improved without increasing the thickness. The thickness of the modified layer 3 can be controlled by plasma processing conditions, for example, the input power and the flow rate of argon or the like.
[0033]
In the present embodiment, the modified layer 3 is formed by plasma processing using a rare gas such as He gas or Ar gas. That is, it is formed by plasma treatment that does not include active species (ions, radicals) of oxygen and nitrogen.
[0034]
Therefore, oxygen can penetrate deep into the SiOC film 2 to suppress an increase in leak current due to a decrease in the insulating property of the SiOC film 2. In addition, as a raw material of the above-mentioned active species of oxygen, for example, O ₂ and N ₂ O are used. In the plasma treatment using a rare gas, the thickness of the modified layer 3 is less likely to increase than in the plasma treatment using oxygen, so that the disadvantage that the thickness of the modified layer 3 exceeds the upper limit (50 nm) is raised. It can be easily avoided.
[0035]
As described above, by increasing the thickness of the modified layer 3 to 50 nm or less and forming the modified layer 3 by a plasma treatment containing no oxygen, an increase in leak current can be easily and sufficiently suppressed. become.
[0036]
Further, since the plasma treatment does not include nitrogen, it is possible to prevent a decrease in resolution of the resist due to nitrogen, as described later. In addition, as a raw material of the above-mentioned active species of nitrogen, for example, N ₂ , N ₂ O, and NH ₃ are exemplified.
[0037]
The problem of lowering the resolution of the resist can be more effectively avoided by forming the SiO ₂ film 4 by a plasma CVD process using a nitrogen-free raw material as in the present embodiment. The sources of conventionally used nitrogen-containing SiO ₂ films include, for example, SiH ₄ / N ₂ O / N ₂ , SiH ₄ / N ₂ O, and TEOS / O ₂ / N ₂ . Of these, N ₂ is used as a diluent gas.
[0038]
Next, as shown in FIG. 1 (c), a resist pattern 5 of via holes on the SiO ₂ film 4, followed by the resist pattern 5 of the SiO ₂ film 4 as a mask, the modified layer 3, SiOC film 2 are sequentially etched by a RIE (Reactive Ion Etching) process to form a via hole 6. The resist pattern 5 is formed by exposing and developing a chemically amplified resist by a known photolithography process. Further, on the surface of the silicon substrate 1 on the bottom surface of the via hole 6, for example, a conductive region such as a source / drain diffusion layer of a MOS transistor exists, but is omitted.
[0039]
Here, in the present embodiment, since the process of the modified layer 3 and the SiO ₂ film 4 (cap film) does not include nitrogen, nitrogen is not introduced into the SiOC film 2. Therefore, when the via hole 6 is formed, N ₂ , NH _{3 and the} like in the SiOC film 2 escape from the side surface of the via hole 6 and an alkaline substance such as NH ₂ containing nitrogen and hydrogen is not generated. . That is, it is possible to prevent the generation of a substance (resolution inhibiting substance) that lowers the resolution of the chemically amplified resist.
[0040]
The via hole 6 is generally deep and has a high aspect ratio, and this tendency further progresses with miniaturization of the element. Therefore, the concentration of the resolution inhibiting substance in the via hole 6 tends to increase.
[0041]
Next, the resist pattern 5 is peeled off, and thereafter, a chemically amplified resist is applied to the entire surface so as to fill the via holes 6, and the chemically amplified resist is exposed and developed, as shown in FIG. 1D. Next, a resist pattern 7 for a wiring groove is formed.
[0042]
At this time, in the case of the present embodiment, as described above, the resolution-inhibiting substance of the chemically amplified resist is not generated when the via hole 6 is formed. Therefore, the resolution of the chemically amplified resist that becomes the resist pattern 7 does not decrease, and the resist pattern 7 having a desired shape can be obtained.
[0043]
FIG. 3 shows a cross-sectional shape of the resist pattern 7 'when a resolution inhibiting substance is generated. As shown in FIG. 3, an unresolved defect of the resist occurs, and the resist pattern 7 ′ is formed so as to cover a part of a region to be a wiring groove. Therefore, even if etching is performed using the resist pattern 7 'as a mask, a wiring groove having a desired shape is not formed.
[0044]
Next, as shown in FIG. 1E, using the resist pattern 7 as a mask, the SiO ₂ film 4, the modified layer 3, and the SiOC film 2 are sequentially etched by an RIE process to form a wiring groove 8.
[0045]
At this time, in the present embodiment, since the resist pattern 7 having the desired shape has been formed, the wiring groove 8 having the desired shape can be formed. Thereafter, a barrier metal film (not shown) is deposited on the entire surface so as to cover the side and bottom surfaces of the wiring groove 8 and the via hole 6.
[0046]
Next, the resist pattern 7 is peeled off, a Cu film is formed on the entire surface by, for example, a plating method so as to fill the wiring groove 8 and the via hole 6, and then the wiring groove 8 and the via hole 6 are formed by a CMP (Chemical Mechanical Polishing) process. By removing unnecessary external Cu film and barrier metal film (not shown) and flattening the surface, Cu wiring (Cu dual wiring) is formed in the wiring groove 8 and the via hole 6 as shown in FIG. A damascene wiring 9 is formed.
[0047]
At this time, in the present embodiment, since the adhesion between the SiOC film 2 and the SiO ₂ film 4 is ensured by the modified layer 3, the film between the SiOC film 2 and the SiO ₂ film 4 is No peeling occurs. Therefore, the SiOC film 2 is protected by the SiO ₂ film 4 during the CMP process, and the mechanical damage of the SiOC film 2 during the CMP process is prevented.
[0048]
Thereafter, as shown in FIG. 1G, a semiconductor device (for example, a logic LSI, a DRAM, an SRAM, or the like) is completed through a known process such as a process of depositing a passivation film 10 over the entire surface by a plasma CVD process. .
[0049]
At this time, in the present embodiment, the adhesion between the SiOC film 2 and the SiO ₂ film 4 is secured by the modified layer 3 and the SiOC film 2 is protected by the SiO ₂ film 4, so that the Plasma damage to the SiOC film 2 is prevented.
[0050]
In the present embodiment, as described above, the thickness of the portion of the modified layer 3 where the C concentration is in the range of 10 to 90% of the C concentration in the SiOC film 2 is 50 nm or less. Since the modified layer 3 has a lower insulating property than the SiOC film 2, if the thickness of the modified layer 3 exceeds 50 nm, an increase in leak current cannot be ignored.
[0051]
The leak current here is a leak current between the adjacent Cu wirings 9 via the modified layer 3 as shown in FIG. FIG. 5 shows the electric field dependence of the leakage current when the thickness of the modified layer 3 is greater than 50 nm (73 nm) and when the thickness of the modified layer 3 is 50 nm or less (16 nm). In order to confirm the reproducibility, the electric field dependence of the leak current was examined for four chips (samples). The reason why only three data at 73 nm can be seen is that the two data overlap. From FIG. 5, it can be seen that when the thickness of the modified layer 3 exceeds 50 nm, the electric field dependence of the leakage current increases and the leakage current increases more than when the thickness is 50 nm or less.
[0052]
Note that the present invention is not limited to the above embodiment. For example, in the above embodiment, the case of the first Cu wiring layer has been described, but the Cu wirings of the second and subsequent layers can be formed by the same method. In the above embodiment, the case of a single wiring layer has been described. However, in the case of a multi-layer wiring layer, each wiring layer may be formed by the same method as in the above embodiment. Further, the present invention may be applied to only a part of the multilayer wiring layers instead of all the layers.
[0053]
In the above embodiment, the case of Cu wiring has been described, but the present invention can be applied to other metal wiring. The semiconductor substrate is not limited to a silicon substrate, and may be, for example, an SOI substrate or a semiconductor substrate containing strained silicon.
[0054]
Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements described in the embodiment, if the problem described in the section of the problem to be solved by the invention can be solved, the constituent Can be extracted as an invention.
[0055]
In addition, various modifications can be made without departing from the scope of the present invention.
[0056]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to improve the adhesion between the SiOC film and the SiO ₂ film without reducing the resolution of the resist, increasing the leak current between the wirings, or both. And a method of manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a step of forming a Cu wiring of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram showing a SiOC film / modified layer / SiO in a case where film peeling has occurred and a case where film peeling has not occurred. FIG. 3 is a diagram showing a C concentration profile of _two films. FIG. 3 is a cross-sectional diagram showing a cross-sectional shape of a resist pattern when a resolution-inhibiting substance is generated. FIG. 4 is a graph showing leakage current between adjacent Cu wirings via a modified layer. FIG. 5 is a diagram showing electric field dependence of leakage current when the thickness of the modified layer is greater than 50 nm and when the thickness is 50 nm or less.
[Explanation of symbols]
1: silicon substrate 2: SiOC film (low-k film)
3. Modified layer (intermediate layer)
4: SiO ₂ film (cap film)
5 ... Resist pattern (for via hole)
6 via hole 7 resist pattern (for wiring groove)
8 Wiring groove 9 Cu wiring 10 Passivation film

Claims (14)

A semiconductor substrate;
An insulating film provided on the semiconductor substrate and containing silicon, oxygen and carbon,
A silicon oxide film provided on the insulating film;
A portion provided between the insulating film and the silicon oxide film and having a carbon concentration in the range of 10% to 90% of the carbon concentration in the insulating film has a film thickness of 10 nm or more, and does not contain nitrogen; A semiconductor device comprising an intermediate layer. A semiconductor substrate;
An insulating film provided on the semiconductor substrate and containing silicon, oxygen and carbon,
A silicon oxide film provided on the insulating film;
A portion provided between the insulating film and the silicon oxide film and having a carbon concentration in the range of 10% or more and 90% or less of the carbon concentration in the insulating film has a thickness of 50 nm or less and does not contain nitrogen; A semiconductor device comprising an intermediate layer. A semiconductor substrate;
An insulating film provided on the semiconductor substrate and containing silicon, oxygen and carbon,
A silicon oxide film provided on the insulating film;
Nitrogen provided between the insulating film and the silicon oxide film and having a carbon concentration in the range of 10% to 90% of the carbon concentration in the insulating film having a film thickness of 10 nm or more and 50 nm or less; A semiconductor device comprising: an intermediate layer containing no. 4. The semiconductor device according to claim 1, wherein the insulating film has a lower relative dielectric constant than the silicon oxide film. The semiconductor device according to claim 4, wherein a relative dielectric constant of the insulating film is 3.0 or less. 6. The semiconductor device according to claim 1, wherein a wiring and a plug are provided in a stacked film of the silicon oxide film, the intermediate layer, and the insulating film. Forming an insulating film containing silicon, oxygen and carbon on the semiconductor substrate;
Modifying the surface of the insulating film with a nitrogen-free plasma,
Forming a silicon oxide film on the insulating film. The method according to claim 7, wherein the plasma containing no nitrogen does not further contain oxygen. 9. The method according to claim 7, wherein the plasma containing no nitrogen includes a plasma of a group 0 element. The method according to claim 9, wherein the group 0 element is helium or argon. The method of manufacturing a semiconductor device according to claim 7, wherein the silicon oxide film is formed in an atmosphere containing no nitrogen. Raw material of the silicon oxide film, a method of manufacturing a semiconductor device according to claim 10, characterized in that it comprises a TEOS or SiH ₄ 13. The method according to claim 7, further comprising: forming a via hole in a laminated film of the insulating film and the silicon oxide film; and forming a wiring groove connected to the via hole on a surface of the laminated film. 13. The method for manufacturing a semiconductor device according to claim 1. Forming a conductive film on the laminated film so as to fill the via hole and the wiring groove; and removing the conductive film outside the via hole and the wiring groove by a CMP process. The method for manufacturing a semiconductor device according to claim 13, wherein:

Images