TW200805595A - Fan out type wafer level package structure and method of the same - Google Patents

Fan out type wafer level package structure and method of the same Download PDF

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Publication number
TW200805595A
TW200805595A TW095129072A TW95129072A TW200805595A TW 200805595 A TW200805595 A TW 200805595A TW 095129072 A TW095129072 A TW 095129072A TW 95129072 A TW95129072 A TW 95129072A TW 200805595 A TW200805595 A TW 200805595A
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TW
Taiwan
Prior art keywords
layer
dielectric layer
wire
type package
diffusion type
Prior art date
Application number
TW095129072A
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Chinese (zh)
Inventor
Wen-Kun Yang
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from US11/456,141 external-priority patent/US7514767B2/en
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW200805595A publication Critical patent/TW200805595A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.

Description

200805595 絕緣層132 錫球136 切割線138 環氧化物層140 :、本案若有化學式時，請揭示最能顯 特徵的化學式： 九、發明說明： 【舍明所屬之技術領域】 本發明與-種半導體之封裝㈣，特別是—種擴散式 (-_ type)晶圓型態封裝（wafer lev ac e ; WLP )。 【先前技術】 半體的技術已經發展的相當的迅速，特別地是半導 體晶粒（dies)有朝向小型化的趨勢。然而，對於半導體 晶粒之功能的需求相對的具有多樣化的趨勢。也就是說， 導體晶粒在-個很小的區域中必須具有更多的輸入 增出古塾⑽pads)，因而使得引線（pins)的密度也快速 勺提同了 &會導致上述半導體晶粒的封裝變的越來越困 難，並且良率也因此降低了。 上述封裝結構的主要目的在於保護上述晶粒免於受到 夕在的損害。再者，由於上述晶粒所產生的熱必須有效率 i透過上述封裝結構來擴散以確保上述晶粒的運作。 進牛線架封裝技術已經不適合引線密度過高之更 v的丰冷肢0日粒。因此，一新的球陣列（BaHGridA胃·· 200805595 經被發展出來，其可以滿足上述更進-疋千¥體晶粒的封砦雲4。l、+、丄+ <又進步 /而永上述球陣列封裝且右, 就是它的球形引線具有比上述導線架 間距（pnch)，並且上述引線不容易損宝盥 小之 較短的訊號傳遞距離可以有益於提昇操;頻;^ 效率的需求。例如：由、相如等 二更快200805595 Insulation layer 132 Tin ball 136 Cutting line 138 Epoxide layer 140: If there is a chemical formula in this case, please disclose the most characteristic chemical formula: IX. Invention description: [Technical field of Sheming] The present invention Semiconductor package (4), especially a diffuse (-_ type) wafer type package (wafer lev ac e; WLP). [Prior Art] The half-body technique has been developed quite rapidly, and in particular, semiconductor dies tend to be miniaturized. However, the demand for the function of semiconductor dies is relatively diversified. That is to say, the conductor grains must have more input in a small area to increase the number of pads (10), so that the density of the pins is also quickly extracted and the resulting semiconductor grains are caused. The packaging becomes more and more difficult, and the yield is therefore reduced. The main purpose of the above package structure is to protect the above-mentioned crystal grains from damage. Furthermore, since the heat generated by the above-mentioned crystal grains must be efficiently i-transmitted through the above-described package structure to ensure the operation of the above-mentioned crystal grains. Into the cattle wire rack packaging technology has not been suitable for the high density of the lead of the v-cooled limb 0 day. Therefore, a new ball array (BaHGridA stomach · 200805595 has been developed, it can meet the above-mentioned more advanced - 疋 thousand ¥ body grain of the closed cloud 4. l, +, 丄 + < and progress / and never The above-mentioned ball array package and right, that is, its spherical lead has a pitch (pnch) than the above-mentioned lead frame, and the short lead signal transmission distance of the above-mentioned lead wire is not easy to be damaged, which can be beneficial for lifting operation; frequency; For example: by, like, etc. two faster

5,62_鏡專利，其揭露了一球陣;：；；出;之美\國Γ 5’239，198號專利揭露了另一個乂弟 带士认* , 八1示异有一導電圖案 :之FR4底材附著於-印刷電路板（PCB)之上二 擴：：明人所提出之台灣第177,766號專利，其揭露了」 心放式（fan0uttype)晶圓型態封裝（WLp)。5,62_Mirror patent, which reveals a ball array;:;; out; beauty\国Γ 5'239,198 patent reveals another brother-in-law who recognizes *, eighty-one shows a conductive pattern: The FR4 substrate is attached to a printed circuit board (PCB). Two expansions: Taiwan Patent No. 177,766, which is proposed by Ming Ren, discloses a "fan0uttype" wafer type package (WLp).

大:分的封裝技術都是先將—晶圓上的晶粒分離成為 :的晶粒’然後再封裝與測試上述個別的晶粒。另外一 ，稱為日日圓型悲封裝之封裝技術可以在分離個別的晶粒之 刖就封裝上述晶圓上之晶粒。上述晶圓型態封裝具有一些 =處，例如：一個較短的生產週期（cycle time)、較低的 仏格以及不需要填充物（under-fill)或鑄模（molding)。 由Adams等人所提出之美國第5,323,〇51號專利“半導體 曰曰圓型態封裝”揭露了一晶圓型態封裝之技術。上面技術 祸述如下。如圖一所示，一晶粒4形成於一半導體晶圓2 之一表面之上，並且一具有預定圖案之玻璃牆熔塊（frit glass walls ) 8以作為黏合劑之上蓋晶圓（cap wafer ) 6置 於上述半導體晶圓2之上，使得上述玻璃牆熔塊8可以完 全包圍著上述晶粒4。然後，研磨沒有晶粒4之半導體晶 200805595 - 圓2之表面以降低上述半導體晶圓2之高戽，這一個步驟 通常稱為背磨” （“back grinding”）。上述晶粒4密封 在一由上述半導體晶圓2、上蓋晶圓6與玻璃牆熔塊8所 組合形成之預定大小的空腔内。一複數個金屬圖形1〇形成 了複數個電極於上述半導體底材晶圓2之上，其係 上述晶粒4之電姓耦合。一複数個金屬線u氣合哥二·形，成 於上述金屬圖形1〇之外部之複數個墊之上，並且透過洞 14延伸而耦接外面的電性晶粒（未示於圖中）。 -如上所述，上述晶粒的大小是非常小的，並且輸入/ 輸出墊是形成於傳統習知技術之晶粒表面上。因此，上述 墊的數目是受到限制的，並且墊之間太短的間距會導致訊 f輕合或訊號干擾的問題。上料錫也會因為上述塾之間 ^勺間距而谷易形成一銲鍚橋（5〇13打心1<3#)。此外， 漸漸地變得越來越小，並且上述晶粒之積 壯_『封衣不但無法透過一些封裝技術（例如晶片大小封 二：具有標準的大小’並且測試設備、封裝設備等等對 ^些固定大小的絲或封裝也不能持續的被使用。 1發明内容】 明，二Γ八鑑於上述習知技術所提到的問題而提出本笋 構與其目的係在於提供擴散式晶圓細 構以維;i:H:目的在於提供擴散式晶圓型態封裝之結 間距述封裝結構之二個相鄰之間的塾具有-適當的 200805595 此外，本發明之再-目的在於提供擴散式晶圓型態封 衣之結構以避免訊號耗合與訊號干擾的情形。 再者，本發明之目的在於降低封裝結構之價柊。 另外，本發明之又-目的在於提高封袭結構:良率。 本發明之另-目的在於提供具有可調整大小之封裝結 構，其係利用測試設備、封褒設-儀.等等_來達到固定― 晶粒或封裝體。 ’ 圓型=述，本發明之再-目的在於提供-種擴散式晶 圓型悲封裝之方法。首先’一複數個晶粒附著到一金屬合 :基：之上。一第一材料層形成於上述金羼合金基底之 、、中上述第一材料層（矽膠）填滿於 底之上之複數個晶粒之間，並且上述第 曰 I且上迷弟—材料層與複數個 曰曰拉之，面在約略相同的高度。然後，烘烤上述第一材料 θ #第材料層（SINR)形成於上述第—材料層與複-數 曰“之上。蝕刻上述複數個晶粒之墊之上之第二材料層 ::部分區域’以形成第一開口。之後，供烤上述第二材 接觸&電層（金屬佈線層）形成於上述第一開口 別與上述墊作電性耗合。一光阻層形成於上述接 層之上。去除上述光阻層之一部分區域以形成一扇 =案並且暴露上述接觸導電層。然後，導線形成於上述 :圖案之上，並且上述導線分別與上述接觸導電層耦 、曾綠/?:剩餘之上述光阻層。之後，—絕緣層形成於上述 ^第二材料層之上、去除上述導線上之絕緣層之一部 刀區或以$成第二開口。然後’烘烤上述絕緣層&最後， 200805595 锻燒凸塊下金屬化層（under ball metallurgy ; UBM )結構 (未示於圖中）與銲接球於上述第二開口之上，並且切割 上述基底以絕緣上述複數個晶粒。 本發明也提供一種擴散式型態封裝之結構。上述封裝 結構包括：一金屬合金基底、一晶粒、第一介電層、第二 介電層、接觸導電層、導線、絕緣·詹、一凸 1 兔全-屬1層與 re-JNi 銲接球。其中所述之金屬合金基底包含鐵j鎳合金 all〇y )、鐵-鎳-姑合金（Fe-Ni-Co alloy )、銅-鐵合金（〇1^6 alloy )、銅 _鉻合金（cu_Cr alloy )、銅-鎳-石夕合金（Cu-Ni-Si alloy)、銅-錫合金（Cu-Sn alloy)或鐵-鎳合金層（laminated) 玻璃纖維材料，上述晶粒係附著到上述金屬合金基底之 上。上述第一介電層形成於上述金屬合金基底之上，其係 在上述金屬合金基底之上之晶粒之外填滿上述第一介電 曰〃中上述第一介電層與晶粒之表面在約略相同的高 度。上述第二介電層形成於第一介電層與晶粒之上，並且 上述第二介電層具有第一開口形成於上述晶粒之墊之上。 觸導電層形成於上述第—開口之上以分別與上述整 接二：Γ上述導線形成於上述第二介電層與相對應的 上，並且上述導線從上述相對應的接觸導電 二:m對應的第一端點’其中上述相對應的端點 疋在上述弟二介電層之表面之内。上 導線與第二介兩呙夕, 、巴、象層形成於上述 成於上二導=二述絕緣層具有第二開口形 上述第二開。之上金屬化層舆銲接球形成於 <上，其係分別與上述導線耦合。 200805595 【實施方式】 本發明之一些實施例將於目前詳細地描述。然而，除 了=明確地描述之外，本發明也可以在一寬廣的範圍之 其它貫施例中被實施，並且本發明之範圍也不限制於 述之專利範圍。 田 一然而’不同構成要素之元#並不依實際的n—来顧-不。一些相關元件的大小是擴大的，並且無意義的部分沒 籲有晝出來，這樣比較容易提供本發明之一更清楚的描述與 理解。 本發明之本質在於拾取與置放標準晶粒於一新的基底 之f以得到一比傳統的晶圓上之晶粒之間的距離更適i與 更=廣的距離。因此，上述封裝結構具有一比上述晶ϋ j還大的球陣列以避免具有太接近的球間距的問題。此 外，上述晶粒可以與被動元件（例如：電容）或其它具有 並列結構或堆疊結構之晶粒一起封裝。本發明之詳細^法 • 將描述如下。 八有Β日粒之元成製造石夕晶圓置放於一框架或底盤 _( ame or tray )上，然後藉由背磨（back &卯_ )上述 完成製造矽晶圓可以得到一範圍為5〇〜3〇〇微米（micron) 之上述完成製造之石夕晶圓厚度。上述之完成製造之砂晶圓 厚度可以很容易地切割上述石夕晶圓上之晶粒以成為個別的 晶粒。如果不經過背磨（backlapping)而上述之完成製造 石夕晶圓不會很難切割的話，上述背磨（back p 是可以被省略的。於切割前，一介電層是選擇二= 200805595 上述完成製造矽晶圓之上以保護晶粒免於損害。 上述個別晶粒接著經過測試以從其中選擇標準的良好 晶粒110。然後，拿取上述標準良好的晶粒11〇並 合金基底1〇〇之上，使得二個相㈣ :之I有一個更寬廣的距離，並且利用一具有良好熱傳 V I·生之UV烘烤型態材料與/或熱烘烤型態附著材—料（未 示）附著上述晶粒110到上述金屬合金基底100之上，二 圖2A所示。上述附著材料係利用塗佈方式形成在上述金 屬合金基底100之上’並且上述附著材料之厚度最好 20〜60微米（mierc)n)之間。當上述晶粒⑽置放於上述 附著材料時，上述附著材料係藉由uv光或熱能來烘烤:L 上述置於金屬合金基底1〇〇之上之二個相鄰晶粒之間的距 離係被安排而具有足夠寬廣的空間以形成以下步驟之扇出 (fanout)終端引線（例如球陣列）。因此，本發明可以維 持一個理想的《間距以避免訊號耦合與訊號干擾的問題、: 亚且可以增加輪入/輸出（1/〇)埠（球）的數 其 粒的大小也變的更小了。上述晶粒110具有輸入/輪出（Ι/0) 墊U6形成於上表面（如圖四所示）。被動元件114或晶粒 112也置放於上述金屬合金基底1〇〇之相鄰的位置之二以 得到一濾波或其它功能，如圖二乙與圖二丙所示。 舉例而言，可用於金屬合金基底1〇〇之材料包含鐵_ 鎳合金（Fe-Ni au0y)、鐵_鎳合金層玻璃纖維材料、鐵-鎳_ 钻 5 至（Fe-Ni-C〇 alloy )、銅-鐵合金（Cu-Fe alloy )、銅· 絡合金（ Cu'Crall〇y)、銅-鎳-石夕合金（Cu-Ni-Sialloy)或 200805595 銅-錫合金（Cu-SnaU〇y)等等，且其中所述之金屬合金基 底之形狀可為圓形或矩形。例如，鐵_鎳合金包含AS TM F3〇 或Alloy 42 ( 42%鎳-58%鐵），其中所述之鐵-鎳合金合成 物包含42%鎳與58%鐵，而A11〇y 42之主要特性包含大 一..、々"於 4.0 至 4.7 ( PPm/£>c )之膨脹係數、約 12 ( w/m-t：) 之熱傳導樣數、約7〇( # ◦ am )之電阻值以及约6-沉) ‘ 之抗彎曲強度；此外，前述鐵_鎳_鈷合金包含astm Fi5 •或K〇Var ( 29Ni 17Co54Fe )，其中所述之鐵-鎳·鈷合金合成 物包含29'%鎳、17%鈷與54%鐵，且Kovar之主要特性包 。3大、·勺；丨於5.1至8.7 ( ppm/ C )之膨脹係數、約4〇 ( w/m_ C )之熱傳導係數、約49 ( # Q -cm )之電阻值。換言之， 本！X明内所述之金屬合金亦被可用於引線合金/引線框架 合金。而這些特殊合金，如：ASTM F3〇或AU〇y 42、astm F15或K〇var，由於其近似陶瓷之熱膨脹係數及其高度可 塑性使之被廣泛地接受，Alloy 42與K〇var 一般係用於陶 i究晶片載體之形成引線/引線框架之用。如前所述，這兩種 材料之熱膨脹係數與矽之熱膨脹係數（2·3 ppm/C>c )和陶 器基底之熱膨脹係數（3.4至7.4 ppm/t：)配合良好，且 Alloy 42與K〇var亦具有較佳之抗彎曲強度，例如aii〇”2 具有620(]\«>〇抗彎曲強度，與一般僅具38〇至55〇(河1^) 抗彎曲強度之銅合金相比可見其優勢。用於引線之材料必 須具備導電性以作為信號傳遞之電性通道媒介，此外用於 引線之材料更需抗腐韻’因為敍錄會增加引線之電阻值進 而產生電性失效，更可能最終導致機械裂痕，本發明内可 200805595 -用於引線之材料包含鐵·鎳合金、鐵-人人 金、=各合金、銅I石夕合金或鋼1合全°孟、銅-鐵合 在本發明中，同時封裝於上述封/專專。 動兀件之數目是不受限制的 冓中之晶粒與被 與被動元件也可同時被封裝在相同二=三個晶粒 之附著材料最好是良好的衣：構中的。本發 t i才c #巳ra认θ 、寻^材料，這樣才▼以ϋ— 上过（日於晶粒11G與金屬合金基底 使付 產生：問題（例如應力)被避免。間溫度差異所 但多實施例雖僅在圖示中描述單-層之導線， 線13。盘第—發明之中’如圖十四中所示。導 _之表上，—具有黏性之材料層⑽形成於基底 成的以::斤:應的圖與其圖示是透過-個單-的晶粒來完 述與理‘簡單化並提供一個對本發明之較清楚的描 第材料層12〇係形成而填滿於上述相鄰 且上則-㈣層12G與晶粒HO之表面在相同 又上述弟一材料層120之材料可以是UV烘烤型態 Z或熱供烤型態材料。然後’藉由―或熱能烘烤上述 弟「材料層！2〇。上述第一材料層12〇可以藉由一網印的 方法或-微影的方法來形成。上述第—材料層ug可以用 轉為-緩衝層以降低由於溫度等所產生之應力。上述第 材料層120可以是一 17¥與/或熱烘烤材料，例如··矽膠、 12 200805595 -環氧化物層、樹脂、BCB等等。上述所提之包括金屬合金 基底100、晶粒110與第一材料層12〇之結構1〇2顗似一 晶圓具有晶粒11 〇形成於其上。 如圖四所示，一第二材料層122塗佈形成於上述結構 —102之上。上述第二材料層122之材料可以是UV烘烤材 料或熱烘烤材料，例如：BCB、聚亞醯胺（1>1)、..幻_17〇. (由Shin-Etsu化學有限公司所製造）等等。然後，利用 一光罩來去除上述晶粒11〇之塾116之上之第二材料層 122之：分區域，以形成第-開口 124於上述墊116之上， t藉自UV或熱過來烘烤上述第二材料層^ 。接著， ，地利用電滎餘刻（咖）或濕餘刻（wet etching)來 =上述塾116之表面以確保沒有殘留的材料留在上述塾 116之上。 ^觸導电層（金屬佈線層）126形成於上 二^：，面之上，如圖六所示。上述接觸導電層 導電# 12:可::？Τ〇、’（CU)或其組合。上述接觸 ^ ^ + , 物理方法、化學方法或其組合之形 成：上述形成方法例如：化學氣相沉積 ===積(。VD)、_與蒸鑛。-光阻層 光罩之= 二觸導電層126之上，然後，藉由利用-:之曝先顯衫以形成上述光之 扇出圖案具有複數個扇 之扇出圖案。上述 上述第二材料層122之^ 口 ’ 5亥開口係從上述墊116到 相鄰的扇出開口之端面内之端點。也就是說’二個 您知點之間距可以比二個相鄰的墊116之 13 200805595 間距寬廣。之後，藉由電鍍方法，導線130形成於上述接 觸導電層126之上，如圖七（垂直圖示）與圖八所示（橫 向圖不，沿著圖七之「a_a，」方向）。上述導線13〇之材 料較佳的是鎳（Ni)、銅（Cu)、金（Au)或其組合。 請參考圖九，蝕刻上述光阻層128與接觸導電層126, 然後，一絕緣層132形成於上述導線13〇與第二材蜱層i22 之上，亚且藉由一光罩使得第二開口 134形成於上述導線 130之上。接著，烘烤上述絕緣層132。上述絕緣層 可以解由旋轉塗佈或網印的方式來形成。上述第二開口 134之位置可以形成上述晶粒11〇或第一材料層之 上較仏地疋分別地形成於上述導線130之端點附近，所 乂相郴的一個第一開口 134之間有一適宜距離可以形成錫 球136於第二開口 134之上，這樣就沒有訊號耦合與訊號 干擾的問題。 請參考圖十，一環氧化物層140形成於上述金屬合金 基底100之背表面之上’也就是沒有晶粒11〇形成於其上 之至屬口 &基底100之表面。然後’就由一光罩使得一上 標形成於上職氧化物層14G之上，並錄烤上述環氧化 物層140或者疋利用印刷模板油印，熱能WV烘烤或雷 射標記（1崎職k)以形成一上標。上述上標是用來確認 兀件的：稱。上述形成環氧化物層⑽之步驟也可以被省 略。接者，上述錫球136置於上述第二開口 134之上，並 且藉由一紅外線回流（IRrefl〇w)的方法將錫球136與上 述H 30之表面連接在一起。而在塾圈陣列封裝（: 200805595The large: sub-package technique is to first separate the die on the wafer into: grains and then package and test the individual die. In addition, a packaging technology called a Japanese-day-type sad package can encapsulate the crystal grains on the wafer after separating individual dies. The wafer type package described above has some =, for example, a shorter cycle time, a lower grid, and no under-fill or molding. U.S. Patent No. 5,323, filed to A.S. Pat. The above technique is described below. As shown in FIG. 1, a die 4 is formed on one surface of a semiconductor wafer 2, and a frit glass wall 8 having a predetermined pattern is used as a cap wafer wafer. 6 is placed on the semiconductor wafer 2 above, so that the glass frit 8 can completely surround the die 4. Then, the surface of the semiconductor crystal 200805595-circle 2 having no crystal grains 4 is ground to lower the height of the above-mentioned semiconductor wafer 2. This step is generally referred to as "back grinding". The above-mentioned crystal grains 4 are sealed in one a predetermined size of the cavity formed by the combination of the semiconductor wafer 2, the upper cover wafer 6 and the glass wall frit 8. A plurality of metal patterns 1 〇 form a plurality of electrodes on the semiconductor substrate wafer 2 It is coupled by the electric number of the above-mentioned crystal grains 4. A plurality of metal wires are formed on the plurality of pads outside the metal pattern 1 and are coupled to the outside through the hole 14 Electrical grains (not shown) - as described above, the size of the above-mentioned crystal grains is very small, and the input/output pads are formed on the surface of the conventional conventional art. Therefore, the above-mentioned pads The number is limited, and the short spacing between the pads can cause the problem of light-fitting or signal interference. The tin can also form a solder bridge due to the spacing between the above-mentioned turns. 〇13打心1<3#). In addition, gradually It is getting smaller and smaller, and the above-mentioned crystal grains are strong. "The seal is not only unable to pass some packaging technology (such as wafer size seal 2: has a standard size) and test equipment, packaging equipment, etc. Or the package can not be used continuously. 1 SUMMARY OF THE INVENTION In view of the problems mentioned in the above-mentioned prior art, the present invention is directed to providing a diffusion wafer to be dimensioned in dimensions; i:H The purpose of the present invention is to provide a diffused wafer type seal for the purpose of providing a diffusion wafer type package with a junction spacing between two adjacent turns of the package structure - suitable 200805595. The structure is to avoid signal interference and signal interference. Furthermore, the object of the present invention is to reduce the price of the package structure. In addition, the present invention is further aimed at improving the encapsulation structure: yield. It is to provide a package structure with a resizable size, which is to use a test device, a package, a device, etc. to achieve a fixed-grain or package. 'Circular=description, the re-purpose of the present invention is A method for diffusing wafer type sad packaging. First, a plurality of crystal grains are attached to a metal bond: a base: a first material layer is formed on the metal tantalum alloy substrate, and the first The material layer (silicone) is filled between the plurality of crystal grains on the bottom, and the above-mentioned third and upper layers of the material layer and the plurality of layers are pulled at the same height. Then, baking The first material θ #material layer (SINR) is formed on the first material layer and the complex-number 曰". The second material layer on the pad of the plurality of dies is etched: a partial region to form a first opening, after which the second material contact & electrical layer (metal wiring layer) is formed on the first opening to electrically interfere with the pad. A photoresist layer is formed on the bonding layer. A portion of the photoresist layer is removed to form a film and expose the contact conductive layer. Then, a wire is formed on the above-mentioned pattern, and the above-mentioned wires are respectively coupled to the above-mentioned contact conductive layer, and are green/?: the remaining photoresist layer. Thereafter, an insulating layer is formed on the second material layer to remove one of the insulating layers on the conductor or to form a second opening. Then, 'baking the above insulating layer & Finally, 200805595, an under ball metallurgy (UBM) structure (not shown) and a solder ball over the second opening, and cutting the substrate Insulating the plurality of crystal grains described above. The present invention also provides a structure of a diffused type package. The package structure comprises: a metal alloy substrate, a die, a first dielectric layer, a second dielectric layer, a contact conductive layer, a wire, an insulating · Zhan, a convex 1 rabbit full-genus 1 layer and re-JNi welding ball. The metal alloy substrate described therein comprises iron j nickel alloy all〇y), iron-nickel-gu alloy (Fe-Ni-Co alloy), copper-iron alloy (〇1^6 alloy), copper_chromium alloy (cu_Cr alloy) ), Cu-Ni-Si alloy, Cu-Sn alloy or iron-nickel alloy laminated glass fiber material, the above-mentioned crystal grain is attached to the above metal alloy Above the substrate. The first dielectric layer is formed on the metal alloy substrate, and the surface of the first dielectric layer and the first surface of the first dielectric layer is filled outside the crystal grains on the metal alloy substrate. At about the same height. The second dielectric layer is formed on the first dielectric layer and the die, and the second dielectric layer has a first opening formed on the pad of the die. The contact conductive layer is formed on the first opening to respectively form the second wire: the wire is formed on the second dielectric layer and the corresponding wire, and the wire corresponds to the corresponding contact conductive two: m The first endpoint 'where the corresponding endpoint is within the surface of the second dielectric layer. The upper wire and the second dielectric layer are formed on the upper side, and the image layer is formed on the upper side of the second conductor. The insulating layer has a second opening shape and the second opening. The upper metallization layer solder balls are formed on the <these, respectively, which are coupled to the above-mentioned wires. 200805595 [Embodiment] Some embodiments of the present invention will now be described in detail. However, the present invention may be embodied in other specific embodiments without departing from the scope of the invention, and the scope of the invention is not limited to the scope of the invention. Tian Yi, however, the yuan of the different constituent elements does not depend on the actual n--not. The size of some of the related elements is expanded, and the meaningless parts are not smothered, which makes it easier to provide a clearer description and understanding of one of the present inventions. The essence of the present invention is to pick and place standard dies on a new substrate to obtain a better distance than the distance between the dies on a conventional wafer. Therefore, the above package structure has a ball array larger than the above-described wafer j to avoid the problem of having a ball pitch that is too close. In addition, the above-described dies may be packaged with passive components (e.g., capacitors) or other dies having a side-by-side structure or a stacked structure. The detailed method of the present invention will be described below. Eight Β 粒 之 制造 制造 制造 制造 制造 制造 制造 制造 制造 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆The thickness of the ruthenium wafer manufactured by the above is 5 〇 to 3 〇〇 micron (micron). The thickness of the sand wafer to be manufactured as described above can easily cut the crystal grains on the above-mentioned silicon wafer to become individual crystal grains. If the above-mentioned finish is not difficult to cut without backlapping, the back grinding can be omitted. Before the cutting, a dielectric layer is selected as the second = 200805595. The fabrication of the germanium wafer is completed to protect the die from damage. The individual die described above is then tested to select a standard good die 110 therefrom. Then, take the above-mentioned standard good grain 11〇 and alloy substrate 1〇 Above the crucible, the two phases (four): I have a wider distance, and utilize a UV-bake profile material with good heat transfer VI and/or a hot-bake profile attachment material (not The above-mentioned die 110 is attached to the above-mentioned metal alloy substrate 100, as shown in FIG. 2A. The above-mentioned adhesive material is formed on the metal alloy substrate 100 by coating method, and the thickness of the above-mentioned adhesive material is preferably 20~ Between 60 micrometers (mierc) n). When the die (10) is placed on the adhesive material, the adhesive material is baked by uv light or thermal energy: L. The distance between two adjacent crystal grains placed on the metal alloy substrate 1〇〇 The system is arranged to have a sufficiently wide space to form the fanout terminal leads (e.g., ball arrays) of the following steps. Therefore, the present invention can maintain an ideal "pitch to avoid signal coupling and signal interference problems, and can increase the number of rounds/outputs (1/〇) 埠 (balls) and the size of the particles becomes smaller. It is. The die 110 has an input/rounding (Ι/0) pad U6 formed on the upper surface (as shown in FIG. 4). The passive component 114 or the die 112 is also placed in the adjacent position of the metal alloy substrate 1 to obtain a filtering or other function, as shown in Fig. 2B and Fig. 2C. For example, the material that can be used for the metal alloy substrate 1 铁 comprises iron-nickel alloy (Fe-Ni au0y), iron-nickel alloy layer glass fiber material, iron-nickel _ drill 5 to (Fe-Ni-C〇alloy ), Cu-Fe alloy, Cu'Crall〇y, Cu-Ni-Sialloy or 200805595 copper-tin alloy (Cu-SnaU〇y) And so on, and the shape of the metal alloy substrate described therein may be circular or rectangular. For example, the iron-nickel alloy comprises ASTM F3® or Alloy 42 (42% nickel-58% iron), wherein the iron-nickel alloy composition comprises 42% nickel and 58% iron, while A11〇y 42 is the main The characteristics include the expansion coefficient of the first one.., 々" from 4.0 to 4.7 (PPm/£>c), the heat conduction sample of about 12 (w/mt:), and the resistance value of about 7〇 (# ◦ am ) And an anti-bending strength of about 6-sinking; in addition, the aforementioned iron-nickel-cobalt alloy comprises astm Fi5 • or K〇Var (29Ni 17Co54Fe ), wherein the iron-nickel·cobalt alloy composition contains 29% Nickel, 17% cobalt and 54% iron, and the main properties of Kovar. 3 large, · spoon; the expansion coefficient of 5.1 to 8.7 (ppm / C), the thermal conductivity of about 4 〇 (w / m_ C), the resistance of about 49 ( # Q - cm). In other words, Ben! The metal alloys described in X Ming are also applicable to lead alloy/lead frame alloys. These special alloys, such as ASTM F3〇 or AU〇y 42, astm F15 or K〇var, are widely accepted due to their approximate ceramic thermal expansion coefficient and their high degree of plasticity. Alloy 42 and K〇var are generally used. It is used to form the lead/lead frame of the wafer carrier. As mentioned earlier, the thermal expansion coefficients of these two materials are well matched with the thermal expansion coefficient of 矽 (2.3 ppm/C>c) and the thermal expansion coefficient of the ceramic substrate (3.4 to 7.4 ppm/t:), and Alloy 42 and K 〇var also has better flexural strength. For example, aii〇”2 has 620(]\«>〇 bending strength, compared with copper alloys which generally have only 38〇 to 55〇 (河1^) bending strength. It can be seen that the material used for the lead must be electrically conductive as the electrical channel medium for signal transmission, and the material used for the lead wire needs to be resistant to corrosion as the description increases the resistance value of the lead and causes electrical failure. More likely to eventually lead to mechanical cracks, the present invention can be used in the 200805595 - the material used for the lead comprises iron · nickel alloy, iron - human gold, = each alloy, copper I stone alloy or steel 1 all full Meng, copper - iron In the present invention, the package is sealed at the same time. The number of the movable members is unrestricted, and the die in the crucible can be packaged in the same two = three crystal grains at the same time as the passive component. The material is preferably a good clothing: in the structure. The hair ti only c #巳ra recognized θ, 寻^材料, so that ϋ 上 上 上 上 上 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日Describe the single-layer wire, line 13. The disk-inventive' is shown in Figure 14. On the table, the viscous material layer (10) is formed on the substrate to: The figure and its illustration are through the simplification of a single-grained grain and provide a clearer layer 12 of the present invention to fill the adjacent and above- (4) The layer 12G and the surface of the grain HO are the same, and the material of the material layer 120 may be a UV baking type Z or a hot baking type material. Then, the material layer is baked by the heat energy. The first material layer 12 can be formed by a screen printing method or a lithography method. The first material layer ug can be converted into a buffer layer to reduce stress caused by temperature or the like. The material layer 120 may be a 17¥ and/or a hot baking material, such as 矽 、, 12 200805595 An epoxide layer, a resin, a BCB, etc. The above-mentioned structure comprising the metal alloy substrate 100, the die 110 and the first material layer 12〇 is similar to a wafer having a crystal grain 11 〇 formed thereon As shown in Fig. 4, a second material layer 122 is coated on the structure - 102. The material of the second material layer 122 may be a UV baking material or a hot baking material, for example: BCB, poly Amidoxime (1>1), .. illusion_17〇. (manufactured by Shin-Etsu Chemical Co., Ltd.), etc. Then, a mask is used to remove the above-mentioned grain 11 The two material layers 122 are sub-regions to form a first opening 124 above the pad 116, and the second material layer is baked by UV or heat. Next, the surface of the crucible 116 is used to determine the surface of the crucible 116 to ensure that no residual material remains on the crucible 116. The contact conductive layer (metal wiring layer) 126 is formed on the upper surface, as shown in FIG. The above contact conductive layer is electrically conductive #12: can be::? Τ〇, '(CU) or a combination thereof. The above contact ^ ^ + , physical method, chemical method or a combination thereof is formed by the above formation method: for example, chemical vapor deposition === product (.VD), _ and steamed ore. - Photoresist layer The photomask is over the two-contact conductive layer 126, and then a fan-out pattern having a plurality of fans is formed by using the -: exposure lamp to form the fan-out pattern. The opening of the second material layer 122 is an end point from the pad 116 to the end face of the adjacent fan-out opening. That is to say, the distance between the two points can be wider than the distance between the two adjacent pads 116 200805595. Thereafter, a wire 130 is formed on the contact conductive layer 126 by a plating method as shown in Fig. 7 (vertical illustration) and Fig. 8 (the horizontal direction is not, along the "a_a," direction of Fig. 7). The material of the above conductor 13 is preferably nickel (Ni), copper (Cu), gold (Au) or a combination thereof. Referring to FIG. 9 , the photoresist layer 128 and the contact conductive layer 126 are etched. Then, an insulating layer 132 is formed on the conductive layer 13 〇 and the second 蜱 layer i22 , and the second opening is formed by a reticle. 134 is formed on the above-mentioned wire 130. Next, the insulating layer 132 is baked. The above insulating layer can be formed by spin coating or screen printing. The position of the second opening 134 may be formed between the first die 134 and the first die 134 of the first material layer. A suitable distance can form the solder ball 136 over the second opening 134, so that there is no problem of signal coupling and signal interference. Referring to FIG. 10, an epoxide layer 140 is formed over the back surface of the above-described metal alloy substrate 100, that is, the surface of the substrate 100 which is formed without the crystal grains 11 。. Then 'a mask is formed on top of the upper oxide layer 14G, and the above epoxide layer 140 is recorded or stenciled with a print template, thermal WV baking or laser marking (1 Saki k) to form a superscript. The above superscript is used to confirm the condition of the piece: The above steps of forming the epoxide layer (10) can also be omitted. The solder ball 136 is placed on the second opening 134, and the solder ball 136 is connected to the surface of the H 30 by an infrared reflow method. And in the circle array package (: 200805595

Land grid array )製程中將省略此步驟。 最後，前面所述之封裝金屬合金基底1〇〇沿著切割線 138進行切割以隔絕個別的封裝積體電路。如上所述，上 述封裝積體電路可以包括被動元件142與晶粒n〇，如圖 十一所示。上述封裝積體電路也可以是一並列結構之多晶 粒，如圖十二所示。·… …、 本發明之封裝方法甚至可以應用以形成具有堆疊結構 之多晶粒及/或多層導線。請參考第十三圖，在形成上述絕 緣層132或第二開口 134之步驟之後，於晶粒11〇之垂直 方向將晶粒110a置於上述絕緣層132之上。然後，第三材 料層120a、第四材料層122a與第二接觸導電層u6a也依 序形成。蝕刻第三材料層12〇a、第四材料層122a與絕緣 f 132，以形成第三開口。之後，導電材料148置於上述 弟三開口之内，並且上述導電材料148與上述導線^^耦 合。上述導電材料148可以是一銲錫。接著，類似上述之 圖七到圖十之圖示，-第二導線！施、—第二絕緣層必 與錫球136依序形成》類似地，上述第三材料層i2〇a與第 四材料層、122a之材料可以是uv烘烤型態或熱|烤型態之 材料，上述第二接觸導電層12以之較佳的材料是鈦（丁丨）、 T (CU)或其組合；而上述第二導線ma之較佳的材料 疋銅（Cii)、在臬（Ni)、金（Au)或其組合。雖然圖十三僅 僅顯示了-具有二個晶粒之封裝堆疊結構，很明顯地:個 比二個晶粒還多之堆疊封裝結構也可以由上面所描述的方 式得到。 15 200805595 纽，根據本發明，上述之封裝結構可以 封 L结構之二個相鄰之間的錫球具有的間ϋ = 本發明可以避免訊號耗合與訊號干擾的情形。再 二月也利用了-個玻璃底材提供給LCD，並且上述玻璃= -^大ί是很大的，所以本發明可以降低上述封裳結構的價 ^提南上述封裝結構的良率。料，本發明钱裝、… 大小可以很容易地調整以適合測試設備、封裝設備等等。 1上，領域技一藝者，本發明雖以較佳實例闡明如 精神以限定本發明之精神。在不脫離本發明之 t申;:所作之修ί與類似的配置，均應包含在下述 槿日月虛，乾圍内’此範圍應覆蓋所有類似修改與類似結 構’且應做最寬廣的詮釋。 【圖式間單說明】 圖:為傳統技術之一半導體晶圓型態封裝之示音圖。 *心圖Γ甲到圖二丙為利用拿與取之方式以重置標準的晶 拉於一新基底之示意圖。 圖三為形成第一材料層於金屬合金基底之上之示意 圖。 " =四為形成第二材料層於第一材料層之上之示意圖。 以形晶粒之塾之上之第二材料層之一部分區域 战弟開口之示意圖。 圖Ζ、為形成接觸導電層於第一開口之上之示意圖。 圖七為^ 一 巧稽由一光阻層以形成導線於扇出圖案之上之縱 向示意圖。 16 200805595 圖八為藉由一光阻層沿著圖七之、，」以形成導線 於扇出圖案之上之橫向示意圖。 圖九為形成絕緣層於上述導線與第二材料層之上之 意圖。 日 ” 圖十為根據本發明之一封裝結構之示意圖。 之 圖十一為根據本發明之一具有一晶粒與一被_-動„元件 封裝結構之示意圖。 之 一圖十二為根據本發明之一具有二個晶粒之封裝結構 示意圖。 圖十二為根據本發明之一具有二個晶粒之封裝堆疊垆 構之示意圖。 ^ 意圖 圖十四為據本發明之一具有多層導線之封裝結構 之示 【主要元件符號說明】 半導體晶圓2 晶粒 4、110、112、110a 上蓋晶圓（cap wafer) 6 玻璃牆溶塊8 金屬圖形10 金屬線12 .洞14 金屬合金基底100 結構102 17 200805595 被動元件114、142 墊116 第一材料層120 第二材料層122 第三材料層120a 第四材料層122a 第一開口 124 接觸導電層126 第二接觸導電層126a 光阻層128 導線130 第二導線130a 絕緣層132 第二絕緣層132a 第二開口 134 錫球136 切割線138 環氧化物層140 導電材料148 具有黏性之材料層150This step will be omitted in the Land grid array process. Finally, the previously described packaged metal alloy substrate 1 is cut along the cutting line 138 to isolate the individual package integrated circuits. As described above, the packaged integrated circuit may include the passive component 142 and the die n〇 as shown in FIG. The above packaged integrated circuit may also be a polycrystalline particle of a side-by-side structure as shown in FIG. The packaging method of the present invention can even be applied to form multi-die and/or multilayer wires having a stacked structure. Referring to the thirteenth drawing, after the step of forming the insulating layer 132 or the second opening 134, the die 110a is placed on the insulating layer 132 in the vertical direction of the die 11. Then, the third material layer 120a, the fourth material layer 122a, and the second contact conductive layer u6a are also sequentially formed. The third material layer 12A, the fourth material layer 122a, and the insulating f132 are etched to form a third opening. Thereafter, a conductive material 148 is placed within the above-described three openings, and the above-mentioned conductive material 148 is coupled to the above-mentioned wires. The conductive material 148 may be a solder. Next, similar to the above-mentioned Figure 7 to Figure 10, the second wire! Similarly, the second insulating layer must be formed in sequence with the solder balls 136. The materials of the third material layer i2〇a and the fourth material layer, 122a may be uv baked or hot-roasted. The material of the second contact conductive layer 12 is preferably titanium (butyl), T (CU) or a combination thereof; and the second material of the second wire is preferably copper (Cii), Ni), gold (Au) or a combination thereof. Although FIG. 13 shows only a package stack structure having two crystal grains, it is apparent that a stacked package structure having more than two crystal grains can also be obtained by the above-described method. 15 200805595 纽, according to the present invention, the above package structure can seal the gap between two adjacent solder balls of the L structure. The present invention can avoid signal interference and signal interference. In February, a glass substrate was also supplied to the LCD, and the above glass = - ^ is large, so the present invention can reduce the yield of the above-mentioned package structure. The size of the present invention can be easily adjusted to suit test equipment, packaging equipment, and the like. In the above, the present invention has been exemplified by the preferred embodiments to define the spirit of the present invention. Without departing from the invention, the repairs and similar configurations shall be included in the following days, and the scope shall cover all similar modifications and similar structures and shall be the broadest. Interpretation. [Illustration between drawings] Figure: A sound diagram of a semiconductor wafer type package in one of the conventional technologies. *Heart map armor to Figure 2C is a schematic diagram of the use of take and take to reset the standard crystal on a new substrate. Figure 3 is a schematic illustration of the formation of a first material layer over a metal alloy substrate. " = four is a schematic diagram of forming a second material layer on top of the first material layer. A schematic diagram of a part of the second material layer above the shape of the grain. Figure Ζ is a schematic diagram of forming a contact conductive layer over the first opening. Figure 7 is a longitudinal schematic view of a photoresist layer formed by a photoresist layer over a fan-out pattern. 16 200805595 Figure VIII is a horizontal schematic view of a photoresist layer formed along a fan-out pattern by a photoresist layer along Figure 7. Figure 9 is an illustration of the formation of an insulating layer over the above-described wires and the second material layer. Figure 10 is a schematic view of a package structure in accordance with the present invention. Figure 11 is a schematic illustration of a die and a package structure in accordance with one of the present invention. Figure 12 is a schematic view of a package structure having two dies according to the present invention. Figure 12 is a schematic illustration of a package stack structure having two dies in accordance with the present invention. ^ Intent Figure 14 is a diagram showing a package structure having a plurality of layers of wires according to the present invention. [Main element symbol description] Semiconductor wafer 2 Die 4, 110, 112, 110a Cap wafer 6 Glass wall block 8 Metal pattern 10 Metal wire 12 . Hole 14 Metal alloy substrate 100 Structure 102 17 200805595 Passive element 114, 142 Pad 116 First material layer 120 Second material layer 122 Third material layer 120a Fourth material layer 122a First opening 124 Contact Conductive layer 126 second contact conductive layer 126a photoresist layer 128 wire 130 second wire 130a insulating layer 132 second insulating layer 132a second opening 134 solder ball 136 cutting line 138 epoxide layer 140 conductive material 148 viscous material Layer 150

Claims (1)

200805595 十、申請專利範圍： L 一種擴散式型態封裝之結構，包括： 一金屬合金基底，其中所述之金屬合金基底之材料包含 鐵-錄合金（Fe-Ni alloy )、鐵-錄-銘合金（ alloy )、銅-鐵合金（cu-Fe alloy )、銅-鉻合金 all〇y )、銅·鎳·石夕合金（Cu-Ni-Di alloy )、鋼_錫合金 (Cu-Sn alloy)或鐵-鎳合金層（laminated)玻璃纖維 材料； ' 一晶粒，附著至該金屬合金基底； 一第一介電層，形成於該金屬合金基底之上，其係在該 金屬合金基底之上之該晶粒之外填滿該第一介電層· 一第二介電層，形成於該第一介電層與該晶粒之上，並 且該第二介電層具有第一開口形成於該晶粒之第—墊2200805595 X. Patent application scope: L A diffusion type package structure, comprising: a metal alloy substrate, wherein the metal alloy substrate material comprises Fe-Ni alloy, iron-record-ming Alloy, copper-iron alloy, copper-chromium alloy, copper-nickel alloy, Cu-Ni alloy, copper-nickel alloy Or an iron-nickel alloy laminated fiberglass material; 'a die attached to the metal alloy substrate; a first dielectric layer formed on the metal alloy substrate over the metal alloy substrate The first dielectric layer and a second dielectric layer are formed on the first dielectric layer and the die, and the second dielectric layer has a first opening formed on the die. The first pad of the die 2 -第-接觸導電層，形成於該第一開口之上，以八 該第一墊作電性耦合； 刀一 網Ϊ導線，形成於該第二介電層與該相對應的第-接 ，電層之上，並且該第一導線從該相對 ^層往外延伸到相對應的第1點，其中該_ = 弟—端點是在該第二介電層之表面之内； ，W的 第、/%緣層，形成於該第—導線與該第二介 上，並且該第一絕緣声且右筮 包^之 之上；以及 層具有弟二開口形成於該第—導線 19 200805595 凸塊下金屬化層（under ball metallurgy ; UBM)及/或銲 接球，形成於該第二開口之上，其分別與該第一導線耦 合。 2·如申請專利範15第1項之擴散式型態封裝之結構，其中 〜斤C之第一介電層之表面與該晶粒在約略相同的高度。 3.如申請專利範圍第丨項之擴散式型態封裝之結_構，其中 所述之晶粒包含一被動元件。 _ 4.如中請專利範圍第1項之擴散式型態封裝之結構，其中 所述之晶粒係藉由切割—完成製造之基底而形成。 5. 如申請專利範圍第4項之擴散式型態封裳之結構，其中 所述之疋成製造之基底係利用背磨以得到一厚度約 50〜300微米（micr〇n)之該完成製造基底。 6. 如申請^利範圍帛1項之擴散式型態封裝之結構’其中 所ίί之第；1電層與該第二介電層之材料包括Uv烘烤 型態材料、熱烘烤型態材料與其組合〆 _ 7.如中請專利範圍第i項之擴散式型態封裝之結構，其中 所述之第一接觸導電層包括鈦（Ti)、銅（Cu)與其电 合。 、 8. 如申料利範圍帛1項之擴散式型態封裝之結構，其中 所述之第一導線層包括鎳（Ni)、銅、金（Au)與其组 合' 八 9. 如中請專利範圍第1項之擴散式型態封裝之結構，其中 戶斤述之鐵-鎳合金合成物包含42%鎳·鄕鐵（合金· 10. 如申請專利範圍第i項之擴散式型態封裝之結構，其中 20 200805595 所述之鐵-鎳-鈷合金合成物包含29%鎳_17%鈷_54%鐵 (Kovar) 〇 11.如申請專利範圍第1項之擴散式型態封裝之結構，更包 括一環氧化物層形成於該金屬合金基底之背表面之上。 12·如申請專利範圍第丨項之擴散式型態封裝之結構，其中 所述之絕緣層包括環氧化物層、樹脂、SINR、—聚亞_醯胺 (PI)與其組合。 13.如申請專利範圍第丨項之擴散式型態封裝之結構，更包 括： 一第二晶粒’附著至該金屬合金基底與該第一介電屌 間於該晶粒之垂直方向； &quot; 二第三介電層，形成該金屬合金基底與該第一介電； 間； Θ心 一第四介電層，形於人+ 弟—日日粒之間，並且該第四介電層具開、 於二晶粒之第二塾之上； #弟-開口形成 -弟二接觸導電層，形成於該第三 巧二塾作電性耗合； 之i其分別與 形成於該第一介電層、該第四介電層與該 …0弟—接觸導電層，並且該第二導線係從 應的該第_ 守、、果係攸垓相對 點，复中:接觸導電層往外延伸到相對應的該第二蠕 表面之内之相對應的第二端點係在該第四介電層之 第〜巴緣層，形成於該第一導線、該第四介電層與該 21 200805595 ' 第一介電層之上； 其中該第二絕緣声、兮楚 第一介雪思 5亥弟一介電層與該第二導線上之今 弟一j電層之上形成一第四開口；以及 裏上之石亥 導電材質，填充於該第四開口内，且 導線與該第二導線作電性耦合。、…別與該第- 11申請專㈣13項之難式㈣料之&amp;構置 中所述之第三介電層之表面與該其 的高度。 ，、成弟一日日粒在約略相同 中：述之第三介電層與該第四介電層包括uv烘烤型熊 材料、熱烘烤型態材料與其組合。。 16.如申請專·圍第13項之擴散式型態封裝之結構，其 中所述之第—接觸導電層包括欽、銅與其組合。八 Π.如申請專=範圍第13項之擴散式型態封裝之結構，其 中所述之第二導線包括鎳、銅、金與其組合。 18.如申凊專利範圍第13項之擴散式型態封裝之結構，更 包括一個或多個被動元件形成於該金屬合金基底之上。 22a first contact conductive layer formed on the first opening to electrically couple the first pad; a knife-net wire formed on the second dielectric layer and the corresponding first connection Above the electrical layer, and the first wire extends outward from the opposite layer to a corresponding first point, wherein the _ = brother-end point is within the surface of the second dielectric layer; a /% edge layer formed on the first wire and the second dielectric, and the first insulating sound and the right side of the package; and the layer having the second opening formed in the first wire 19 200805595 An under metallurgy (UBM) and/or a solder ball are formed over the second opening and coupled to the first wire, respectively. 2. The structure of the diffusion type package of claim 1, wherein the surface of the first dielectric layer is at approximately the same height as the die. 3. The junction of the diffusion type package of claim </ RTI> wherein said die comprises a passive component. 4. The structure of a diffusion type package according to the first aspect of the patent, wherein the crystal grains are formed by cutting-finishing the manufactured substrate. 5. The structure of the diffused type of stencil of claim 4, wherein the substrate is manufactured by back grinding to obtain a thickness of about 50 to 300 micrometers (micror〇n). Substrate. 6. For the structure of the diffusion type package of the application of the scope of the first item, the material of the first dielectric layer includes the Uv baking type material and the hot baking type. The material and the combination thereof are as follows: 7. The structure of the diffusion type package of the invention of claim i, wherein the first contact conductive layer comprises titanium (Ti), copper (Cu) and its electrical connection. 8. The structure of the diffusion type package according to the scope of claim 1 wherein the first wire layer comprises nickel (Ni), copper, gold (Au) and its combination '8. The structure of the diffusion type package of the first item, wherein the iron-nickel alloy composition of the household contains 42% nickel and strontium iron (alloy·10, as in the diffusion type package of the patent application scope i) The structure, wherein the iron-nickel-cobalt alloy composition described in 20 200805595 comprises 29% nickel_17% cobalt _54% iron (Kovar) 〇 11. The structure of the diffusion type package according to claim 1 of the patent scope, Further, an epoxide layer is formed on the back surface of the metal alloy substrate. The structure of the diffusion type package according to the scope of the invention, wherein the insulating layer comprises an epoxide layer, a resin, SINR, polypyramidine (PI) and the combination thereof. 13. The structure of the diffusion type package according to the scope of the application of the patent application, further comprising: a second die attached to the metal alloy substrate and the first a dielectric gap in the vertical direction of the die; &quot; two third dielectric layer Forming the metal alloy substrate and the first dielectric; a core-fourth dielectric layer, formed between the human + brother-day particles, and the fourth dielectric layer has an opening and a second grain Above the second ;; #弟-开口形成-二二 contact conductive layer, formed in the third coincidence for electrical consumption; i is formed separately from the first dielectric layer, the fourth The electric layer is in contact with the conductive layer, and the second wire is from the opposite point of the first keeper, the fruit 攸垓, and the second: the contact conductive layer extends outward to the corresponding second worm a corresponding second end point in the surface is formed on the first barrier layer of the fourth dielectric layer, formed on the first conductive line, the fourth dielectric layer, and the 21 200805595 'first dielectric layer The second insulating sound, the first dielectric layer of the first Chu Shisi 5 Haidi and the second electrical layer on the second wire form a fourth opening; and the upper part of the stone a conductive material filled in the fourth opening, and the wire is electrically coupled to the second wire. ..., and the application of the first - 11 application (four) 1 The surface of the third dielectric layer and the height of the third dielectric layer are the same as the height of the third dielectric layer. The fourth dielectric layer comprises a uv baking type bear material, a hot baked type material and a combination thereof. 16. The structure of the diffusion type package according to Item 13 of the application, wherein the first contact The conductive layer comprises a combination of Qin, copper and the like. The structure of the diffusion type package according to claim 13 of the application, wherein the second wire comprises nickel, copper, gold and a combination thereof. The structure of the diffusion type package of claim 13 further includes one or more passive components formed on the metal alloy substrate. twenty two
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8786110B2 (en) 2010-09-24 2014-07-22 J-Devices Corporation Semiconductor device and manufacturing method thereof
US9343396B2 (en) 2010-02-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming IPD in fan-out wafer level chip scale package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343396B2 (en) 2010-02-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming IPD in fan-out wafer level chip scale package
US8786110B2 (en) 2010-09-24 2014-07-22 J-Devices Corporation Semiconductor device and manufacturing method thereof

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