CN107017175A - 用于接合的多撞击工艺 - Google Patents

用于接合的多撞击工艺 Download PDF

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Publication number
CN107017175A
CN107017175A CN201611124232.3A CN201611124232A CN107017175A CN 107017175 A CN107017175 A CN 107017175A CN 201611124232 A CN201611124232 A CN 201611124232A CN 107017175 A CN107017175 A CN 107017175A
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Prior art keywords
package assembling
technique
metal
pad
hit
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CN201611124232.3A
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CN107017175B (zh
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邵栋梁
董志航
施玟伶
陈筱芸
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
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    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/06—Soldering, e.g. brazing, or unsoldering making use of vibrations, e.g. supersonic vibrations
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Abstract

一种方法包括实施第一撞击工艺以使第一封装组件的金属凸块撞击第二封装组件的金属焊盘。金属凸块和金属焊盘的第一个包括铜。金属凸块和金属焊盘的第二个包括铝。该方法还包括实施第二撞击工艺以使金属凸块撞击金属焊盘。实施退火以使金属凸块接合在金属焊盘上。本发明实施例涉及封装及其形成方法以及用于接合的多撞击工艺。

Description

用于接合的多撞击工艺
技术领域
本发明实施例涉及封装及其形成方法以及用于接合的多撞击工艺。
背景技术
由于集成电路的发明，由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了持续地快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。
这些集成改进基本上是二维(2D)的性质，由集成组件占据的体积基本上在半导体晶圆的表面上。虽然光刻中的巨大改进已经引起了2D集成电路形成中的相当大的改进，但是对于二维中获得的密度，存在物理限制。这些限制的一个是这些组件的最小尺寸的需求。同样，当更多器件放入到一个芯片时，需要更复杂的设计。
随着器件数量的增加，额外的限制来自于器件之间的互连件的数量和长度的显著增加。当互连件的数量和长度增加时，电路RC延迟和功耗增加。
因此，探索了三维(3D)集成电路(IC)以解决以上讨论的限制。在3DIC的典型的形成工艺中，形成两个晶圆或管芯(每个均包括一些集成电路)，并且之后接合在一起。接合通常包括使用焊料以接合在铜凸块上形成的镍层。
发明内容
根据本发明的一个实施例，提供了一种用于形成封装件的方法，包括：实施第一撞击工艺以使第一封装组件的金属凸块撞击第二封装组件的金属焊盘，其中，所述金属凸块和所述金属焊盘的第一个包括铜，并且所述金属凸块和所述金属焊盘的第二个包括铝；实施第二撞击工艺以使所述金属凸块撞击所述金属焊盘；以及实施退火以将所述金属凸块接合在所述金属焊盘上。
根据本发明的另一实施例，还提供了一种用于形成封装件的方法，包括：将第一封装组件提高至第二封装组件上方并且与所述第二封装组件间隔开；实施第一撞击工艺以使所述第一封装组件撞击所述第二封装组件；在所述第一撞击工艺之后，将所述第一封装组件提高至所述第二封装组件上方并且与所述第二封装组件间隔开；实施第二撞击工艺以使所述第一封装组件撞击所述第二封装组件；以及退火所述第一封装组件和所述第二封装组件以将所述第一封装组件接合至所述第二封装组件。
根据本发明的又一实施例，还提供了一种封装件结构，包括：第一封装组件，包括含铜凸块；第二封装组件，包括含铝焊盘，其中，所述含铜凸块接合至所述含铝焊盘，并且其中，所述含铜凸块延伸至所述含铝焊盘内；以及金属间化合物(IMC)，将所述含铜凸块连接至所述含铝焊盘，其中，所述金属间化合物包括铜和铝。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图14示出了根据一些实施例的用于形成封装件的管芯/晶圆的形成和接合工艺中的中间阶段的截面图。
图15至图17示出了根据一些实施例的一些接合的封装件的截面图。
图18示出了根据一些实施例的用于通过接合形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例提供了封装件及其形成方法。示出了形成接合结构的中间阶段。讨论了一些实施例的一些改变。贯穿各个视图和示例性实施例，相同的参照标号用于指定相同的元件。
图1至图14示出了根据一些实施例的封装件的形成中的中间阶段的截面图。图1至图14中所示的步骤也示出了图18中所示的示意性工艺流程。
图1示出了封装组件100的截面图。根据本发明的一些实施例，封装组件100是包括有源器件(诸如晶体管和/或管芯)和可能的无源器件(诸如电容器、电感器、电阻器等)的器件晶圆。根据本发明的可选实施例，封装组件100是插入式晶圆，可以包括或可以不包括有源器件和/或无源器件。根据本发明的又另一可选实施例，封装组件100是封装衬底带，可以是其中具有核芯或无核芯的封装衬底。在随后的讨论中，器件晶圆用作示例性封装组件100。本发明的理念也可以应用于插入式晶圆、封装衬底等。
根据本发明的一些实施例，示例性晶圆100包括半导体衬底20和在半导体衬底20的顶面处形成的部件。半导体衬底20可以由晶体硅、晶体锗、硅锗和/或III-V族化合物半导体(诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP)等形成。半导体衬底20也可以包括块状硅衬底或绝缘体上硅(SOI)衬底。可以在半导体衬底20中形成浅沟槽隔离(STI)区域(未示出)以隔离半导体衬底20中的有源区域。虽然未示出，但是也可以形成延伸至半导体衬底20内的贯通孔，其中，该贯通孔用于电互连位于晶圆100的相对侧上的导电部件。
根据本发明的一些实施例，晶圆100包括集成电路器件22(形成在半导体衬底20的顶面上)。示例性集成电路器件22包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。此处未示出集成电路器件22的细节。根据可选实施例，晶圆100用于形成插入器，没有形成有源器件，其中，衬底20可以是半导体衬底或介电衬底。
层间电介质(ILD)24形成在半导体衬底20上方并且填充了集成电路器件22中的晶体管的栅极堆叠件(未示出)之间的间隔。根据一些示例性实施例，ILD 24包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等。可以使用旋涂、可流动化学汽相沉积(FCVD)等形成ILD24。根据本发明的可选实施例，使用诸如等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)等的沉积方法形成ILD 24。
接触插塞28形成在ILD 24中，并且用于将集成电路器件22电连接至上面的金属线和通孔。根据本发明的一些实施例，接触插塞28由从钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金和/或它们的多层中选择的导电材料形成。接触插塞28的形成可以包括在ILD 24中形成开口，将导电材料填充至接触开口，以及实施平坦化(诸如化学机械抛光(CMP))至接触插塞28的顶面以与ILD 24的顶面齐平。
如图1所示，如果有的话，在ILD 24和集成电路器件22上方形成蚀刻停止层26。蚀刻停止层26可以由碳化硅、氮化硅、氮氧化硅、碳氮化硅等形成。蚀刻停止层26也由相对于上面的介电层30具有高蚀刻选择性的材料形成，并且因此蚀刻停止层26可以用于停止介电层30的蚀刻。
图1中还示出了介电层30(在下文中可选地称为金属间介电(IMD)层30)。根据本发明的一些实施例，IMD层30由低k介电材料(具有低于约3.0、约2.5或甚至更低的介电常数(k值))形成。IMD层30由Black Diamond(注册商标的应用材料)、含碳的低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。IMD层30也可以具有低k值(可以低于约3.0、2.5或2.0)。根据本发明的一些实施例，IMD层30的形成可以包括沉积含致孔剂的介电材料并且之后实施固化工艺以逐出致孔剂，并且因此剩余的IMD层30是多孔的。根据可选实施例，IMD层30由非低k介电材料(诸如氧化硅、氮化硅、碳化硅、氮氧化硅等)形成。
在IMD层30中形成导线32。根据一些实施例，导线32包括扩散阻挡层34和位于扩散阻挡层34上方的含铜材料36。扩散阻挡层34可以包括钛、氮化钛、钽、氮化钽等，并且具有防止含铜材料36中的铜扩散至IMD层30的功能。导线32在下文中也称为金属线32。导线32的形成可以包括单镶嵌工艺。
在IMD层30和导线32上方形成蚀刻停止层38和IMD层40。根据本发明的一些实施例，蚀刻停止层38是由从碳化硅、氮化硅、氮氧化硅、碳氮化硅等中选择的介电材料形成。IMD层40可以由低k介电材料或非低k介电材料形成，并且IMD层40的材料可以从用于形成IMD层30的备选材料的相同的组中选择。
形成导电通孔42和导线44以电连接至导线32。根据本发明的一些实施例，导电通孔42和导线44的形成包括形成通孔开口和沟槽，实施毯式沉积以形成导电衬垫，沉积铜或铜合金的薄晶种层(未示出)，并且例如，通过电镀、化学镀、沉积等用导电材料填充剩余的通孔开口和沟槽。导电衬垫可以由钛、氮化钛、钽、氮化钽或其它替代物形成。导电材料可以包括铜、铜合金、银、金、钨、铝等。实施诸如CMP的平坦化以使导电衬垫和导电材料的表面齐平，并且从IMD层40的顶面去除过量的材料。
图1也示意性地示出了更多介电(IMD)层46和位于介电层46中的相应的导线和通孔(未示出)。根据一些示例性实施例，根据封装组件100的路由需求确定IMD层46的数量，并且可以在从0至7的范围。IMD层46的数量等于0意味着随后形成的蚀刻停止层48和介电层56直接形成在IMD层40上方，其中，它们之间没有额外的介电层和导线。IMD层46中的导线和通孔(未示出)可以电连接至集成电路器件22。
在介电层46上方形成蚀刻停止层48和IMD层50。根据本发明的一些实施例，蚀刻停止层48由从用于形成蚀刻停止层26的备选材料的相同的组中选择的介电材料形成，其中，该备选材料可以包括碳化硅、氮化硅、氮氧化硅、碳氮化硅等。IMD层50也可以由低k介电材料或非低k介电材料形成，并且IMD层50的材料可以从用于形成IMD层30和40的备选材料的相同的组中选择。
参照图1，在IMD层50中形成通孔52和导电部件54。通孔52和导电部件54的材料可以从用于形成通孔42和导线44的相同的备选材料中选择。形成工艺也与通孔42和导线44的形成类似，并且因此不在此处重复。导电部件54包括导电焊盘和可能的导线。
参照图2，在IMD层50上方形成介电层62。根据本发明的一些实施例，介电层62由非低k介电材料形成。例如，如图2所示，介电层62包括位于IMD层50上方的层56、位于层56上方的蚀刻停止层58和位于蚀刻停止层58上方的层60。根据本发明的一些示例性实施例，介电层56和60由未掺杂的硅酸盐玻璃(USG)形成，并且蚀刻停止层58由与介电层56和60的材料不同的材料(诸如氮化硅)形成。根据可选实施例，整个介电层62由均质介电材料(诸如USG)形成。
参照图3，形成了沟槽63和通孔开口65，并且暴露了金属部件54的焊盘部分。根据一些实施例，如图3所示，通孔开口65的横向尺寸小于沟槽63的横向尺寸。根据可选实施例，通孔开口65的横向尺寸与沟槽63的横向尺寸基本相同。因此，沟槽63和通孔开口65组合形成了开口(具有从介电层62的顶部表面至底部表面一直延伸的直线边缘)。当介电层62由相同的材料形成时，使用单蚀刻工艺形成开口。
图4示出了通孔64和金属凸块66的形成。根据一些实施例，如图4所示，通孔64和金属凸块66包括扩散阻挡层71和含铜材料73。根据可选实施例(参照图6)，通孔64和金属凸块66包括含铜材料，而没有形成扩散阻挡层。如图4所示的含铜材料73可以具有高于约70％的原子百分比或90％的铜百分比。含铜材料73也可以由基本纯铜(例如，铜原子百分比高于约99％)形成。
在形成金属凸块66之后，实施回蚀刻以允许金属凸块66的至少部分从剩余的介电层62的顶面凸出来。例如，如图5所示，蚀刻介电层60，其中，蚀刻停止层58停止蚀刻，并且在回蚀刻之后暴露蚀刻停止层58。根据可选实施例，在蚀刻介电层60的底部之前，停止蚀刻。例如，时间模式可以用于停止蚀刻。相应地，虚线69用于示出产生的介电层60的顶面。图6示出了在金属凸块66中没有形成扩散阻挡层的结构。图1至图6所示的工艺步骤示出为图18中所示的工艺流程中的步骤302。
图7示出了根据可选实施例的封装组件100的截面图。在这些实施例中，在顶部低k介电层上方形成钝化层68。金属焊盘72形成在钝化层68上方，并且通过金属线和通孔电连接至集成电路器件22。金属焊盘72可以是铝焊盘或铝铜焊盘，并且可以使用其它金属材料。
形成钝化层70以覆盖金属焊盘72的边缘部分，并且金属焊盘72的中心部分通过钝化层70中的开口暴露。每个钝化层68和70均可以是单层或复合层，并且可以由非低k介电材料形成。根据本发明的一些实施例，钝化层68和70的一个或两个是复合层(包括氧化硅层(未示出)和位于氧化硅层上方的氮化硅层(未示出))。
在钝化层70上方形成聚合物层74。聚合物层74可以由聚合物(诸如聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等)形成。图案化聚合物层74，并且形成钝化后互连件(PPI)76，该钝化后互连件(PPI)76包括位于聚合物层74上面的第一部分以及延伸至聚合物层74内以电连接至金属焊盘72的第二部分。在聚合物层74上方形成聚合物层78。聚合物层78可以包括聚酰亚胺或其它聚合物基材料(诸如PBO或BCB)。金属凸块66延伸至聚合物层78内以接触PPI 76。如图所示，金属凸块66可以包括凸块下金属(UBM)和位于UBM上方的含铜材料。
图8示出了根据一些实施例的封装组件200的截面图。封装组件200可以是器件管芯，器件管芯包括半导体衬底120、有源器件122、ILD 124、接触插塞128、金属线132、144和154以及通孔142和152。此外，器件管芯200可以包括低k介电层130、140、146和150。也形成了金属焊盘172以及钝化层168和170。钝化层170的一些部分可以覆盖金属焊盘172的边缘部分。根据一些实施例，金属焊盘172是铝焊盘，铝焊盘具有可以高于约70％的原子百分比、高于约90％的铝百分比或可以由基本纯铝(例如，铝原子百分比高于约99％)形成。
图9至图14示出了根据一些实施例的封装组件100和200的接合中的中间阶段的截面图，其中，在接合中实施多撞击工艺。简化了图9至图13中的封装组件100和200，并且可以参照图1至图8发现封装组件100和200的详细的结构。
图9示出了初始阶段，其中，封装组件100和200彼此间隔开。封装组件100和200可以是离散的管芯或未锯切的晶圆。相应地，图9至图13中所示的接合工艺可以是管芯至管芯接合工艺、晶圆至晶圆接合工艺或管芯至晶圆接合工艺。封装组件100中的金属凸块66包括金属凸块66表面处的氧化物层67。如图13中示意性示出的，氧化物层67也可以在金属凸块66的侧壁上。氧化物层67可以是原生氧化物层。例如，当金属凸块66是铜凸块时，氧化物层67是铜氧化物层。封装组件200中的金属焊盘172包括金属焊盘172表面处的氧化物层167。氧化物层167也可以是原生氧化物层。例如，当金属焊盘172是铝焊盘时，氧化物层167是铝氧化物层。氧化物层67和167是完全地覆盖金属凸块66和金属焊盘172的连续的氧化物层。
例如，使用真空头拿起封装组件100，从而使得金属凸块66与金属焊盘172间隔开。下一步，封装组件100朝向封装组件200移动，从而使得金属凸块66撞击金属焊盘172。相应的工艺步骤如图18中所示的工艺流程中的步骤304所示。如撞击的结果，连续的氧化物层67和167打破成更小的碎片(pieces)。同样，通过现在未连续的氧化物层67和167暴露金属凸块66和金属焊盘172的一些最初覆盖的非氧化表面。
封装组件100的速度(在冲击时)足够大以打破足够百分比的氧化物层67和167。例如，根据形成的撞击多少，暴露冲击的金属凸块66和金属焊盘172的多于10％、20％、30％、40％或50％或更多的非氧化表面。如果实施较少的撞击，则在每个撞击中，则由每个撞击暴露金属凸块66和金属焊盘172的更高的百分比的非氧化表面。为了打破氧化物层67和167，选择的封装组件100和200的相对速度应足够大。例如，在冲击时，金属凸块66和金属焊盘172的相对速度可以高于约100μm/秒。
图10示出了冲击期间封装组件100和200的截面图，其中，氧化物层67和167示出为打破成的更小的碎片，并且通过更小的碎片之间的间隙暴露金属凸块66和金属焊盘172的一些表面。应该理解，虽然图10至图12示出的打破的碎片为更规律的图案，但是氧化物层67和167的打破的碎片的图案是任意的。
参照图11，再次拿起封装组件100直至它与封装组件200间隔开。如图12所示，实施第二撞击工艺。相应的工艺步骤如图18中所示的工艺流程中的步骤306所示。第二撞击工艺导致氧化物层67和167的已经打破的碎片进一步打破成更小的碎片。此外，如第二撞击工艺的结果，通过氧化物层67和167的打破的碎片暴露金属凸块66和金属焊盘172的更多非氧化表面。与第一撞击相比，第二撞击可以导致金属凸块66的暴露的表面的百分比增加多于约10％。在第二撞击工艺冲击时，金属凸块66和金属焊盘172的相对速度可以高于约100μm/秒。
在第二撞击工艺之后，非氧化金属凸块66的一些暴露的表面与非氧化金属焊盘172的暴露的表面直接接触。根据一些实施例，在第二撞击工艺之后，实施更多撞击工艺，每个撞击工艺均导致氧化物层67和167打破成更小的碎片，并且可能导致暴露更多非氧化表面。控制撞击工艺的总数量以防止封装组件100和200的其它部分受到损坏。例如，撞击工艺的总数量小于10。根据可选实施例，在第二撞击工艺之后，没有实施更多的撞击工艺，并且退火封装组件100和200。
根据可选实施例，在整个撞击工艺期间，氧化物层67和相应的氧化物层167保持接触实施撞击工艺。例如，首先将氧化物层67放入至与相应的氧化物层167接触(没有撞击)。下一步，使用工具(与锤子类似，未示出)撞击与封装组件200接触的封装组件100。在每个撞击期间和之间，封装组件100保持与封装组件200接触。
在完成撞击工艺时，金属凸块66的所有与相应的金属焊盘172的非氧化部分直接接触的非氧化表面具有总面积。该总面积和金属凸块66的总底部面积的比率可以大于约30％(倾向于高)，以改进接合的可靠性。
在撞击工艺期间和之间，可以没有加热封装组件100和200，并且可以处于室温(例如，在约17℃和约23℃之间)。在最终的撞击工艺(可以是第二或之后的撞击工艺)之后，金属凸块66保持与相应的金属焊盘172接触而没有再次分隔开。之后，实施退火，期间，金属凸块66也保持与相应的金属凸块172接触。相应的工艺步骤如图18中所示的工艺流程中的步骤308所示。可以在介于约150℃和约250℃之间的范围内的温度下实施退火。退火持续时间可以介于约1.5小时和约2.5小时之间。
在退火期间，彼此直接接触的铜和铝彼此互扩散(铜比铝具有更高的扩散速率)。在存在氧化物碎片67和167的位置，基本没有互扩散发生。作为扩散的结果，如图13中示意性示出的，形成了金属间化合物(IMC)82，并且因此，金属凸块66接合至金属焊盘172。IMC82包括铜和铝的合金以及金属凸块66和金属焊盘172中的可能的其它元素(如果存在的话)。在封装组件100和200的接合之后，底部填充物80可以分配至封装组件100和200之间的间隙。底部填充物80可以与位于金属凸块66的侧壁上的氧化物层67接触，并且可以与氧化物层167接触。
由于金属凸块66的底部转换成IMC 82，因此金属凸块66的剩余的未覆盖的部分称为金属凸块66’。类似地，在下文中，金属焊盘172的未覆盖的剩余的部分也称为金属焊盘172’。图14示出了金属凸块66’和金属焊盘172’的部分的放大视图。如图14中示意性示出的，在金属凸块66’和金属焊盘172’的界面处，存在氧化部分67、氧化部分167和IMC 82，这将(非氧化的和非合金的)金属凸块66’与(非氧化的和非合金的)金属焊盘172’分隔开。一些氧化部分67(或167)可以具有接触金属凸块66’的上部表面和接触金属焊盘172’的底部表面的上表面。一些其它氧化部分67(或167)可以完全地在IMC 82中(并且由IMC 82包围)。相应地，一些氧化部分67和167可以形成完全由IMC 82环绕(或包围)的岛，并且IMC 82的一些部分可以由氧化部分67和/或167环绕。此外，根据一些实施例，金属凸块66’可以延伸至金属焊盘172’内大于约0.1μm的一深度D1(即，氧化物层167的底部表面(未改变部分)和金属凸块66’的最低部分之间的垂直距离)。应该注意，最初的金属凸块66撞击至金属焊盘172’内一距离D1’D1’是氧化物层167的底部表面和IMC 82(假设转换成IMC 82的金属凸块66和金属焊盘172的部分具有相同的厚度)的中间高度之间的垂直距离。
根据一些示例性实施例，金属凸块66是铜凸块，并且金属焊盘172是铝焊盘。根据其它实施例，金属凸块66是铝凸块，并且金属焊盘172是铜焊盘。
图15至图17示出了根据一些实施例的一些应用。图15和图17中的封装组件100和200的接合结构和接合工艺可以与图1至图14中所示的基本相同，并且因此这些应用中的工艺细节和材料不在此处重复。图15示出了晶圆上芯片(CoW)结构，其中，芯片100接合至晶圆200。晶圆200可以是其中包括有源器件的器件晶圆或可以是无有源器件的插入式晶圆。贯通孔202穿透晶圆200的衬底(例如，半导体衬底)。
图16示出了集成扇出(InFO)结构，该集成扇出(InFO)结构包括穿透包封材料(诸如模塑料)206的贯通孔204。芯片100接合至芯片(或晶圆)200，其中，包封材料206也包封其中的芯片100。图17示出了与图16中所示的结构类似的结构，其中，有两个芯片100接合至相同的芯片200。
本发明的实施例具有一些优势特征。通过直接接合铝和铜，不再需要用于传统接合结构的焊料区域、镍层等。可以实施多个撞击工艺，并且因此不需要使用化学溶液去除氧化物层。因此节约了接合工艺的成本，并且增强了接合工艺的吞吐量。铜凸块可以直接形成为相应的晶圆/管芯中的顶金属层，并且因此简化了相应的晶圆的结构和形成工艺，并且减小了成本。
根据本发明的一些实施例，一种方法包括实施第一撞击工艺以使第一封装组件的金属凸块撞击第二封装组件的金属焊盘。金属凸块和金属焊盘的第一个包括铜。金属凸块和金属焊盘的第二个包括铝。该方法还包括实施第二撞击工艺以使金属凸块撞击金属焊盘。实施退火以将金属凸块接合在金属焊盘上。
根据本发明的一些实施例，一种方法包括将第一封装组件提高至位于第二封装组件上方并且与第二封装组件间隔开，并且实施第一撞击工艺以使第一封装组件撞击第二封装组件。该方法还包括，在第一撞击工艺之后，将第一封装组件提高至位于第二封装组件上方并且与第二封装组件间隔开，实施第二撞击工艺以使第一封装组件撞击第二封装组件，并且退火第一封装组件和第二封装组件以将第一封装组件接合至第二封装组件。
根据本发明的一些实施例，一种结构包括具有含铜凸块的第一封装组件和具有含铝焊盘的第二封装组件。含铜凸块接合至含铝焊盘。含铜凸块延伸至含铝焊盘。IMC将含铜凸块连接至含铝焊盘，并且IMC包括铜和铝。
根据本发明的一个实施例，提供了一种用于形成封装件的方法，包括：实施第一撞击工艺以使第一封装组件的金属凸块撞击第二封装组件的金属焊盘，其中，所述金属凸块和所述金属焊盘的第一个包括铜，并且所述金属凸块和所述金属焊盘的第二个包括铝；实施第二撞击工艺以使所述金属凸块撞击所述金属焊盘；以及实施退火以将所述金属凸块接合在所述金属焊盘上。
在上述方法中，还包括在所述第一撞击工艺之后且在所述第二撞击工艺之前的第三撞击工艺，其中，所述第三撞击工艺包括使所述金属凸块撞击所述金属焊盘。
在上述方法中，在所述第一撞击工艺之前，位于所述金属凸块的表面处的第一氧化物层和位于所述金属焊盘的表面处的第二氧化物层是连续的氧化物层，其中，在所述第一撞击工艺中，所述第一氧化物层撞击所述第二氧化物层。
在上述方法中，在所述第一撞击工艺和所述第二撞击工艺中，所述第一氧化物层和所述第二氧化物层均被打破成碎片。
在上述方法中，将所述第一封装组件从与所述第二封装组件间隔开的位置移动以冲击所述第二封装组件来实施所述第一撞击工艺。
在上述方法中，在所述第一撞击工艺和所述第二撞击工艺的每个之后，所述金属凸块延伸至所述金属焊盘内。
在上述方法中，在所述退火期间，所述金属凸块保持延伸至所述金属焊盘内。
在上述方法中，在所述第二撞击工艺之后，所述金属凸块保持与所述金属焊盘接触直至完成所述退火。
根据本发明的另一实施例，还提供了一种用于形成封装件的方法，包括：将第一封装组件提高至第二封装组件上方并且与所述第二封装组件间隔开；实施第一撞击工艺以使所述第一封装组件撞击所述第二封装组件；在所述第一撞击工艺之后，将所述第一封装组件提高至所述第二封装组件上方并且与所述第二封装组件间隔开；实施第二撞击工艺以使所述第一封装组件撞击所述第二封装组件；以及退火所述第一封装组件和所述第二封装组件以将所述第一封装组件接合至所述第二封装组件。
在上述方法中，所述第一封装组件和所述第二封装组件的第一个包括突出的金属凸块，以及所述第一封装组件和所述第二封装组件的第二个包括凹进的金属焊盘，并且其中，在所述第一撞击工艺和所述第二撞击工艺中，所述突出的金属凸块撞击所述凹进的金属焊盘。
在上述方法中，通过所述第一撞击工艺和所述第二撞击工艺将位于所述突出的金属凸块的表面上的第一氧化物层和位于所述凹进的金属焊盘的表面上的第二氧化物层打破成碎片，并且在所述第二撞击工艺之后，所述突出的金属凸块的非氧化表面与所述凹进的金属焊盘的非氧化表面物理接触。
在上述方法中，所述第二撞击工艺导致所述突出的金属凸块延伸至所述凹进的金属焊盘内，并且其中，在所述第二撞击工艺和所述退火之间的整个持续时间中，所述突出的金属凸块保持延伸至所述凹进的金属焊盘内。
在上述方法中，所述凹进的金属焊盘的边缘部分被钝化层覆盖，并且在所述第一撞击工艺中，所述突出的金属凸块延伸至所述钝化层中的开口内。
在上述方法中，在所述第一撞击工艺和所述第二撞击工艺中，所述第一封装组件以高于100μm/秒的速度冲击所述第二封装组件。
根据本发明的又一实施例，还提供了一种封装件结构，包括：第一封装组件，包括含铜凸块；第二封装组件，包括含铝焊盘，其中，所述含铜凸块接合至所述含铝焊盘，并且其中，所述含铜凸块延伸至所述含铝焊盘内；以及金属间化合物(IMC)，将所述含铜凸块连接至所述含铝焊盘，其中，所述金属间化合物包括铜和铝。
在上述结构中，还包括：多个离散的铝氧化物碎片，接触所述金属间化合物；以及多个离散的铜氧化物碎片，接触所述金属间化合物。
在上述结构中，所述多个离散的铝氧化物碎片和所述多个离散的铜氧化物碎片的一个被所述金属间化合物环绕。
在上述结构中，所述第二封装组件还包括覆盖所述含铝焊盘的边缘部分的钝化层，并且所述含铜凸块延伸至所述钝化层中的开口内。
在上述结构中，还包括位于所述第一封装组件和所述第二封装组件之间的底部填充物，其中，所述底部填充物环绕所述含铜凸块。
在上述结构中，所述含铜凸块延伸至所述含铝焊盘内大于0.1μm的深度。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种用于形成封装件的方法，包括：
实施第一撞击工艺以使第一封装组件的金属凸块撞击第二封装组件的金属焊盘，其中，所述金属凸块和所述金属焊盘的第一个包括铜，并且所述金属凸块和所述金属焊盘的第二个包括铝；
实施第二撞击工艺以使所述金属凸块撞击所述金属焊盘；以及
实施退火以将所述金属凸块接合在所述金属焊盘上。
2.根据权利要求1所述的方法，还包括在所述第一撞击工艺之后且在所述第二撞击工艺之前的第三撞击工艺，其中，所述第三撞击工艺包括使所述金属凸块撞击所述金属焊盘。
3.根据权利要求1所述的方法，其中，在所述第一撞击工艺之前，位于所述金属凸块的表面处的第一氧化物层和位于所述金属焊盘的表面处的第二氧化物层是连续的氧化物层，其中，在所述第一撞击工艺中，所述第一氧化物层撞击所述第二氧化物层。
4.根据权利要求3所述的方法，其中，在所述第一撞击工艺和所述第二撞击工艺中，所述第一氧化物层和所述第二氧化物层均被打破成碎片。
5.根据权利要求1所述的方法，其中，将所述第一封装组件从与所述第二封装组件间隔开的位置移动以冲击所述第二封装组件来实施所述第一撞击工艺。
6.根据权利要求1所述的方法，其中，在所述第一撞击工艺和所述第二撞击工艺的每个之后，所述金属凸块延伸至所述金属焊盘内。
7.根据权利要求1所述的方法，其中，在所述退火期间，所述金属凸块保持延伸至所述金属焊盘内。
8.根据权利要求1所述的方法，其中，在所述第二撞击工艺之后，所述金属凸块保持与所述金属焊盘接触直至完成所述退火。
9.一种用于形成封装件的方法，包括：
将第一封装组件提高至第二封装组件上方并且与所述第二封装组件间隔开；
实施第一撞击工艺以使所述第一封装组件撞击所述第二封装组件；
在所述第一撞击工艺之后，将所述第一封装组件提高至所述第二封装组件上方并且与所述第二封装组件间隔开；
实施第二撞击工艺以使所述第一封装组件撞击所述第二封装组件；以及
退火所述第一封装组件和所述第二封装组件以将所述第一封装组件接合至所述第二封装组件。
10.一种封装件结构，包括：
第一封装组件，包括含铜凸块；
第二封装组件，包括含铝焊盘，其中，所述含铜凸块接合至所述含铝焊盘，并且其中，所述含铜凸块延伸至所述含铝焊盘内；以及
金属间化合物(IMC)，将所述含铜凸块连接至所述含铝焊盘，其中，所述金属间化合物包括铜和铝。
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