TWI418000B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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Publication number
TWI418000B
TWI418000B TW099141866A TW99141866A TWI418000B TW I418000 B TWI418000 B TW I418000B TW 099141866 A TW099141866 A TW 099141866A TW 99141866 A TW99141866 A TW 99141866A TW I418000 B TWI418000 B TW I418000B
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Taiwan
Prior art keywords
substrate
conductive material
forming
die
integrated circuit
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TW099141866A
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English (en)
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TW201212185A (en
Inventor
Yi Jen Lai
You Hua Chou
Hon Lin Huang
Huai Tei Yang
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Taiwan Semiconductor Mfg
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Publication of TW201212185A publication Critical patent/TW201212185A/zh
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Publication of TWI418000B publication Critical patent/TWI418000B/zh

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Description

半導體結構及其形成方法
本發明係關於半導體元件，且更特別關於具有晶粒邊緣接點的半導體元件。
由於不同電子構件如電晶體、二極體、電阻、或電容等等之積體密度持續改良，半導體積體電路產業已快速成長一段時日。改良上述積體密度的主要方法為持續縮小結構尺寸，讓更多的構件可整合至固定面積中。
過去數十年中半導體封裝的轉變，數次衝擊了整個半導體業。對大部份的IC元件之高通量組裝來說，導入表面貼裝技術(SMT)與球柵陣列(BGA)封裝為重要的里程碑，可減少印刷電路板上的墊層間距。習知的封裝IC其結構中，基本上採用細金線作為晶粒上金屬墊之間的內連線，或以細金線連接被固化橡膠封裝材分隔的電極。另一方面，部份的晶片等級封裝(CSP)或BGA封裝需採用焊料凸塊/焊球，以提供晶粒上接點與基板上接點兩者之間的電性連接。上述基板可為封裝基板、印刷電路板、其他晶粒/晶圓、或類似物。其他CSP或BGA封裝中的焊球或焊料凸塊係位於導電柱上，取決於結構積體度所用的焊料接點。一般會將底填材料置於IC與其下基板(如封裝基板)之間，以增加結構的機械強度並保護IC不受環境污染物影響。
在這些實施例中，不同基板之間的電性接點即焊料凸塊。採用不同基板往往意謂著這些基板各自具有不同的熱膨脹係數(CTE)。當元件升溫或降溫時，不同基板可能會因CTE差異而以不同的速率膨脹或縮小。這會在接點區造成額外應力，進而使接點碎裂及/或產生其他問題如分層。
本發明一實施施提供一種半導體結構，包括積體電路基板，具有接觸墊形成其上；保護層形成於積體電路基板上，保護層至少露出部份的接觸墊，且保護層具有溝槽自接觸墊延伸至積體電路基板之邊緣；以及導電材料填入保護層之溝槽以形成晶粒邊緣接點。
本發明另一實施例提供一種半導體結構之形成方法，包括提供晶圓，具有複數個接點形成其上；形成保護層於晶圓上；圖案化保護層以露出接點，並形成多個溝槽自個別的接點延伸至切割線；形成導電材料於溝槽中；以及延著切割線將晶圓分隔為複數個晶粒，其中溝槽中的至少部份導電材料沿著切割線邊緣露出。
本發明又一實施例提供一種半導體結構之形成方法，包括提供一或多個積體電路晶粒，其中每一積體電路晶粒具有複數個晶粒邊緣接點；提供內連線結構，其中內連線結構包括一或多個內連線基板，且至少一內連線基板具有複數個電性接點形成其上；以及將一或多個積體電路晶粒置於內連線結構中，使一或多個積體電路晶粒之晶粒邊緣接點電性耦合至至少一內連線基板中個別的電性接點，其中內連線基板垂直積體電路晶粒之主要表面。
下列說明中的實施例將揭露如何形成並使用半導體結構。然而必需理解的是，這些實施例提供多種可行的發明概念，並可應用於多種特定內容中。特定實施例僅用以說明形成及使用實施例的特定方式，並非用以侷限本發明的範圍。
第1圖係本發明一實施例中，晶粒101的部份透視圖。晶粒101含有基板102，其具有保護層104形成其上。保護層104含有圖形106如後保護層形成其上。後續將詳述圖形106自較下層的接點(未圖示於第1圖)延伸至晶粒邊緣。圖形106自晶粒邊緣露出，以形成晶粒邊緣接點108。
第2A-5B圖係本發明一實施例中，形成第1圖所示之半導體元件的製程在不同階段之剖視圖。A系列圖示如第2A-5A圖係沿著第1圖之A-A線段，而B系列圖示如第2B-5B圖係沿著第1圖之B-B線段。必需注意的是，B系列圖示中含有兩個相鄰的晶粒以更明確的說明實施例，其中所含的虛線201指的是兩個相鄰晶粒之間的切割線。
如第2A及2B圖所示的一實施例中，部份的基板202可視情況具有電路204形成其上。基板202可為基體矽、掺雜或未掺雜的基板、或絕緣層上矽(SOI)基板之主動層。一般的SOI基板含有半導體材料層如矽形成於絕緣層上。上述絕緣層可為氧化埋層(BOX)或氧化矽層。絕緣層可形成於基板(如一般矽基板或玻璃基板)上。此外，基板202亦可為其他基板如多層結構或組成漸變式基板。
基板202上視情況形成的電路204可為任何適於特定應用的電路。在一實施例中，電路204含有電子元件形成於基板202上，以及一或多層介電層形成於電子元件上。在介電層之間可形成金屬層以傳遞電子元件之間的電子訊號。電子元件可形成於一或多層的介電層上或介電層中。
舉例來說，電路204可具有多種n型金氧半(NMOS)及/或p型金氧半(PMOS)元件如電晶體、電容、電阻、二極體、光二極體、熔絲、或類似物，彼此以內連線相接以形成具有一或多種功能之結構如記憶結構、處理結構、感測器、放大器、功率分佈器、輸入/輸出電路、或類似物。本技藝人士應理解上述實例僅用以舉例及進一步說明本發明，並非用以侷限本發明。本發明亦可採用其他電路。
接著可形成層間介電層(ILD)208如低介電常數材料如磷掺雜矽酸鹽玻璃(PSG)、硼磷掺雜矽酸鹽玻璃(BPSG)、氟化矽酸鹽玻璃(FSG)、碳氧化矽、旋塗玻璃、旋塗高分子、矽碳材料、上述之化合物、上述之複合物、上述之組合、或類似物。層間介電層208之形成方法可為本技藝已知的方法如旋轉塗佈法、化學氣相沉積法(CVD)、或電漿增強式CVD(PECVD)。必需注意的是，層間介電層208可為多層結構。
接著形成接點210穿過層間介電層208，以提供電性連接至電路204。接點210之形成方法可為微影製程如沉積並圖案化光阻材料於層間介電層208上，層間介電層208露出的部份將用以形成接點210。接著進行蝕刻製程如非等向乾蝕刻以形成開口於層間介電層208中。可將擴散阻障層及/或黏著層(未圖示)襯墊於開口中，再將導電材料填入開口。在一實施例中，擴散阻障層可為一或多層的氮化鉭、鉭、氮化鈦、鈦、鈷鎢合金、或類似物，而導電材料可為銅、鎢、鋁、銀、或上述之組合、或類似物。至此形成第2A圖所示之接點210。
接著形成一或多層的金屬間介電層(212)212與相關的金屬層(未圖示)於層間介電層208上。一般來說，一或多層的金屬間介電層212與相關的金屬層可讓電路204彼此連線，並提供外部電性連接。金屬間介電層212之組成可為低介電常數之介電材料如PECVD或高密度電漿CVD(HDPCVD)形成的FSG或類似物，並可進一步含有層間蝕刻停止層。接點214係位於最上層的金屬間介電層以提供外部電性連接。
必需注意的是，在相鄰的介電層如層間介電層208與金屬間介電層212之間，可具有一或多層的蝕刻停止層(未圖示)。一般來說，蝕刻停止層在形成通孔及/或接點的蝕刻製程中作為停止機制。蝕刻停止層形成於介電材料上，與相鄰的其他層(比如下方的半導體基板202、上方的層間介電層208、或上方的金屬間介電層212)之間具有不同的蝕刻選擇性。在一實施例中，蝕刻停止層可為氮化矽、碳氮化矽、碳氧化矽、氮化碳、上述之組合、或類似物。蝕刻停止層之沉積方法可為CVD或PECVD。
如第3A及3B圖所示的一實施例中，形成保護層316於接點214及最上層的金屬間介電層上212，以保護下方的層狀結構不受多種的環境污染物影響。保護層316可為一或多層的介電材料如氮化矽、電漿增強式氧化物(PEOX)、電漿增強式氮化矽(PE-SiN)、電漿增強式未掺雜的矽酸鹽玻璃(PE-USG)、或類似物。接著圖案化保護層316以提供開口於接點214上，而圖案化方法可為雙鑲嵌製程。如第3B圖所示，進一步圖案化保護層316以形成自接點214延伸至切割線201的溝槽317。在一實施例中，保護層316之形成方法可為CVD或PVD製程，其厚度可介於約1,000至約30,000之間。溝槽317之寬度可介於5μm至10μm之間，其深度可介於800至30,000之間。
接著將導電材料填入保護層316中的溝槽317，以形成圖形318作為後保護內連線層的一部份。圖形318可為任何合適的導電材料如銅、鎳、鉑、鋁、銀、上述之組合、類似物。圖形318之形成方法可為任何合適技術如PVD、CVD、電化學沉積法(ECD)、分子束磊晶法(MBE)、原子層沉積法(ALD)、電鍍法、或類似方法。必需注意的是某些實施例中，特別是順應性沉積層狀材料於晶圓的整個表面上之製程如PVD或CVD，可能需要進行蝕刻或平坦化製程(比如CMP)將多餘的導電材料自保護層316表面移除。
如第4A及4B圖所示的一實施例中，沿著切割線201形成凹陷420。在切割線201的位置，凹陷420截斷並露出部份的圖形318。圖形318露出部份的厚度介於約1,200至約35,000之間，可作為後續詳述的晶粒邊緣接點。在一實施例中，凹陷420的深度至少相等於圖形318之厚度。凹陷420的形成方法可為雷射切割。雷射切割可形成凹陷於保護層316如同形成凹陷於圖形材料(如銅)中，這將使圖形318具有露出的邊緣並形成晶粒邊緣接點。
如第5A及5B圖所示，在切割基板202後，形成拋光層522於圖形318的表面上。在一實施例中，拋光層522可為直接位於圖形318上並與之接觸的鎳層。此外可視情況形成額外層，使拋光層522為化學鍍鎳浸金層(ENIG)、鎳化學鍍鈀與浸金層(ENEPIG)、或鎳鈀層。拋光層522之形成方法可為ECP、無電電鍍法、或類似方法。
在一實施例中，拋光層522自第5A及5B圖所示之晶粒邊緣表面凸出，這將使電性接點易於形成。在一實施例中，拋光層522自晶粒邊緣凸出的範圍介於約100至約5,000之間。必需理解的是某些實施例需要較凸出的拋光層，此時需沉積額外的導電材料於圖形318上，且導電材料與圖形318之組成可相同或不同。舉例來說，當圖形318之組成為銅，可採用ECP製程等方法形成額外的銅材於圖形318上。
圖形318/拋光層522組成晶粒邊緣接點524。可視情況薄化基板背面並形成蓋層於晶粒表面上。蓋層亦可作為散熱器。
第6圖係一實施例中，晶粒601之部份透視圖。第6圖所示之實施例與第1圖所示之實施例類似，兩者間類似的單元將沿用相同標號，除了晶粒601之晶粒邊緣接點602延伸穿過整個晶粒601。後續內容將進一步詳述穿透基板通孔的作法，以及經由穿透基板通孔切割晶粒的作法。
第7A-9B圖係本發明一實施例中，形成第6圖所示之半導體元件的製程在不同階段之剖視圖。A系列圖示如第7A-9A圖係沿著第6圖之A-A線段，而B系列圖示如第7B-9B圖係沿著第6圖之B-B線段。必需注意的是，B系列圖示中含有兩個相鄰的晶粒以更明確的說明實施例，其中所含的虛線201指的是兩個相鄰晶粒之間的切割線。第2A-5B圖及第7A-9B圖中類似的元件將沿用相同標號，且不贅述類似元件的形成方法與材質。
首先如第7A及7B圖所示，部份的基板202具有穿透基板通孔730形成其中。穿透基板通孔730可由任何合適技術形成，且由任何合適材質組成。舉例來說，穿透基板通孔730之形成方法可為蝕刻或鑽孔，形成穿透部份基板202之通孔如第7A-7B圖所示。接著將導電材料如鋁、銅、其他金屬、合金、掺雜的多晶矽、上述之組合、或類似物填入通孔中。在後述內容中，可沿著穿透基板通孔730進行切割製程，以形成晶粒邊緣接點。在一實施例中，穿透基板通孔730之直徑介於約3,000至約40,000之間。
在其他技術中，可蝕刻部份基板形成通孔，再沉積介電層於通孔中以形成穿透基板通孔730。在此實施例中，先薄化基板背面再移除通孔中的介電層，之後再沉積導電材料於通孔中。除了上述方法外，亦可採用其他方法。此外，穿透基板通孔730可含有襯墊層如阻障層，其材質較佳為介電材料如氧化物、氮化物、或類似物。
如第8A及8B圖所示，形成保護層316於基板202上。第8A及8B圖所示之保護層316的組成與形成方法類似於前述第3A及3B圖所示之保護層316，差別在此實施例之保護層316被進一步圖案化以露出穿透基板通孔730。形成於保護層316中的溝槽可填入導電材料以形成圖形318。
如第9A及9B圖所示，在切割基板202後進行薄化晶圓製程，直到露出穿透基板通孔730。在切割基板後，可形成第5圖所示之拋光層522。在一實施例中，拋光層522自晶粒邊緣的表面凸出，如第9A及9B圖所示。如此一來，可形成隆起的電性接點。如第9A及9B圖所示，穿透基板通孔730/圖形318/拋光層522所組成的晶粒邊緣接點950延伸至晶粒的所有厚度。可視情況形成蓋層於晶粒表面上，且蓋層可作為散熱器。在另一實施例中，穿透基板通孔730(與之後形成的晶粒邊緣接點950)並未完全穿過晶粒，即使在薄化基板202後也只有延伸穿過部份的基板202。
第10圖係本發明一實施例中，可用於封裝多個晶粒之多重晶粒封裝1002的透視圖。多重晶粒封裝1002含有外殼1004及內連線結構1006。一般來說，內連線結構1006具有一或多個牆狀物或基板1007，晶粒如第1及6圖所示之晶粒101及60可分別形成其上。如第10圖所示之實施例中，內連線結構1006具有四面牆狀物或基板1007。沿著內連線結構1006之內表面，該些基板中至少一者具有晶粒支撐物1012以支撐插置於內連線結構中的晶粒。末端基板1007(如虛線框)有利於說明內連線結構1006之內部結構。每面牆狀物可獨立形成於單一晶圓，切割後再以膠體或其他接著劑接合組裝成圖示結構。在第10圖所示之實施例中，內連線結構具有三個狹縫10091 、10092 、與10093 。每一狹縫10091 、10092、與10093 可容納同型晶粒(比如相同記憶體)，或容納不同功能的晶粒(比如一者為處理器晶粒，而另一者為記憶體晶粒以形成系統級封裝(SIP))。圖中狹縫的數目只有三個，但其他實施例可具有更多或更少的狹縫。在第13圖中，三個晶粒1301係插置於內連線結構1006中。
延著內連線結構1006之內表面形成的接點1008，可提供電性連接至晶粒邊緣接點如第5圖及第9圖所示之晶粒邊緣接點524與950。接點1008係電性耦合至一或多個沿著內連線結構1006之底部邊緣形成的外部接點1010。外部接點可具有隆起的接點如導電柱、焊球/焊料凸塊、上述之組合、或類似物，可將內連線結構1006電性耦合至印刷電路板、封裝基板、高密度內連線結構、或類似物。
外殼1004之牆狀物或基板1016係沿著內連線結構1006之外表面形成，可保護內連線結構1006。外殼1004亦可作為散熱器，可幫助複數個晶粒操作時產生的熱散逸至環境中。基板1016可分別形成，再以膠體或其他接著劑組裝成外殼。由外殼1004之內表面凸出的微懸吊柱1018可作為內連線結構1006之熱擴散緩衝，亦可作為內連線結構1006與外殼1004之間的熱傳輸機構。
第11圖係用以形成多晶粒封裝1002之內連線結構的基板1007之剖視圖，或用以容納一或多個積體電路晶粒(比如第1-9B圖所示的晶粒)之封裝基板的剖視圖。在一實施例中，基板1007中的基材1104具有金屬層1106形成其上。基材1104可為基體矽、掺雜或未掺雜的基材、或絕緣層上矽(SOI)基板之主動層。在一實施例中，基材1104可為印刷電路板、壓合基材、或類似物。在一實施例中，基材之組成如矽的熱膨脹係數(CTE)，最好與置入多重晶粒封裝的積體電路晶粒之基板類似。基材1104可具有一或多層的介電層。
金屬層1106可為任何合適導電材料如銅、鎳、鉑、鋁、銀、上述之組合、或類似物。金屬層1106之形成方法可為任何合適製程如PVD、CVD、ECD、MBE、ALD、電鍍法、或類似方法。
接著形成並圖案化保護層1108於基材1104之表面上，使對應晶粒邊緣接點之接點區域的部份金屬層1106露出。保護層1108可為一或多層的介電材料如氮化矽、PEOX、PE-SiN、PE-USG、高分子、或類似物。
接著根據第10圖之接點1008，形成隆起的接點1110於保護層1108內的開口中。隆起的接點1110可為一或多層的適當導電材料如銅、鎳、鉑、鋁、銀、上述之組合、會類似物。隆起的接點1110之形成方法可為任何合適技術如PVD、CVD、ECD、MBE、ALD、電鍍、或類似方法。接著形成拋光層1112如鎳層、ENIG層、ENEPIG層、或類似物。拋光層1112亦可作為延著基板邊緣形成之隆起的接點，如第11圖所示。在一實施例中，隆起的接點1110之高度介於約2,000至約20,000之間。
根據第10圖所示之晶粒支撐物1012，形成於隆起的接點1110其行列之間的晶粒支撐物1114可作為對準標記，亦可讓晶粒插置於內連線結構1006中。晶粒支撐物1114之組成可為介電材料如氧化矽、玻璃、或石英，其形成方法可為膠體黏結搭配印刷法，亦可為粉末形成法。晶粒支撐物1114亦可為導電材料如金屬球或金屬立方結構，其形成方法可為膠體黏結搭配印刷法，亦可為粉末冶金法。在一實施例中，晶粒支撐物1114之高度介於約300μm至5,000μm之間，其寬度介於約300μm至約5,000μm之間。
必需注意的是第11圖中，單一金屬層連接至每一隆起的接點1110的態樣僅用以舉例。在一實施例中，金屬層的設計可讓隆起的接點佈線至不同的外部接點。
第12圖係用以形成第10圖之外殼1004的基板1016之剖視圖。基板1016之基材1204含有微懸吊柱1210凸出其上。基材1204可為任何合適基材如矽基材、金屬基材、陶瓷基材、或類似物。在一實施例中，基材1204之厚度為約1mm。微懸吊柱1210之組成可為矽膠橡膠、微金屬彈簧、或類似物。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
101、601、1301．．．晶粒
102、202、1007、1016．．．基板
104、316．．．保護層
106、318．．．圖形
108、524、602、950．．．晶粒邊緣接點
201‧‧‧切割線
204‧‧‧電路
208‧‧‧層間介電層
210、214、1008‧‧‧接點
212‧‧‧金屬間介電層
317‧‧‧溝槽
420‧‧‧凹陷
522、1112‧‧‧拋光層
730‧‧‧穿透基板通孔
1002‧‧‧多重晶粒封裝
1004‧‧‧外殼
1006‧‧‧內連線結構
10091、10092、10093‧‧‧狹縫
1010‧‧‧外部接點
1012、1114‧‧‧晶粒支撐物
1018、1204‧‧‧微懸吊柱
1104、1204‧‧‧基材
1106‧‧‧金屬層
1110‧‧‧隆起的接點
第1圖係本發明一實施例中，具有晶粒邊緣接點之積體電路晶粒的透視圖；
第2A、2B、3A、3B、4A、4B、5A及5B圖係本發明一實施例中，形成半導體元件之製程的不同階段剖視圖；
第6圖係本發明另一實施例中，具有晶粒邊緣接點之積體電路晶粒的透視圖；
第7A、7B、8A、8B、9A及9B係本發明一實施例中，形成半導體元件之製程的不同階段剖視圖；
第10圖係本發明又一實施例中，具有晶粒邊緣接點之積體電路晶粒所用之多重晶粒封裝的透視圖；
第11圖係本發明一實施例中，多重晶粒封裝所用之內連線結構牆狀物；
第12圖係本發明一實施例中，多重晶粒封裝之外殼的牆狀物；以及
第13圖係本發明一實施例中，複數個積體電路晶粒連接至多重晶粒封裝的透視圖。
202．．．基板
208．．．層間介電層
214．．．接點
212．．．金屬間介電層
316．．．保護層
317．．．溝槽
522．．．拋光層
730．．．穿透基板通孔
318．．．圖形
950．．．晶粒邊緣接點

Claims (10)

  1. 一種半導體結構，包括：一積體電路基板，具有一接觸墊形成其上；一保護層形成於該積體電路基板上，該保護層至少露出部份的該接觸墊，且該保護層具有一溝槽自該接觸墊延伸至該積體電路基板之邊緣；以及一第一導電材料填入該保護層之該溝槽以形成一晶粒邊緣接點；以及一第二導電材料形成於該第一導電材料上，其中該第二導電材料延伸超過該保護層。
  2. 如申請專利範圍第1項所述之半導體結構，更包括一穿透基板通孔於該基板之邊緣上，且該晶粒邊緣接點包括該穿透基板通孔。
  3. 如申請專利範圍第1項所述之半導體結構，更包括一內連線結構，該內連線結構具有複數個內連線基板與該積體電路基板垂直，至少一內連線基板具有另一接觸墊，且該另一接觸墊電性耦合至該晶粒邊緣接點。
  4. 如申請專利範圍第3項所述之半導體結構，更包括一外殼，該外殼具有複數個外殼基板，且該些外殼基板與該積體電路基板分別位於該內連線結構相反之兩側。
  5. 如申請專利範圍第4項所述之半導體結構，更包括一微懸吊柱夾設於該內連線結構與該外殼之間。
  6. 一種半導體結構之形成方法，包括：提供一晶圓，具有複數個接點形成其上； 形成一保護層於該晶圓上；圖案化該保護層以露出該些接點，並形成多個溝槽自個別的該些接點延伸至一切割線；形成一第一導電材料於該溝槽中以形成一晶粒邊緣接點；形成第二導電材料於該第一導電材料上，其中該第二導電材料延伸超過該保護層；以及延著該切割線將該晶圓分隔為複數個晶粒，其中該溝槽中的至少部份該導電材料沿著該切割線邊緣露出。
  7. 如申請專利範圍第6項所述之半導體結構之形成方法，更包括在該晶圓中沿著該切割線形成複數個穿透基板通孔於該溝槽下，使該溝槽中的導電材料電性耦合至個別的該些穿透基板通孔。
  8. 一種半導體結構之形成方法，包括：提供一或多個積體電路晶粒，其中每一該積體電路晶粒具有複數個晶粒邊緣接點，其中該些晶粒邊緣接點之形成方法係將第一導電材料填入一保護層的多個溝槽中；形成一第二導電材料於該第一導電材料上，其中該第二導電材料延伸超過該保護層；提供一內連線結構，其中該內連線結構包括一或多個內連線基板，且至少一該內連線基板具有複數個電性接點形成其上；以及將一或多個該積體電路晶粒置於該內連線結構中，使一或多個該積體電路晶粒之該些晶粒邊緣接點電性耦 合至至少一該內連線基板中個別的該些電性接點，其中該內連線基板垂直該積體電路晶粒之主要表面。
  9. 如申請專利範圍第8項所述之半導體結構之形成方法，更包括一外殼位於該內連線結構之一側，且該外殼與該積體電路晶粒分別位於該內連線結構相反之兩側。
  10. 如申請專利範圍第9項所述之半導體結構之形成方法，更包括一微懸吊柱夾設於該外殼與該內連線結構之間。
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