CN102386157B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
CN102386157B
CN102386157B CN201010602782.8A CN201010602782A CN102386157B CN 102386157 B CN102386157 B CN 102386157B CN 201010602782 A CN201010602782 A CN 201010602782A CN 102386157 B CN102386157 B CN 102386157B
Authority
CN
China
Prior art keywords
substrate
contact
internal connection
integrated circuit
nude film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010602782.8A
Other languages
English (en)
Other versions
CN102386157A (zh
Inventor
赖怡仁
周友华
黄宏麟
杨怀德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102386157A publication Critical patent/CN102386157A/zh
Application granted granted Critical
Publication of CN102386157B publication Critical patent/CN102386157B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03823—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05006—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种半导体结构及其形成方法，本发明提供的一种采用裸片边缘接点的半导体元件。集成电路裸片具有沟槽的后保护层，而沟槽填有导电材料且自接点延伸至裸片边缘以形成裸片边缘接点。沿着裸片边缘，可视情况形成穿透基板通孔。这将使沟槽中的导电材料电性耦合至穿透基板通孔，以形成较大的裸片边缘接点。上述集成电路裸片可置于多重裸片封装中，且多重裸片封装的墙状物的主要表面垂直于集成电路裸片的主要表面。裸片边缘接点可电性连接至多重裸片封装的墙状物上的接点。多重裸片封装可含有边缘接点以连接至另一基板如印刷电路板、封装基板、高密度内连线、或类似物。本发明提供3D IC封装更方便的测试接点与对抗热应力造成的集成电路龟裂。

Description

半导体结构及其形成方法
技术领域
本发明涉及一种半导体元件，且特别是涉及一种具有裸片边缘接点的半导体元件。
背景技术
由于不同电子构件如晶体管、二极管、电阻、或电容等等的集成密度持续改良，半导体集成电路产业已快速成长一段时日。改良上述集成密度的主要方法为持续缩小结构尺寸，让更多的构件可整合至固定面积中。
过去数十年中半导体封装的转变，数次冲击了整个半导体业。对大部分的IC元件的高通量组装来说，导入表面贴装技术(SMT)与球栅阵列(BGA)封装为重要的里程碑，可减少印刷电路板上的垫层间距。现有的封装IC其结构中，基本上采用细金线作为裸片上金属焊盘之间的内连线，或以细金线连接被固化橡胶封装材分隔的电极。另一方面，部分的芯片等级封装(CSP)或BGA封装需采用焊料凸块/焊球，以提供裸片上接点与基板上接点两者之间的电性连接。上述基板可为封装基板、印刷电路板、其他裸片/晶片、或类似物。其他CSP或BGA封装中的焊球或焊料凸块位于导电柱上，取决于结构集成度所用的焊料接点。一般会将底填材料置于IC与其下基板(如封装基板)之间，以增加结构的机械强度并保护IC不受环境污染物影响。
在这些实施例中，不同基板之间的电性接点即焊料凸块。采用不同基板往往意味着这些基板各自具有不同的热膨胀系数(CTE)。当元件升温或降温时，不同基板可能会因CTE差异而以不同的速率膨胀或缩小。这会在接点区造成额外应力，进而使接点碎裂及/或产生其他问题如分层。
发明内容
为克服现有技术的缺陷，本发明一实施施提供一种半导体结构，包括集成电路基板，具有接触焊盘形成其上；保护层形成于集成电路基板上，保护层至少露出部分的接触焊盘，且保护层具有沟槽自接触焊盘延伸至集成电路基板的边缘；以及导电材料填入保护层的沟槽以形成裸片边缘接点。其优点在于提供3D IC封装更方便的测试接点与对抗热应力造成的集成电路龟裂。并且边缘接点可避免TSV(Through Substrate Via)穿透集成电路对元件集成度的破坏与对集成电路元件可能的金属污染。
本发明另一实施例提供一种半导体结构的形成方法，包括提供晶片，具有多个接点形成其上；形成保护层于晶片上；图案化保护层以露出接点，并形成多个沟槽自个别的接点延伸至切割线；形成导电材料于沟槽中；以及延着切割线将晶片分隔为多个裸片，其中沟槽中的至少部分导电材料沿着切割线边缘露出。
本发明又一实施例提供一种半导体结构的形成方法，包括提供一或多个集成电路裸片，其中每一集成电路裸片具有多个裸片边缘接点；提供内连线结构，其中内连线结构包括一或多个内连线基板，且至少一内连线基板具有多个电性接点形成其上；以及将一或多个集成电路裸片置于内连线结构中，使一或多个集成电路裸片的裸片边缘接点电性耦合至至少一内连线基板中个别的电性接点，其中内连线基板垂直集成电路裸片的主要表面。结合前述裸片边缘接点的技术，通过此立体的SOC封装结构，可降低集成电路散热不良的风险。通过可抽换式的概念与保留扩充插槽的架构，大大提升高性能SOC维修与扩充的条件，降低维护与扩充成本。提供3D IC封装的另一种选择。
附图说明
图1是本发明一实施例中，具有裸片边缘接点的集成电路裸片的透视图；
图2A-图5B是本发明一实施例中，形成半导体元件的工艺的不同阶段剖视图；
图6是本发明另一实施例中，具有裸片边缘接点的集成电路裸片的透视图；
图7A-图9B是本发明一实施例中，形成半导体元件的工艺的不同阶段剖视图；
图10是本发明又一实施例中，具有裸片边缘接点的集成电路裸片所用的多重裸片封装的透视图；
图11是本发明一实施例中，多重裸片封装所用的内连线结构墙状物；
图12是本发明一实施例中，多重裸片封装的外壳的墙状物；以及
图13是本发明一实施例中，多个集成电路裸片连接至多重裸片封装的透视图。
【主要附图标记说明】
101、601、1301～裸片；102、202、1007、1016～基板；104、316～保护层；106、318～图形；108、524、602、950～裸片边缘接点；201～切割线；204～电路；208～层间介电层；210、214、1008～接点；212～金属间介电层；317～沟槽；420～凹陷；522、1112～抛光层；730～穿透基板通孔；1002～多重裸片封装；1004～外壳；1006～内连线结构；10091、10092、10093～狭缝；1010～外部接点；1012、1114～裸片支撑物；1018、1204～微悬吊柱；1104、1204～基材；1106～金属层；1110～隆起的接点。
具体实施方式
下列说明中的实施例将公开如何形成并使用半导体结构。然而必需理解的是，这些实施例提供多种可行的发明概念，并可应用于多种特定内容中。特定实施例仅用以说明形成及使用实施例的特定方式，并非用以局限本发明的范围。
裸片边缘接点的技术其优点在于提供3D IC封装更方便的测试接点与对抗热应力造成的集成电路龟裂。并且边缘接点可避免TSV(Through SubstrateVia)穿透集成电路对元件集成度的破坏与对集成电路元件可能的金属污染。
图1是本发明一实施例中，裸片101的部分透视图。裸片101含有基板102，其具有保护层104形成其上。保护层104含有图形106如后保护层形成其上。后续将详述图形106自较下层的接点(未图示于图1)延伸至裸片边缘。图形106自裸片边缘露出，以形成裸片边缘接点108。
图2A-图5B是本发明一实施例中，形成图1所示的半导体元件的工艺在不同阶段的剖视图。A系列图示如图2A-图5A是沿着图1的A-A线段，而B系列图示如图2B-图5B是沿着图1的B-B线段。必需注意的是，B系列图示中含有两个相邻的裸片以更明确的说明实施例，其中所含的虚线201指的是两个相邻裸片之间的切割线。
如图2A及图2B所示的一实施例中，部分的基板202可视情况具有电路204形成其上。基板202可为基体硅、掺杂或未掺杂的基板、或绝缘层上硅(SOI)基板的有源层。一般的SOI基板含有半导体材料层如硅形成于绝缘层上。上述绝缘层可为氧化埋层(BOX)或氧化硅层。绝缘层可形成于基板(如一般硅基板或玻璃基板)上。此外，基板202也可为其他基板如多层结构或组成渐变式基板。
基板202上视情况形成的电路204可为任何适于特定应用的电路。在一实施例中，电路204含有电子元件形成于基板202上，以及一或多层介电层形成于电子元件上。在介电层之间可形成金属层以传递电子元件之间的电子信号。电子元件可形成于一或多层的介电层上或介电层中。
举例来说，电路204可具有多种n型金属氧化物半导体(NMOS)及/或p型金属氧化物半导体(PMOS)元件如晶体管、电容、电阻、二极管、光二极管、熔丝、或类似物，彼此以内连线相接以形成具有一或多种功能的结构如存储结构、处理结构、传感器、放大器、功率分布器、输入/输出电路、或类似物。本领域普通技术人员应理解上述实例仅用以举例及进一步说明本发明，并非用以局限本发明。本发明也可采用其他电路。
接着可形成层间介电层(ILD)208如低介电常数材料如磷掺杂硅酸盐玻璃(PSG)、硼磷掺杂硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、碳氧化硅、旋涂玻璃、旋涂高分子、硅碳材料、上述的化合物、上述的复合物、上述的组合、或类似物。层间介电层208的形成方法可为本领域已知的方法如旋转涂布法、化学气相沉积法(CVD)、或等离子体增强式CVD(PECVD)。必需注意的是，层间介电层208可为多层结构。
接着形成接点210穿过层间介电层208，以提供电性连接至电路204。接点210的形成方法可为光刻工艺如沉积并图案化光致抗蚀剂材料于层间介电层208上，层间介电层208露出的部分将用以形成接点210。接着进行蚀刻工艺如非等向干蚀刻以形成开口于层间介电层208中。可将扩散阻挡层及/或粘着层(未图示)衬垫于开口中，再将导电材料填入开口。在一实施例中，扩散阻挡层可为一或多层的氮化钽、钽、氮化钛、钛、钴钨合金、或类似物，而导电材料可为铜、钨、铝、银、或上述的组合、或类似物。至此形成图2A所示的接点210。
接着形成一或多层的金属间介电层(IMD)212与相关的金属层(未图示)于层间介电层208上。一般来说，一或多层的金属间介电层212与相关的金属层可让电路204彼此连线，并提供外部电性连接。金属间介电层212的组成可为低介电常数的介电材料如PECVD或高密度等离子体CVD(HDPCVD)形成的FSG或类似物，并可进一步含有层间蚀刻停止层。接点214位于最上层的金属间介电层以提供外部电性连接。
必需注意的是，在相邻的介电层如层间介电层208与金属间介电层212之间，可具有一或多层的蚀刻停止层(未图示)。一般来说，蚀刻停止层在形成通孔及/或接点的蚀刻工艺中作为停止机制。蚀刻停止层形成于介电材料上，与相邻的其他层(比如下方的半导体基板202、上方的层间介电层208、或上方的金属间介电层212)之间具有不同的蚀刻选择性。在一实施例中，蚀刻停止层可为氮化硅、碳氮化硅、碳氧化硅、氮化碳、上述的组合、或类似物。蚀刻停止层的沉积方法可为CVD或PECVD。
如图3A及图3B所示的一实施例中，形成保护层316于接点214及最上层的金属间介电层212上，以保护下方的层状结构不受多种的环境污染物影响。保护层316可为一或多层的介电材料如氮化硅、等离子体增强式氧化物(PEOX)、等离子体增强式氮化硅(PE-SiN)、等离子体增强式未掺杂的硅酸盐玻璃(PE-USG)、或类似物。接着图案化保护层316以提供开口于接点214上，而图案化方法可为双镶嵌工艺。如图3B所示，进一步图案化保护层316以形成自接点214延伸至切割线201的沟槽317。在一实施例中，保护层316的形成方法可为CVD或PVD工艺，其厚度可介于约
Figure BSA00000397555600051
至约
Figure BSA00000397555600052
之间。沟槽317的宽度可介于5μm至10μm之间，其深度可介于
Figure BSA00000397555600053
至
Figure BSA00000397555600054
之间。
接着将导电材料填入保护层316中的沟槽317，以形成图形318作为后保护内连线层的一部分。图形318可为任何合适的导电材料如铜、镍、铂、铝、银、上述的组合、类似物。图形318的形成方法可为任何合适技术如PVD、CVD、电化学沉积法(ECD)、分子束外延法(MBE)、原子层沉积法(ALD)、电镀法、或类似方法。必需注意的是某些实施例中，特别是顺应性沉积层状材料于晶片的整个表面上的工艺如PVD或CVD，可能需要进行蚀刻或平坦化工艺(比如CMP)将多余的导电材料自保护层316表面移除。
如图4A及图4B所示的一实施例中，沿着切割线201形成凹陷420。在切割线201的位置，凹陷420截断并露出部分的图形318。图形318露出部分的厚度介于约
Figure BSA00000397555600061
至约
Figure BSA00000397555600062
之间，可作为后续详述的裸片边缘接点。在一实施例中，凹陷420的深度至少相等于图形318的厚度。凹陷420的形成方法可为激光切割。激光切割可形成凹陷于保护层316如同形成凹陷于图形材料(如铜)中，这将使图形318具有露出的边缘并形成裸片边缘接点。
如图5A及图5B所示，在切割基板202后，形成抛光层522于图形318的表面上。在一实施例中，抛光层522可为直接位于图形318上并与之接触的镍层。此外可视情况形成额外层，使抛光层522为化学镀镍浸金层(ENIG)、镍化学镀钯与浸金层(ENEPIG)、或镍钯层。抛光层522的形成方法可为ECP、无电电镀法、或类似方法。
在一实施例中，抛光层522自图5A及图5B所示的裸片边缘表面凸出，这将使电性接点易于形成。在一实施例中，抛光层522自裸片边缘凸出的范围介于约
Figure BSA00000397555600063
至约
Figure BSA00000397555600064
之间。必需理解的是某些实施例需要较凸出的抛光层，此时需沉积额外的导电材料于图形318上，且导电材料与图形318的组成可相同或不同。举例来说，当图形318的组成为铜，可采用ECP工艺等方法形成额外的铜材于图形318上。
图形318/抛光层522组成裸片边缘接点524。可视情况薄化基板背面并形成盖层于裸片表面上。盖层也可作为散热器。
图6是一实施例中，裸片601的部分透视图。图6所示的实施例与图1所示的实施例类似，两者间类似的单元将沿用相同附图标记，除了裸片601的裸片边缘接点602延伸穿过整个裸片601。后续内容将进一步详述穿透基板通孔的作法，以及经由穿透基板通孔切割裸片的作法。
图7A-图9B是本发明一实施例中，形成图6所示的半导体元件的工艺在不同阶段的剖视图。A系列图示如图7A-图9A是沿着图6的A-A线段，而B系列图示如图7B-图9B是沿着图6的B-B线段。必需注意的是，B系列图示中含有两个相邻的裸片以更明确的说明实施例，其中所含的虚线201指的是两个相邻裸片之间的切割线。图2A-图5B及图7A-图9B中类似的元件将沿用相同附图标记，且不赘述类似元件的形成方法与材质。
首先如图7A及图7B所示，部分的基板202具有穿透基板通孔730形成其中。穿透基板通孔730可由任何合适技术形成，且由任何合适材质组成。举例来说，穿透基板通孔730的形成方法可为蚀刻或钻孔，形成穿透部分基板202的通孔如图7A-图7B所示。接着将导电材料如铝、铜、其他金属、合金、掺杂的多晶硅、上述的组合、或类似物填入通孔中。在后述内容中，可沿着穿透基板通孔730进行切割工艺，以形成裸片边缘接点。在一实施例中，穿透基板通孔730的直径介于约
Figure BSA00000397555600071
至约
Figure BSA00000397555600072
之间。
在其他技术中，可蚀刻部分基板形成通孔，再沉积介电层于通孔中以形成穿透基板通孔730。在此实施例中，先薄化基板背面再移除通孔中的介电层，之后再沉积导电材料于通孔中。除了上述方法外，也可采用其他方法。此外，穿透基板通孔730可含有衬垫层如阻挡层，其材质较佳为介电材料如氧化物、氮化物、或类似物。
如图8A及图8B所示，形成保护层316于基板202上。图8A及图8B所示的保护层316的组成与形成方法类似于前述图3A及图3B所示的保护层316，差别在此实施例的保护层316被进一步图案化以露出穿透基板通孔730。形成于保护层316中的沟槽可填入导电材料以形成图形318。
如图9A及图9B所示，在切割基板202后进行薄化晶片工艺，直到露出穿透基板通孔730。在切割基板后，可形成图5所示的抛光层522。在一实施例中，抛光层522自裸片边缘的表面凸出，如图9A及图9B所示。如此一来，可形成隆起的电性接点。如图9A及图9B所示，穿透基板通孔730/图形318/抛光层522所组成的裸片边缘接点950延伸至裸片的所有厚度。可视情况形成盖层于裸片表面上，且盖层可作为散热器。在另一实施例中，穿透基板通孔730(与之后形成的裸片边缘接点950)并未完全穿过裸片，即使在薄化基板202后也只有延伸穿过部分的基板202。
图10是本发明一实施例中，可用于封装多个裸片的多重裸片封装1002的透视图。此立体的SOC封装结合前述裸片边缘接点的技术，除可降低集成电路散热不良的风险并同时具备可抽换式与保留扩充插槽的架构，提升SOC维修与扩充的条件，降低维护与扩充成本。多重裸片封装1002含有外壳1004及内连线结构1006。一般来说，内连线结构1006具有一或多个墙状物或基板1007，裸片如图1及图6所示的裸片101及60可分别形成其上。如图10所示的实施例中，内连线结构1006具有四面墙状物或基板1007。沿着内连线结构1006的内表面，所述多个基板中至少一个具有裸片支撑物1012以支撑插置于内连线结构中的裸片。末端基板1007(如虚线框)有利于说明内连线结构1006的内部结构。每面墙状物可独立形成于单一晶片，切割后再以胶体或其他接着剂接合组装成图示结构。在图10所示的实施例中，内连线结构具有三个狭缝10091、10092、与10093。每一狭缝10091、10092、与10093可容纳同型裸片(比如相同存储器)，或容纳不同功能的裸片(比如一个为处理器裸片，而另一个为存储器裸片以形成系统级封装(SIP))。图中狭缝的数目只有三个，但其他实施例可具有更多或更少的狭缝。在图13中，三个裸片1301插置于内连线结构1006中。
延着内连线结构1006的内表面形成的接点1008，可提供电性连接至裸片边缘接点如图5及图9所示的裸片边缘接点524与950。接点1008电性耦合至一或多个沿着内连线结构1006的底部边缘形成的外部接点1010。外部接点可具有隆起的接点如导电柱、焊球/焊料凸块、上述的组合、或类似物，可将内连线结构1006电性耦合至印刷电路板、封装基板、高密度内连线结构、或类似物。
外壳1004的墙状物或基板1016是沿着内连线结构1006的外表面形成，可保护内连线结构1006。外壳1004也可作为散热器，可帮助多个裸片操作时产生的热散逸至环境中。基板1016可分别形成，再以胶体或其他接着剂组装成外壳。由外壳1004的内表面凸出的微悬吊柱1018可作为内连线结构1006的热扩散缓冲，也可作为内连线结构1006与外壳1004之间的热传输机构。
图11是用以形成多裸片封装1002的内连线结构的基板1007的剖视图，或用以容纳一或多个集成电路裸片(比如图1-图9B所示的裸片)的封装基板的剖视图。在一实施例中，基板1007中的基材1104具有金属层1106形成其上。基材1104可为基体硅、掺杂或未掺杂的基材、或绝缘层上硅(SOI)基板的有源层。在一实施例中，基材1104可为印刷电路板、压合基材、或类似物。在一实施例中，基材的组成如硅的热膨胀系数(CTE)，最好与置入多重裸片封装的集成电路裸片的基板类似。基材1104可具有一或多层的介电层。
金属层1106可为任何合适导电材料如铜、镍、铂、铝、银、上述的组合、或类似物。金属层1106的形成方法可为任何合适工艺如PVD、CVD、ECD、MBE、ALD、电镀法、或类似方法。
接着形成并图案化保护层1108于基材1104的表面上，使对应裸片边缘接点的接点区域的部分金属层1106露出。保护层1108可为一或多层的介电材料如氮化硅、PEOX、PE-SiN、PE-USG、高分子、或类似物。
接着根据图10的接点1008，形成隆起的接点1110于保护层1108内的开口中。隆起的接点1110可为一或多层的适当导电材料如铜、镍、铂、铝、银、上述的组合、会类似物。隆起的接点1110的形成方法可为任何合适技术如PVD、CVD、ECD、MBE、ALD、电镀、或类似方法。接着形成抛光层1112如镍层、ENIG层、ENEPIG层、或类似物。抛光层1112也可作为延着基板边缘形成的隆起的接点，如图11所示。在一实施例中，隆起的接点1110的高度介于约
Figure BSA00000397555600091
至约
Figure BSA00000397555600092
之间。
根据图10所示的裸片支撑物1012，形成于隆起的接点1110其行列之间的裸片支撑物1114可作为对准标记，也可让裸片插置于内连线结构1006中。裸片支撑物1114的组成可为介电材料如氧化硅、玻璃、或石英，其形成方法可为胶体粘结搭配印刷法，也可为粉末形成法。裸片支撑物1114也可为导电材料如金属球或金属立方结构，其形成方法可为胶体粘结搭配印刷法，也可为粉末冶金法。在一实施例中，裸片支撑物1114的高度介于约300μm至5,000μm之间，其宽度介于约300μm至约5,000μm之间。
必需注意的是图11中，单一金属层连接至每一隆起的接点1110的形式仅用以举例。在一实施例中，金属层的设计可让隆起的接点布线至不同的外部接点。
图12是用以形成图10的外壳1004的基板1016的剖视图。基板1016的基材1204含有微悬吊柱1210凸出其上。基材1204可为任何合适基材如硅基材、金属基材、陶瓷基材、或类似物。在一实施例中，基材1204的厚度为约1mm。微悬吊柱1210的组成可为硅胶橡胶、微金属弹簧、或类似物。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界的范围为准。

Claims (10)

1.一种半导体结构，包括：
一集成电路基板，具有一接触焊盘形成其上；
一保护层形成于该集成电路基板上，该保护层具有一开口于至少部分的该接触焊盘上，且该保护层具有一沟槽自该接触焊盘延伸至该集成电路基板的边缘；以及
一导电材料位于该保护层的该沟槽中，且该导电材料自该接触焊盘延伸至该集成电路基板的边缘。
2.根据权利要求1所述的半导体结构，还包括一穿透基板通孔于该基板的边缘上，且该裸片边缘接点包括该穿透基板通孔。
3.根据权利要求1所述的半导体结构，还包括一内连线结构，该内连线结构具有多个内连线基板与该集成电路基板垂直，至少一内连线基板具有另一接触焊盘，且该另一接触焊盘电性耦合至该裸片边缘接点。
4.根据权利要求3所述的半导体结构，还包括一外壳，该外壳具有多个外壳基板，且所述多个外壳基板与该集成电路基板分别位于该内连线结构相反的两侧。
5.根据权利要求4所述的半导体结构，还包括一微悬吊柱夹设于该内连线结构与该外壳之间。
6.一种半导体结构的形成方法，包括：
提供一晶片，具有多个接点形成其上；
形成一保护层于该晶片上；
图案化该保护层以露出所述多个接点，并形成多个沟槽自个别的所述多个接点延伸至一切割线；
形成一导电材料于该沟槽中；以及
延着该切割线将该晶片分隔为多个裸片，其中该沟槽中的至少部分该导电材料沿着该切割线边缘露出。
7.根据权利要求6所述的半导体结构的形成方法，还包括在该晶片中沿着该切割线形成多个穿透基板通孔于该沟槽下，使该沟槽中的导电材料电性耦合至个别的所述多个穿透基板通孔。
8.一种半导体结构的形成方法，包括：
提供一或多个集成电路裸片，其中每一该集成电路裸片具有多个裸片边缘接点，其中所述裸片边缘接点是一导电材料并位于一保护层的沟槽中，且该导电材料自一接触焊盘延伸至该集成电路基板的边缘；
提供一内连线结构，其中该内连线结构包括一或多个内连线基板，且至少一该内连线基板具有多个电性接点形成其上；以及
将一或多个该集成电路裸片置于该内连线结构中，使一或多个该集成电路裸片的所述多个裸片边缘接点电性耦合至至少一该内连线基板中个别的所述多个电性接点，其中该内连线基板垂直该集成电路裸片的主要表面。
9.根据权利要求8所述的半导体结构的形成方法，还包括一外壳位于该内连线结构的一侧，且该外壳与该集成电路裸片分别位于该内连线结构相反的两侧。
10.根据权利要求9所述的半导体结构的形成方法，还包括一微悬吊柱夹设于该外壳与该内连线结构之间。
CN201010602782.8A 2010-09-02 2010-12-21 半导体结构及其形成方法 Active CN102386157B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/874,816 US8541262B2 (en) 2010-09-02 2010-09-02 Die edge contacts for semiconductor devices
US12/874,816 2010-09-02

Publications (2)

Publication Number Publication Date
CN102386157A CN102386157A (zh) 2012-03-21
CN102386157B true CN102386157B (zh) 2014-05-07

Family

ID=45770110

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010602782.8A Active CN102386157B (zh) 2010-09-02 2010-12-21 半导体结构及其形成方法

Country Status (3)

Country Link
US (2) US8541262B2 (zh)
CN (1) CN102386157B (zh)
TW (1) TWI418000B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5805306B2 (ja) * 2011-05-06 2015-11-04 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ 複数の構成素子支持領域を分離する溝構造を備えている構成素子支持体結合体及び複数の構成素子支持体領域の製造方法
US8803322B2 (en) 2011-10-13 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through substrate via structures and methods of forming the same
US9269678B2 (en) * 2012-10-25 2016-02-23 United Microelectronics Corp. Bond pad structure and method of manufacturing the same
KR101758857B1 (ko) * 2014-10-24 2017-07-18 삼성전기주식회사 인쇄회로기판, 그 제조방법 및 모듈
US9466585B1 (en) 2015-03-21 2016-10-11 Nxp B.V. Reducing defects in wafer level chip scale package (WLCSP) devices
US9852959B2 (en) 2016-02-05 2017-12-26 Globalfoundries Inc. Corrosion resistant chip sidewall connection with crackstop and hermetic seal
US10134719B2 (en) * 2016-06-30 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9685535B1 (en) 2016-09-09 2017-06-20 International Business Machines Corporation Conductive contacts in semiconductor on insulator substrate
CN110416236A (zh) * 2018-04-28 2019-11-05 中芯国际集成电路制造（天津）有限公司 芯片的封装方法、半导体结构及其制备方法
CN109817602A (zh) * 2019-01-31 2019-05-28 中国科学院微电子研究所 基板及其制造方法
US10879206B1 (en) * 2019-10-16 2020-12-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for forming the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7375009B2 (en) * 2002-06-14 2008-05-20 Micron Technology, Inc. Method of forming a conductive via through a wafer

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
KR100245257B1 (ko) * 1993-01-13 2000-02-15 윤종용 웨이퍼 수준의 반도체 패키지의 제조방법
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
JP3519453B2 (ja) * 1994-06-20 2004-04-12 富士通株式会社 半導体装置
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6252302B1 (en) 1996-09-19 2001-06-26 Warren M. Farnworth Heat transfer material for an improved die edge contacting socket
US6034438A (en) 1996-10-18 2000-03-07 The Regents Of The University Of California L-connect routing of die surface pads to the die edge for stacking in a 3D array
US5990566A (en) 1998-05-20 1999-11-23 Micron Technology, Inc. High density semiconductor package
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
JP2000243900A (ja) * 1999-02-23 2000-09-08 Rohm Co Ltd 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
SG102639A1 (en) 2001-10-08 2004-03-26 Micron Technology Inc Apparatus and method for packing circuits
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6855572B2 (en) * 2002-08-28 2005-02-15 Micron Technology, Inc. Castellation wafer level packaging of integrated circuit chips
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
EP2575166A3 (en) * 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
TWI515863B (zh) 2008-03-12 2016-01-01 英維瑟斯公司 載體安裝式電氣互連晶粒組成件
US7863722B2 (en) * 2008-10-20 2011-01-04 Micron Technology, Inc. Stackable semiconductor assemblies and methods of manufacturing such assemblies
US8338939B2 (en) * 2010-07-12 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation processes using TSV-last approach

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7375009B2 (en) * 2002-06-14 2008-05-20 Micron Technology, Inc. Method of forming a conductive via through a wafer

Also Published As

Publication number Publication date
TWI418000B (zh) 2013-12-01
TW201212185A (en) 2012-03-16
US20130328215A1 (en) 2013-12-12
US9190347B2 (en) 2015-11-17
US20120056328A1 (en) 2012-03-08
CN102386157A (zh) 2012-03-21
US8541262B2 (en) 2013-09-24

Similar Documents

Publication Publication Date Title
CN102386157B (zh) 半导体结构及其形成方法
US11594462B2 (en) Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US11610865B2 (en) Semiconductor package
US11626388B2 (en) Interconnect structure with redundant electrical connectors and associated systems and methods
US9837383B2 (en) Interconnect structure with improved conductive properties and associated systems and methods
JP6858569B2 (ja) Ｔｓｖ構造体を有した多重積層素子
US10679921B2 (en) Semiconductor device packages with direct electrical connections and related methods
CN106206337B (zh) 半导体装置及半导体装置的制造方法
CN100470793C (zh) 半导体器件和制造半导体器件的方法
CN102214617B (zh) 半导体封装基板
CN202534641U (zh) 已封装电子器件
US11887841B2 (en) Semiconductor packages
CN107408546B (zh) 具有底部填充封围腔的半导体装置组合件
CN106910736A (zh) 半导体封装及其制造方法
CN203085525U (zh) 可用于堆叠的集成电路
CN108428679A (zh) 具有热导柱的集成电路封装
WO2022132274A1 (en) Hermetic sealing structures in microelectronic assemblies having direct bonding
EP4260370A1 (en) Hermetic sealing structures in microelectronic assemblies having direct bonding
KR20230043271A (ko) 반도체 칩 및 반도체 패키지
CN115881688A (zh) 封装件及其形成方法
KR20170109328A (ko) 반도체 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant