CN115881688A - 封装件及其形成方法 - Google Patents
封装件及其形成方法 Download PDFInfo
- Publication number
- CN115881688A CN115881688A CN202210707612.9A CN202210707612A CN115881688A CN 115881688 A CN115881688 A CN 115881688A CN 202210707612 A CN202210707612 A CN 202210707612A CN 115881688 A CN115881688 A CN 115881688A
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- Prior art keywords
- bond pad
- semiconductor substrate
- dielectric layer
- die
- bonding
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Abstract
方法包括:在第一晶圆上形成第一介电层;以及形成穿透第一介电层的第一接合焊盘。第一晶圆包括第一半导体衬底,并且第一接合焊盘与第一半导体衬底的第一表面接触。方法还包括:在第二晶圆上形成第二介电层;以及形成延伸至第二介电层中的第二接合焊盘。第二晶圆包括第二半导体衬底。将第一晶圆锯切成多个管芯,第一接合焊盘位于多个管芯中的第一管芯中。第一接合焊盘接合至第二接合焊盘。本申请的实施例还涉及封装件及其形成方法。
Description
技术领域
本申请的实施例涉及封装件及其形成方法。
背景技术
混合接合是用于将两个封装组件(诸如晶圆和管芯)彼此接合的常见的接合方案。利用混合接合,可以在不增加用于形成接合的封装组件成本的情况下实现高接合强度。
发明内容
本申请的一些实施例提供了一种形成封装件的方法,包括:在第一晶圆上形成第一介电层,其中,所述第一晶圆包括第一半导体衬底;形成穿透所述第一介电层的第一接合焊盘,其中,所述第一接合焊盘与所述第一半导体衬底的第一表面接触;在第二晶圆上形成第二介电层,其中,所述第二晶圆包括第二半导体衬底;形成延伸至所述第二介电层中的第二接合焊盘;将所述第一晶圆锯切成多个管芯,其中,所述第一接合焊盘位于所述多个管芯中的第一管芯中;以及将所述第一接合焊盘接合至所述第二接合焊盘。
本申请的另一些实施例提供了一种封装件,包括:第一管芯,包括:第一半导体衬底;第一介电层,位于所述第一半导体衬底上方;以及第一接合焊盘,位于所述第一半导体衬底上方并且物理连接至所述第一半导体衬底,其中,所述第一接合焊盘延伸至所述第一介电层中;以及第二管芯,位于所述第一管芯上方,所述第二管芯包括:第二半导体衬底;第二介电层,位于所述第一半导体衬底下面,其中,所述第二介电层接合至所述第一介电层;以及第二接合焊盘,位于所述第二半导体衬底下面,其中,所述第二接合焊盘延伸至所述第二介电层中,并且所述第二接合焊盘接合至所述第一接合焊盘。
本申请的又一些实施例提供了一种封装件,包括:第一管芯,包括:第一半导体衬底;集成电路,位于所述第一半导体衬底的正面上方和正面上;多个介电层,位于所述第一半导体衬底的所述正面上方和正面上;第一深接合焊盘,穿透所述多个介电层;以及第一有源接合焊盘,位于所述多个介电层的第一顶面层中,其中,所述第一有源接合焊盘包括与所述第一深接合焊盘的第二顶面和所述第一有源接合焊盘的第三顶面共面的第一顶面。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图9示出了根据一些实施例的在管芯的形成中的中间阶段的截面图。
图10至图14示出了根据一些实施例的使用图1至图9中所示的工艺形成的一些管芯的截面图。
图15示出了根据一些实施例的通过混合接合形成的管芯堆叠件。
图16和图17示出了根据一些实施例的接合的管芯。
图18至图21示出了根据一些实施例的一些接合焊盘的顶视图。
图22示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外,为了便于描述,本文可以使用诸如“位于…下面”、“在…下方”、“下部”、“位于…上面”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
提供了包括深接合焊盘的器件管芯及其形成方法。示出了包括接合的器件管芯的封装件。深接合焊盘可以延伸至对应器件管芯的半导体衬底。随着深接合焊盘形成,提高了所得封装件的散热,并且接合更加可靠。深接合焊盘可以用于实现与介电层接合相结合的混合接合。深接合焊盘也可以与浅接合焊盘和/或有源金属焊盘结合使用,本文讨论的实施例是为了提供能够制造或使用本发明的主题的实例,并且本领域普通技术人员将容易理解在保持在不同实施例的预期范围内的同时可以进行的修改。贯穿各个视图和说明性实施例,相同的参考标号用于表示相同的元件。虽然方法实施例可以讨论为以特定顺序实施,但是其它方法实施例可以以任何逻辑顺序实施。
图1至图9示出了根据本发明的一些实施例的在晶圆和管芯的形成中的中间阶段的截面图。对应的工艺也示意性地反映在如图22中所示的工艺流程200中。
图1示出了在晶圆2中形成集成电路和通孔的截面图。相应的工艺示出为如图22中所示的工艺流程200中的工艺202。根据本发明的一些实施例,晶圆2是包括有源器件(诸如晶体管和/或二极管)和/或无源器件(诸如电容器、电感器、电阻器等)的器件晶圆。根据可选实施例,晶圆2是没有有源器件的伪晶圆。器件晶圆2中可以包括多个完全相同的芯片4,其中示出了芯片4中的一个。芯片4在下文中可选地称为(器件)管芯。
管芯4可以选自各种类型的器件管芯。根据本发明的一些实施例,器件管芯4是逻辑管芯,其可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、微控制单元(MCU)管芯、基带(BB)管芯、应用处理器(AP)管芯等。根据可选实施例,管芯4是存储器管芯,其可以是静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯、电阻随机存取存储器(RRAM)管芯等。根据又一些可选实施例,管芯4是模拟管芯或伪管芯。当是伪管芯时,管芯4没有有源器件(诸如晶体管和二极管)和/或无源管芯(诸如电容器、电阻器、电感器等)。
根据本发明的一些实施例,晶圆2包括半导体衬底5。半导体衬底5可以由晶体硅、晶体锗、晶体硅锗或III-V族化合物半导体(诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等)形成。半导体衬底5也可以是块状硅衬底或绝缘体上硅(SOI)衬底。可以在半导体衬底5中形成浅沟槽隔离(STI)区域(未显示)以隔离半导体衬底5中的有源区域。
根据一些实施例,通孔6(有时也称为硅通孔或半导体通孔)形成为延伸至半导体衬底5中。通孔6可以包括或由金属材料形成,诸如铜、镍、钨等。包围通孔6形成将通孔6与半导体衬底5电隔离的隔离层(未显示)。通孔6形成为延伸至半导体衬底5的顶面和底面之间的中间水平。通孔6中的一个显示为虚线以指示它可以形成或者可以不形成。通孔6可以具有不同的尺寸。例如,一些通孔6(其可以用于热传导)的宽度(或直径)W1大于一些其它通孔6(其可以用于布线电信号)的宽度W2。根据可选实施例,器件管芯4中没有通孔。
根据本发明的一些实施例,器件管芯4是包括集成电路器件8(其形成在半导体衬底5的顶面上)的有源管芯。示例性集成电路器件8可以包括有源器件(诸如互补金属氧化物半导体(CMOS)晶体管和二极管)和无源器件(诸如电阻器、电容器、电感器等)。集成电路器件8的细节在此未示出。根据可选实施例,器件管芯4是伪管芯,其中没有有源器件和无源器件管芯。
图2示出了正面互连结构16的形成。相应的工艺示出为如图22中所示的工艺流程200中的工艺204。在半导体衬底5上方形成填充集成电路器件8中的晶体管(未显示)的栅极堆叠件之间的间隔的层间电介质(ILD)10。根据一些示例性实施例,ILD 10由氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)等形成。ILD 10可以使用旋涂、可流动化学气相沉积(FCVD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)等形成。
在ILD 10中形成用于将集成电路器件8和通孔6电连接至上面的金属线和通孔的接触插塞12。根据本发明的一些实施例,接触插塞12由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金和/或它们的多层的导电材料形成。接触插塞12的形成可以包括:在ILD 10中形成接触开口;将导电材料填充至接触开口中;以及实施平坦化(诸如化学机械抛光(CMP)工艺)以使接触插塞12的顶面与ILD 10的顶面齐平。
在ILD 10和接触插塞12上方形成互连结构16。互连结构16包括介电层22、金属线(和焊盘)18和介电层22中的通孔20。介电层22在下文中可选地称为金属间介电(IMD)层22。根据本发明的一些实施例,一些或全部介电层22由具有低于约3.0或约2.5的介电常数值(k值)的低k介电材料形成。介电层22可以由含碳的低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的一些实施例,介电层22的形成包括:沉积含致孔剂的介电材料;以及然后实施固化工艺以驱除致孔剂,并且因此剩余的介电层22是多孔的。根据本发明的可选实施例,一些或全部介电层22由非低k介电材料形成,诸如氧化硅、碳化硅(SiC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)等。可以在IMD层22之间形成可以由氮氧化硅、氧化铝、氮化铝等或它们的组合形成的蚀刻停止层(未显示),并且为了简单起见未显示。
金属线18和通孔20形成在介电层22中。相同层级处的金属线18在下文中统称为金属层。根据本发明的一些实施例,互连结构16包括通过通孔20互连的多个金属层。金属线18和通孔20可以由铜或铜合金形成,并且它们也可以由其它金属形成。形成工艺可以包括单重镶嵌工艺和双重镶嵌工艺。在示例性单重镶嵌工艺中,首先在介电层22中的一个中形成沟槽,随后利用导电材料填充沟槽。然后实施诸如CMP工艺的平坦化工艺以去除导电材料的高于IMD层的顶面的过量部分,在沟槽中留下金属线。在双重镶嵌工艺中,沟槽和通孔开口都形成在IMD层中,通孔开口位于沟槽下面并且连接至沟槽。然后将导电材料填充至沟槽和通孔开口中以分别形成金属线和通孔。导电材料可以包括扩散阻挡层和扩散阻挡层上方的含铜金属材料。扩散阻挡层可以包括钛、氮化钛、钽、氮化钽等。
参考图3,根据本发明的一些实施例沉积表面介电层24。相应的工艺示出为如图22中所示的工艺流程200中的工艺206。表面介电层24由非低k介电材料形成,并且可以与下面的介电层22物理接触,或者通过诸如蚀刻停止层的其它层与介电层22分隔开。表面介电层24可以是包括硅和另一元素(包括氧、氮、碳等或它们的组合)的基于氧化硅的介电材料。例如,表面介电层24可以包括或由氧化硅、氮氧化硅(SiON)、氮化硅(SiN)、氮氧化硅(SiON)、碳氮氧化硅(SiOCN)、碳氮化硅(SiCN)、碳氧化硅(SiOC)、碳化硅(SiC)等形成。
通过蚀刻工艺在表面介电层24中形成开口26和28。在开口26的形成中,顶部金属化层中的金属线/焊盘18中的金属焊盘用作蚀刻停止层,并且金属焊盘18露出。在开口28的形成中,下面的介电层用作蚀刻停止层,并且暴露于开口28。虽然未显示,开口26可以包括通孔开口和通孔开口上方的沟槽,其用于形成双重镶嵌结构。
参考图4,形成有源接合焊盘30和浅接合焊盘32。相应的工艺示出为如图22中所示的工艺流程200中的工艺208。浅接合焊盘32是在最终封装件中电浮置的伪接合焊盘。形成工艺可以包括:沉积共形阻挡层(使用诸如TiN、TaN、Ti、Ta等的导电材料);沉积诸如铜、钨、钴等的金属材料;以及实施平坦化工艺以去除过量材料。
图4还示出了通过多个蚀刻工艺形成开口34(包括开口34A和34B)。相应的工艺示出为如图22中所示的工艺流程200中的工艺210。多个蚀刻工艺可以响应于介电层22、ILD10和蚀刻停止层的不同材料而采用不同的蚀刻气体。半导体衬底5的顶面暴露于开口34A。半导体衬底5的顶面和通孔6(如果形成)中的一个的顶面暴露于开口34B。根据一些实施例,开口34具有其与半导体衬底5的顶面齐平或基本齐平的底面。根据可选实施例,开口34延伸至半导体衬底5中以形成具有深度D1的凹槽,其可以大于约深度D1也可以在约/>和约/>之间的范围内。虚线代表凹槽的对应底部和侧壁。
参考图5,形成深接合焊盘36(包括36A和36B)。相应的工艺示出为如图22中所示的工艺流程200中的工艺212。形成工艺也可以包括:沉积共形阻挡层(诸如TiN、TaN、Ti、Ta等);沉积诸如铜、钨、钴等的金属材料;以及实施平坦化工艺以去除过量材料。所得深接合焊盘36A具有其接触半导体衬底5的顶面的整个底面。此外,深接合焊盘36A的侧壁可以不连接至任何其它导电部件(诸如金属部件)。另一方面,深接合焊盘36B电连接至下面的通孔6。应该理解,对应通孔6使用虚线示出,以指示它可以形成或者可以不形成。深接合焊盘36可以具有从介电层24的顶面延伸至半导体衬底5的顶面的直侧壁。
下一步,如图6中所示,对半导体衬底5的背面(所示的底侧)实施背面研磨工艺以去除半导体衬底5的部分,直至通孔6露出。相应的工艺示出为如图22中所示的工艺流程200中的工艺214。然后使半导体衬底5从背面略微凹进(例如,通过蚀刻),使得通孔6从半导体衬底5的背表面(所示的底面)突出。
根据可选实施例,没有形成通孔6,并且跳过对晶圆2的背面实施的工艺(如图6至图9中所示)。
下一步,同样如图6中所示,沉积介电层38,随后是CMP工艺或机械研磨工艺以重新暴露通孔6。相应的工艺示出为如图22中所示的工艺流程200中的工艺216。因此通孔6也穿透介电层38。根据一些实施例,介电层38由氧化硅、氮化硅、氮氧化硅、碳氮化硅等形成。
参考图7,可以形成背面再分布线(RDL)40,其包括接触通孔6的焊盘部分。相应的工艺示出为如图22中所示的工艺流程200中的工艺218。根据一些实施例,RDL 40可以由铝、铜、镍、钛等形成。可以形成介电层42,RDL 40延伸至介电层42中。虽然形成一个介电层42和一个RDL 40层作为实例,但是可以形成多个介电层和多个RDL层,这取决于布线要求。
图8进一步示出了有源接合焊盘45、浅接合焊盘47和接合焊盘46的形成。相应的工艺示出为如图22中所示的工艺流程200中的工艺220。有源接合焊盘45电连接至通孔6,通孔6进一步连接至集成电路8和/或有源接合焊盘30接合焊盘46电连接至通孔6和深接合焊盘36B。浅接合焊盘47是在最终封装件中电浮置的伪接合焊盘,每个由介电材料完全包围。根据一些实施例,接合焊盘46包括或由氮化钛、铜、钨等、它们的多层和/或它们的合金形成。
根据一些实施例,接合焊盘46形成在表面介电层44中,其可以包括或可以由氧化硅、SiN、SiC、SiOC、SiON、SiOCN等形成。接合焊盘46的底面可以与表面介电层44的底面共面。
图9示出了深接合焊盘48A的形成。相应的工艺示出为如图22中所示的工艺流程200中的工艺222。根据一些实施例,深接合焊盘48A的形成包括:蚀刻穿过介电层38、42和44以在半导体衬底5的背面上形成开口,使得半导体衬底5的背表面(所示的底面)暴露于开口;利用导电材料填充开口;以及实施平坦化工艺。深接合焊盘48A的导电材料可以选自用于形成深接合焊盘36A的相同的候选材料组。根据这些实施例,深接合焊盘48A可以通过半导体衬底5热连接至深接合焊盘36A以形成导热沟道。
根据可选实施例,代替形成接合焊盘46和RDL 40以连接至通孔6和深接合焊盘36B,在半导体衬底的背面上形成使用虚线示出的深接合焊盘48B。深接合焊盘48B可以与深接合焊盘48A的形成同时形成。因此深接合焊盘36B和48B以及对应通孔6形成导热沟道。
根据一些实施例,深接合焊盘36的横向尺寸W3和深接合焊盘48的横向尺寸W3’大于有源接合焊盘30的横向尺寸W4和有源接合焊盘45的横向尺寸W4’。因此,提高了导热路径的导热效率,并且同时可以形成更多的信号路径。横向尺寸W3和W3’也可以等于或大于浅接合焊盘32的横向尺寸W5和浅接合焊盘47的横向尺寸W5’。
在随后的工艺中,可以沿划线50通过锯切工艺分割晶圆2,并且器件管芯4彼此分隔开。相应的工艺示出为如图22中所示的工艺流程200中的工艺224。
器件管芯4可以包括任意组合的四种类型的接合焊盘(包括有源接合焊盘30、(伪)浅接合焊盘32、深接合焊盘36A和深接合焊盘36B),这意味着在管芯中,可以以任意组合在器件管芯4的相同侧中形成一种、两种、三种或所有四种类型的接合焊盘。接合焊盘的这些组合可以形成在半导体衬底5的正面(可选地称为有源侧)、背面或正面和背面上。贯穿描述,半导体衬底5的具有有源集成电路8的侧称为有源侧或正面,并且相对侧称为无源侧或背面。当形成在背面上时,器件管芯4可以包括任意组合的一种、两种、三种或四种类型的有源接合焊盘45、浅接合焊盘47、接合焊盘46和深接合焊盘48。
此外,器件管芯4可以包括集成电路8,其可以包括有源器件,并且可以包括或可以不包括无源器件。对应器件管芯4是有源器件管芯。根据可选实施例,器件管芯4包括无源器件并且没有有源器件。根据又一些可选实施例,器件管芯4没有有源器件和无源器件。在这种情况下,器件管芯4是伪管芯。图13、图14和图15中显示了一些示例性伪管芯4。
在一些器件管芯4中,形成通孔6,并且在相应器件管芯4的正面和背面上形成接合焊盘。所得器件管芯4称为双面器件管芯,图10、图11和图13至图15中显示了一些实例。在一些其它器件管芯4中,没有形成通孔6,并且跳过了对晶圆2的背面实施的工艺(如图6至图9中所示)。所得器件管芯4是单面的,图12和图15中显示了示例性单面器件管芯4。
图10至图14示出了一些示例性器件管芯4,它们可以使用参考图1至图9所讨论的工艺来形成。示例性器件管芯4堆叠以形成如图15中所示的封装件。根据这些实施例的器件管芯4具有不同的部件组合,这在上面已提到。应该理解,同样如上所述,也可以采用任何其它组合来形成不同的器件管芯,这也在本发明的范围内。这些图中的器件管芯的细节(诸如介电层、金属线、通孔、RDL等)未显示,并且细节可以参考先前讨论的实施例找到。
图10示出了根据一些实施例的双面器件管芯4(也表示为4-3)。对应器件管芯4的所示底侧可以是正面,并且相应集成电路8位于使用实线所示的位置处。根据可选实施例,对应器件管芯4的所示顶侧可以是正面,并且相应集成电路8位于使用虚线所示的位置处。
在图11中,对应器件管芯4(也表示为4-2A)的所示顶侧可以是正面,并且也示出了虚线框以显示所示的底侧可以替代地是相应器件管芯4的正面。也示意性地示出了无源器件33。
图12示出了根据一些实施例的单面器件管芯4(也表示为4-1)。示出了深接合焊盘36。也示出了一些浅接合焊盘32。位于浅接合焊盘32中的一个下面的虚线(标记为36)指示这些浅接合焊盘也可以形成为深接合焊盘,其在图15中用于显示深接合焊盘36也可以用作与集成电路8的电连接。
图13和图14示出了一些示例性伪管芯4,它们没有有源器件和无源器件。图13示出了伪管芯,诸如接合焊盘46和深接合焊盘48的背面部件显示为虚线以指示伪管芯4可以是双面的或单面的。图14示出了示例性双面伪管芯4(也表示为4-2B),其包括如图13中所示的部件的部分。使用虚线显示了通孔6以示出通孔可以形成或可以不形成。当形成时,这些通孔以及上面的深接合焊盘36和下面的深接合焊盘48可以用作电连接或导热路径以互连上面的管芯和下面的管芯。不连接至任何通孔的接合焊盘36A(图13)用作导热沟道。根据一些实施例,在器件管芯的正面上存在由均质介电材料形成的单个介电层24,并且深(伪)接合焊盘36A和36B穿透单个介电层24。根据可选实施例,在伪管芯4的正面上存在两个介电层24A和24B,浅接合焊盘32位于上介电层24B中。在衬底5的背面上,也可以存在单个介电层或两个介电层。
图15示出了通过接合如图10至图12和图14中所示的器件管芯4的多个层形成的封装件52。为了区分封装件52中的器件管芯,器件管芯4的每个可以随后是“-”符号和层号以指示器件管芯的层。可以存在“n”个器件管芯4的层堆叠,并且整数n可以是2、3、4、5或更多。此外,在相同层中,使用字母A、B、C等来彼此区分器件管芯4。例如,在封装件52中,层-2器件管芯包括有源器件管芯4-2A和伪管芯4-2B和4-2C。可以使用可以是模制化合物、模制底部填充物等的密封剂54来填充相邻器件管芯4之间的间隙。所示示例性器件管芯4除了包括集成电路8之外,也可以包括无源器件33。接合的器件管芯包括有源器件管芯4-1、4-2A、4-3和4-n。此外,双面伪器件管芯4-2B和单面伪器件管芯4-2C也接合在管芯堆叠件中。
根据一些实施例,在顶部器件管芯4-n的顶面上形成电连接件58,其可以是焊料区域、金属柱、接合焊盘等。根据一些实施例,底部器件管芯4-1在其底面处没有电连接件,并且其中没有通孔。在有源器件管芯4-1、4-2A和4-3的每个中,存在指示集成电路8的位置的实心框,其也指示了哪侧是对应器件管芯4的正面。在器件管芯4-2A和4-2的每个中也存在虚线框以表示可选实施例,其中集成电路8不是形成在实心框所在的位置,而是形成在虚线框所在的位置。因此,图15显示了面至面接合、背至背接合和面至背接合方案,这取决于集成电路8所在的位置。
根据一些实施例,器件管芯4之间的接合通过混合接合(其包括通过直接金属至金属接合将金属焊盘接合至金属焊盘)和表面介电层的熔融接合来接合。例如,一个器件管芯4或伪管芯4(4-2B或4-2C)中的深接合焊盘36(参考图9)和浅接合焊盘32的每个可以通过金属至金属接合与深接合焊盘36和48以及浅接合焊盘32和47中的任何一个接合。有源接合焊盘30(参考图9)的每个可以接合至另一器件管芯中的有源接合焊盘30或45。表面介电层24(图9)可以接合至相邻管芯中的表面介电层24或表面介电层44,生成Si-O-Si结合。
一些示例性接合方案简要讨论如下。应该理解,也可以翻转器件管芯4的每个的正面和背面,如上所述。因此,所示的正面接合焊盘可以可选地是背面接合焊盘,并且反之亦然。接合结构60-1表示第一器件管芯4-1中的深接合焊盘36至第二器件管芯4-2A的深接合焊盘48的接合。接合结构60-2表示第二器件管芯4-2A中的深接合焊盘36至第三器件管芯4-3的深接合焊盘36的接合。
接合结构60-3表示第三器件管芯4-3中的深接合焊盘36至第二器件管芯4-2A的浅接合焊盘32的接合。接合结构60-1、60-2和60-3电连接至对应器件管芯4的半导体衬底5。接合结构60-4表示第三器件管芯4-3中的浅接合焊盘(例如,图10中的接合焊盘32)至第二器件管芯4-2A的浅接合焊盘32的接合。接合结构60-4电浮置。接合结构60-5和60-6表示相邻器件管芯4中的有源接合焊盘(例如,接合焊盘30和/或45)的接合,使得相邻器件管芯中的集成电路电互连。
伪管芯4-2B和4-2C没有有源器件和无源器件,并且可以用于填充由相对小的器件管芯4-2A留下的间隔。伪管芯4-2B是双面伪管芯,深(伪)接合焊盘位于对应半导体衬底5的一侧或两侧上。当形成通孔6时,对应接合焊盘可以是不具有电气功能的伪焊盘,或者可以用作用于将器件管芯4-1电连接至器件管芯4-3的信号路径或电源路径(VDD或接地)。例如,当深接合焊盘形成为接合结构60-7的一部分时,对应深接合焊盘36(虚线)可以用于连接至器件管芯4-1的衬底5。当伪管芯4-2B中不形成通孔6时,伪管芯4-2B中的深接合焊盘可以用于散热,例如,用于将器件管芯4-3中生成的热量传导至器件管芯4-1,并且然后传导至下面的散热器(未显示)。也可以在伪管芯4-2B中形成浅接合焊盘32和/或47以提高接合强度。
伪管芯4-2C是单面管芯,深(伪)接合焊盘和浅接合焊盘形成在对应半导体衬底5的一侧上。同样,可以在半导体衬底5中形成通孔6,或者半导体衬底5可以没有通孔6。
图16和图17示出了图15中的两个接合的管芯的一些细节。图16示出了根据一些实施例的通过面至背接合而彼此接合的两个晶圆2-1’和2-2’(和/或器件管芯4-1’和4-2’)。器件管芯4-1’和4-2’可以表示图15中的两个器件管芯(诸如器件管芯4-2A和4-3)。箭头66的方向指示对应器件管芯4的正面所面向的方向。在所示实例中,下器件管芯4-1’具有其接合至上器件管芯4-2’的背面的正面。
图17示出了根据一些实施例的通过面至面接合而彼此接合的两个晶圆2-1”和2-2”(和/或器件管芯4-1”和4-2”)。器件管芯4-1’和4-2’也可以表示图15中的两个器件管芯(诸如器件管芯4-2A和4-3)。箭头68的方向指示对应器件管芯4的正面所面向的方向。在所示实例中,下器件管芯4-1”具有其接合至上器件管芯4-2”的背面的正面。
图18至图21示出了根据一些实施例的一些接合焊盘64的顶视图。接合焊盘64的每个可以表示有源接合焊盘30和45(图9)、浅接合焊盘32和47、接合焊盘46以及深接合焊盘48中的任何一个。应该理解,虽然圆形和矩形用作实例来显示接合焊盘64的顶视形状,但是也可以采用其它形状,诸如六边形、椭圆形、八边形等。
参考图18,接合焊盘64可以布置为具有诸如阵列的重复图案。接合焊盘64可以具有彼此相同的尺寸和形状。参考图19,接合焊盘64可以布置为具有包括彼此交错的两个阵列的交错图案。接合焊盘64可以具有相同的尺寸。同样,接合焊盘64可以具有彼此相同的形状。图20示出了布置为交错的接合焊盘64,一个阵列中的接合焊盘64A具有与另一阵列中的接合焊盘64B的尺寸不同的的尺寸。图21示出了布置为交错的接合焊盘64,一个阵列中的接合焊盘64C具有与另一阵列中的接合焊盘64D不同的形状。
在上述实施例中,根据本发明的一些实施例讨论了一些工艺和部件以形成三维(3D)封装件。也可以包括其它部件和工艺。例如,可以包括测试结构以帮助对3D封装或3DIC器件进行验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘,它允许测试3D封装或3DIC、使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上实施。此外,本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法结合使用,以增加良率并且降低成本。
本发明的实施例具有一些有利特征。通过形成深接合焊盘,提高了从一个器件管芯至另一个(以及至散热器)的散热,因为热量可以通过这些焊盘直接传导至半导体衬底,而不通过低导热介电层。由于深接合焊盘至对应半导体衬底的良好锚定,也提高了接合可靠性。此外,浅接合焊盘与深接合焊盘和有源接合焊盘相结合,以进一步提高接合可靠性。
根据本发明的一些实施例,方法包括:在第一晶圆上形成第一介电层,其中,第一晶圆包括第一半导体衬底;形成穿透第一介电层的第一接合焊盘,其中,第一接合焊盘与第一半导体衬底的第一表面接触;在第二晶圆上形成第二介电层,其中,第二晶圆包括第二半导体衬底;形成延伸至第二介电层中的第二接合焊盘;将第一晶圆锯切成多个管芯,第一接合焊盘位于多个管芯中的第一管芯中;以及将第一接合焊盘接合至第二接合焊盘。
在实施例中,方法还包括:通过熔融接合将第一介电层接合至第二介电层。在实施例中,第二接合焊盘物理接触第二半导体衬底。在实施例中,在第一半导体衬底上方形成第一多个介电层,第一介电层是第一多个介电层的表面层,并且其中,第一接合焊盘穿透第一多个介电层的每个。在实施例中,方法还包括:在第一半导体衬底的正面上形成集成电路;以及在第一介电层中形成有源接合焊盘,其中,有源接合焊盘电连接至集成电路。
在实施例中,第一接合焊盘和第一介电层形成在第一管芯的正面上。在实施例中,第一接合焊盘形成在第一管芯的背面上,并且其中,背面与正面相对。在实施例中,方法还包括:在第一介电层中形成浅接合焊盘,其中,浅接合焊盘电浮置。在实施例中,在第二半导体衬底上方形成第二多个介电层,第二介电层是第二多个介电层的表面层,并且其中,第二接合焊盘具有接触第二多个介电层中的额外介电层的顶面的底面。在实施例中,第一晶圆中没有有源器件和无源器件。
根据本发明的一些实施例,封装件包括:第一管芯,包括:第一半导体衬底;第一介电层,位于第一半导体衬底上方;以及第一接合焊盘,位于第一半导体衬底上方并且物理连接至第一半导体衬底,其中,第一接合焊盘延伸至第一介电层中;以及第二管芯,位于第一管芯上方,第二管芯包括:第二半导体衬底;第二介电层,位于第一半导体衬底下面,其中,第二介电层接合至第一介电层;以及第二接合焊盘,位于第二半导体衬底下面,其中,第二接合焊盘延伸至第二介电层中,并且第二接合焊盘接合至第一接合焊盘。在实施例中,第二接合焊盘物理接触第二半导体衬底。
在实施例中,第二管芯还包括位于第二介电层上方并且接触第二介电层的额外介电层,其中,第二接合焊盘是包括接触额外介电层的底面的顶面的浅接合焊盘。在实施例中,第二接合焊盘由介电材料完全包围。在实施例中,第一管芯是没有有源器件和无源器件的伪管芯。在实施例中,第一管芯还包括位于第一半导体衬底上的集成电路。在实施例中,封装件还包括:通孔,穿透第一半导体衬底,其中,第一接合焊盘还与通孔物理接触。
根据本发明的一些实施例,封装件包括:第一管芯,包括:第一半导体衬底;集成电路,位于第一半导体衬底的正面上方和正面上;多个介电层,位于第一半导体衬底的正面上方和正面上;第一深接合焊盘,穿透多个介电层;以及第一有源接合焊盘,位于多个介电层的第一顶面层中,其中,第一有源接合焊盘包括与第一深接合焊盘的第二顶面和第一有源接合焊盘的第三顶面共面的第一顶面。在实施例中,封装件还包括:第二管芯,位于第一管芯上方,其中,第二管芯包括:第二半导体衬底;第二深接合焊盘,接触第二半导体衬底,其中,第二深接合焊盘接合至第一深接合焊盘并且物理接触第一深接合焊盘;以及第二有源接合焊盘,接合至第一有源接合焊盘。在实施例中,封装件还包括:第二管芯,位于第一管芯上方,其中,第二管芯包括:第二半导体衬底;浅接合焊盘,接合至第一深接合焊盘并且物理接触第一深接合焊盘,其中,浅接合焊盘通过至少一个介电层与第二半导体衬底物理分隔开;以及第二有源接合焊盘,接合至第一有源接合焊盘。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于执行与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成封装件的方法,包括:
在第一晶圆上形成第一介电层,其中,所述第一晶圆包括第一半导体衬底;
形成穿透所述第一介电层的第一接合焊盘,其中,所述第一接合焊盘与所述第一半导体衬底的第一表面接触;
在第二晶圆上形成第二介电层,其中,所述第二晶圆包括第二半导体衬底;
形成延伸至所述第二介电层中的第二接合焊盘;
将所述第一晶圆锯切成多个管芯,其中,所述第一接合焊盘位于所述多个管芯中的第一管芯中;以及
将所述第一接合焊盘接合至所述第二接合焊盘。
2.根据权利要求1所述的方法,还包括:通过熔融接合将所述第一介电层接合至所述第二介电层。
3.根据权利要求1所述的方法,其中,所述第二接合焊盘物理接触所述第二半导体衬底。
4.根据权利要求1所述的方法,其中,在所述第一半导体衬底上方形成第一多个介电层,所述第一介电层是所述第一多个介电层的表面层,并且其中,所述第一接合焊盘穿透所述第一多个介电层的每个。
5.根据权利要求4所述的方法,还包括:
在所述第一半导体衬底的正面上形成集成电路;以及
在所述第一介电层中形成有源接合焊盘,其中,所述有源接合焊盘电连接至所述集成电路。
6.根据权利要求5所述的方法,其中,所述第一接合焊盘和所述第一介电层形成在所述第一管芯的所述正面上。
7.根据权利要求5所述的方法,其中,所述第一接合焊盘形成在所述第一管芯的背面上,并且其中,所述背面与所述正面相对。
8.根据权利要求4所述的方法,还包括:
在所述第一介电层中形成浅接合焊盘,其中,所述浅接合焊盘电浮置。
9.一种封装件,包括:
第一管芯,包括:
第一半导体衬底;
第一介电层,位于所述第一半导体衬底上方;以及
第一接合焊盘,位于所述第一半导体衬底上方并且物理连接至所述第一半导体衬底,其中,所述第一接合焊盘延伸至所述第一介电层中;以及
第二管芯,位于所述第一管芯上方,所述第二管芯包括:
第二半导体衬底;
第二介电层,位于所述第一半导体衬底下面,其中,所述第二介电层接合至所述第一介电层;以及
第二接合焊盘,位于所述第二半导体衬底下面,其中,所述第二接合焊盘延伸至所述第二介电层中,并且所述第二接合焊盘接合至所述第一接合焊盘。
10.一种封装件,包括:
第一管芯,包括:
第一半导体衬底;
集成电路,位于所述第一半导体衬底的正面上方和正面上;
多个介电层,位于所述第一半导体衬底的所述正面上方和正面上;
第一深接合焊盘,穿透所述多个介电层;以及
第一有源接合焊盘,位于所述多个介电层的第一顶面层中,其中,所述第一有源接合焊盘包括与所述第一深接合焊盘的第二顶面和所述第一有源接合焊盘的第三顶面共面的第一顶面。
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