TWI830178B - 具有深接合墊的封裝及其形成方法 - Google Patents
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- TWI830178B TWI830178B TW111110295A TW111110295A TWI830178B TW I830178 B TWI830178 B TW I830178B TW 111110295 A TW111110295 A TW 111110295A TW 111110295 A TW111110295 A TW 111110295A TW I830178 B TWI830178 B TW I830178B
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- bonding pad
- semiconductor substrate
- die
- dielectric layer
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Abstract
一種封裝的形成方法包括在第一晶圓上形成第一介電
層,以及形成貫穿第一介電層的第一接合墊。第一晶圓包括第一半導體基底,並且第一接合墊與第一半導體基板的第一表面接觸。該方法還包括在第二晶圓上形成第二介電層以及形成延伸到第二介電層中的第二接合墊。第二晶圓包括第二半導體基底。第一晶圓被鋸切成多個晶粒,第一接合墊在該些晶粒中的第一晶粒中。第一接合墊與第二接合墊接合。
Description
本發明的實施例是有關於一種封裝及其形成方法,且特別是有關於一種具有深接合墊的封裝及其形成方法。
混合接合(hybrid bonding)是一種常見的接合方式,用於接合兩個封裝元件,如晶圓和晶粒相互連接。使用混合接合可實現高接合強度,而不增加形成接合的封裝組件的成本。
根據一些實施例,一種封裝的形成方法包括在第一晶圓上形成第一介電層,其中所述第一晶圓包括第一半導體基底;形成貫穿所述第一介電層的第一接合墊,其中所述第一接合墊與所述第一半導體基底的第一表面接觸;在第二晶圓上形成第二介電層,其中所述第二晶圓包括第二半導體基底;形成延伸到所述第二介電層中的第二接合墊;將所述第一晶圓鋸切成多個晶粒,所述第一接合墊在所述晶粒中的第一晶粒中;以及將所述第一接合墊接合到所述第二接合墊。
根據一些實施例,一種封裝包括第一晶粒以及在所述第
一晶粒之上的第二晶粒。第一晶粒包括第一半導體基底、在所述第一半導體基底之上的第一介電層及在所述第一半導體基底之上並物理連接到所述第一半導體基底的第一接合墊,其中所述第一接合墊延伸到所述第一介電層中。第二晶粒包括第二半導體基底、在所述第二半導體基底之下的第二介電層以及在所述第二半導體基底之下的第二接合墊,所述第二介電層與所述第一介電層接合,所述第二接合墊延伸到所述第二介電層中,並且所述第二接合墊與所述第一接合墊接合。
根據一些實施例,一種封裝包括第一半導體基底、在所述第一半導體基底的前側之上的積體電路、在所述第一半導體基底的所述前側之上的多個介電層、貫穿所述介電層的第一深接合墊以及在所述多個介電層的第一頂面層中的第一主動接合墊,其中所述第一主動接合墊包括第一頂面,所述第一頂面與所述第一深接合墊的第二頂面共面。
2、2-1’、2-1”、2-2’、2-2”:晶圓
4:晶片(晶粒)
4-1、4-1’、4-1”、4-2、4-2’、4-2A、4-2B、4-2C、4-2”、4-3、4-n:裝置晶粒
4-C:虛設晶粒
5:半導體基底
6:穿孔
8:積體電路裝置
10:層間介電質(ILD)
12:接觸插栓
16:內連線結構
17:前側內連線結構
18:金屬線
20:通孔
22、24A、24B、38、42:介電層
24、44:表面介電層
26、28、34、34A、34B:開口
30、45:主動接合墊
32、47:淺接合墊
33:被動裝置
36、36A、36B、48、48A、48B:深接合墊
40:背側重分佈線(重佈線路層)
46、64、64A、64B、64C、64D:接合墊
50:切割道
52:封裝
54:包封體
58:電性連接件
60-1、60-2、60-3、60-4、60-5、60-6、60-7:接合結構
66、68:箭頭
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224:製程
D1:深度
W1、W2:寬度
W3、W3’、W4、W4’、W5、W5’:側向尺寸
當結合圖式閱讀時,自以下詳細描述最佳地理解本揭露內容的態樣。應注意,根據業界中的標準慣例,各種特徵未按比例繪製。事實上,出於論述清楚起見,可任意地增加或減小各種特徵的尺寸。
圖1-9示出了根據一些實施例的形成晶粒的中間階段的剖視圖。
圖10-14示出了根據一些實施例使用圖1-9中所示的製程來形成的一些晶粒的剖視圖。
圖15示出了根據一些實施例的藉由混合接合所形成的晶粒疊層。
圖16和17示出了根據一些實施例的接合晶粒。
圖18-21示出了根據一些實施例的一些接合墊的俯視圖。
圖22示出了根據一些實施例的形成封裝的製程流程。
以下揭露內容提供諸多不同的實施例或實例,用於實施本揭露的不同特徵。下文闡述構件及排列的具體實例以簡化本揭露。當然,這些僅為範例,其目的不在於限制本揭露範圍。舉例而言,在以下說明中第一特徵形成於第二特徵「之上」或形成於第二特徵「上」,可包括第一特徵與第二特徵被形成為直接接觸的實施例,亦可包括第一特徵與第二特徵之間形成有額外特徵使得所述第一特徵與所述第二特徵不直接接觸的實施例。另外,本揭露可在各個範例中重複使用元件編號及/或字母。這樣的重複是為了簡化及清晰描述本揭露,而非用以限定各種實施例及/或配置之間的關係。
此外,為了方便說明,本文中可能使用例如「位於...之下」、「位於...下方」、「下部的」、「位於...上方」、「上部的」等空間相對性用語來描述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除了圖中所繪示的定向之外,所述空間相對性用語亦涵蓋裝置在使用或操作中的不同定向。設備可以具有其他定向(旋轉90度或處於其他定向),其所使用的空間相對性描述語亦可用同樣的方式解讀。
提供包括深接合墊的裝置晶粒及其形成方法。示出了包括接合的裝置晶粒的封裝。深接合墊可延伸到對應的裝置晶粒的半導體基底。隨著深接合墊的形成,所得的封裝的散熱得到改善並且接合更加可靠。深接合墊可與介電層的接合一起使用來實現混合接合。深接合墊也可與淺接合墊及/或主動金屬墊一起使用,本文所討論的實施例是為了提供示例以實現或使用本公開的主題,並且該發明所屬技術領域中具有通常知識者將容易理解可在保持在不同實施例的預期範圍內的同時進行修改。在各個視圖和說明性的實施例中,相同的附圖標號用於表示相同的元件。儘管可將所討論的方法實施例按特定的順序執行,但其他方法實施例可按任何邏輯順序執行。
圖1至圖9示出了根據本公開的一些實施例形成晶圓和晶粒的中間階段的剖視圖。相應的製程也示意性地反應在製程流程200中,如圖22所示。
圖1示出了在晶圓2中形成積體電路和穿孔的剖視圖。如圖22所示,相應的製程在製程流程200中示出為製程202。根據本公開的一些實施例,晶圓2是裝置晶圓,其包括主動裝置(例如電晶體及/或二極體)及/或被動裝置(例如電容器、電感器、電阻器等)。根據替代的實施例,晶圓2是不具有主動裝置的虛設晶圓。裝置晶圓2可在其中包括多個相同的晶片4,其中示出了晶片4中的一者。晶片4在下文中也被稱為(裝置)晶粒。
晶粒4可從各種類型的裝置晶粒中選擇。根據本發明的一些實施例,裝置晶粒4為邏輯晶粒,其可以是中央處理器(Central Processing Unit,CPU)晶粒、圖形處理器(Graphics Processing
Unit,GPU)晶粒、微控制單元(Micro Control Unit,MCU)晶粒、基頻帶(Base Band,BB)晶粒、應用處理器(Application processor,AP)晶粒等。根據替代的實施例,晶粒4是記憶體晶粒,其可以是靜態隨機存取記憶體(Static Random Access Memory,SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)晶粒、電阻隨機存取記憶體(Resistive Random Access Memory,RRAM)晶粒等。根據又一替代的實施例,晶粒4是類比晶粒或虛設晶粒。當為虛設晶粒時,晶粒4不含主動裝置(如電晶體和二極體)及/或被動晶粒(如電容器、電阻器、電感器等)。
根據本公開的一些實施例,晶圓2包括半導體基底5。半導體基底5可由結晶矽、結晶鍺、結晶矽鍺或諸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等的三-五(III-V)族化合物半導體來形成。半導體基底5還可以是塊狀矽基底或絕緣體上矽(Silicon-On-Insulator,SOI)基底。可在半導體基底5中形成淺溝槽隔離(Shallow Trench Isolation,STI)區(未顯示)以隔離半導體基底5中的主動區。
根據一些實施例,穿孔6(有時也稱為矽穿孔或半導體穿孔)形成為延伸到半導體基底5。穿孔6可由金屬材料形成或包括金屬材料(例如銅、鎳、鎢等)。隔離層(未示出)圍繞穿孔6形成並且將穿孔6與半導體基底5電性隔離。穿孔6形成為延伸到半導體基底5的頂面和底面之間的中間水平。穿孔6中的一者繪示為虛線以表示它可能會或可能不會形成。穿孔6可有不同的尺寸。舉例來說,一些穿孔6(可用於導熱)的寬度(或直徑)W1
大於一些其他穿孔6(可用於路由電訊號)的寬度W2。根據替代的實施例,其中裝置晶粒4沒有穿孔。
根據本公開的一些實施例,裝置晶粒4是主動晶粒,其包括形成在半導體基底5的頂面上的積體電路裝置8。積體電路裝置8的例子可包括諸如互補金屬氧化物半導體(Complementary Metal-Oxide Semiconductor,CMOS)電晶體和二極體的主動裝置,以及諸如電阻器、電容器、電感器等的被動裝置。積體電路裝置8的細節在此不再贅述。根據替代的實施例,裝置晶粒4是其中沒有主動裝置和被動裝置的虛設晶粒。
圖2示出了前側內連線結構17的形成。如圖22所示,相應的製程在製程流程200中顯示為製程204。層間介電質(Inter-Layer Dielectric,ILD)10形成在半導體基底5上方並填滿在積體電路裝置8中的電晶體(未示出)的閘極疊層之間的空間。根據一些示例實施例,ILD10由氧化矽、磷矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、摻硼磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、摻氟矽酸鹽玻璃(Fluorine-Doped Silicate Glass,FSG)或類似者。ILD10可使用旋塗、可流動化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)、化學氣相沉積(Chemical Vapor Deposition,CVD)、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition,PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition,LPCVD)等方式形成。
接觸插栓12形成在ILD10中並用於將積體電路裝置8和穿孔6電性連接到上覆的金屬線和通孔。根據本公開的一些實施
例,接觸插栓12由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、合金及/或其多層的導電材料形成。接觸插栓12的形成可包括在ILD10中形成接點開口,將一或多種導電材料填入到接點開口中,以及執行平坦化(例如化學機械拋光(Chemical Mechanical Polish,CMP)製程)以使接觸插栓12的頂面與ILD10的頂面齊平。
在ILD10和接觸插栓12上形成內連線結構16。內連線結構16包括介電層22、金屬線(和接墊)18和介電層22中的通孔20。在下文中,介電層22替代地被稱為金屬間介電(Inter-Metal Dielectric,IMD)層22。根據本公開的一些實施例,一些或全部的介電層22由具有低於約3.0或約2.5的介電常數值(k值)的低k電介質材料形成。介電層22可由含碳的低k介電質材料、氫矽氧氟烷(Hydrogen Silses-Quioxane,HSQ)、甲基矽氧矽氧烷(Methy-Silses-Quioxane,MSQ)等形成。根據本發明的一些實施例,介電層22的形成包括沉積含致孔劑的介電材料,然後進行固化製程以除去致孔劑,因此剩餘的介電層22是多孔的。根據本公開的替代實施例,一些或全部的介電層22由非低k電介質材料形成,例如氧化矽、碳化矽(SiC)、碳氮化矽(SiCN)、矽氧碳氮化物(SiOCN)等。可由氧氮化矽、氧化鋁、氮化鋁等或其組合形成的蝕刻停止層(未示出)可形成在IMD介電層22之間,並且為了簡單起見並未示出。
金屬線18和通孔20形成在介電層22中。以下將同一層級的金屬線18統稱為金屬層。根據本公開的一些實施例,內連線結構16包括互連通孔20的多個金屬層。金屬線18和通孔20可
由銅或銅合金形成,也可以由其他金屬形成。形成製程可包括單鑲嵌和雙鑲嵌製程。在示例的單鑲嵌製程中,溝渠是先形成在介電層22中的一者中,然後用導電材料填滿溝渠。然後執行平坦化製程(例如CMP製程)以去除高於IMD層的頂面的導電材料的多餘部分,以在溝渠中留下金屬線。在雙鑲嵌製程中,溝渠和通孔開口都形成在IMD層中,通孔開口下伏且連接到溝渠。然後將導電材料填充到溝渠和通孔開口中,以分別形成金屬線和通孔。導電材料可包括擴散阻擋層和擴散阻擋層之上的含銅金屬材料。擴散阻擋層可包括鈦、氮化鈦、鉭、氮化鉭等。
參照圖3,根據本公開的一些實施例沉積表面介電層24。如圖22所示,相應的製程在製程流程200中顯示為製程206。表面介電層24由非低k電介質材料形成,並可與下面的介電層22物理接觸,或者藉由諸如蝕刻停止層的其他層與介電層22分開。表面介電層24可以是氧化矽基的介電材料,其包括矽和另一種元素(包括氧、氮、碳、或類似者或其組合)。舉例來說,表面介電層24可由以下來形成或可包括以下:氧化矽、氮氧化矽(SiON)、氮化矽(SiN)、氮氧化矽(SiON)、矽氧碳氮化物(SiOCN)、碳氮化矽(SiCN)、碳氧化矽(SiOC)、碳化矽(SiC)或類似者。
藉由蝕刻製程在表面介電層24中形成開口26和28。在形成開口26的過程中,金屬線18中的金屬墊/頂部金屬化層中的接墊被用作蝕刻停止層,並且金屬墊被暴露出來。在形成開口28的過程中,下伏的介電層用作蝕刻停止層,並被開口28暴露出來。儘管未示出,開口26可包括通孔開口和通孔開口之上的溝渠,其用於形成雙鑲嵌結構。
參照圖4,形成主動接合墊30和淺接合墊32。如圖22所示,相應的製程在製程流程200中顯示為製程208。淺接合墊32是虛設接合墊,在最終封裝中是電性浮置的。形成製程可包括沉積共形阻障層(使用諸如TiN、TaN、Ti、Ta等的導電材料)、沉積諸如銅、鎢、鈷等的金屬材料、以及執行平坦化製程以去除多餘的材料。
圖4進一步示出了藉由多個蝕刻製程形成開口34(包括開口34A和34B)。如圖22所示,相應的製程在製程流程200中顯示為製程210。多個蝕刻製程可以響應於介電層22、ILD10和蝕刻停止層的不同材料而採用不同的蝕刻氣體。半導體基底5中的頂面被開口34A暴露出來。半導體基底5的頂面和穿孔6之一的頂面(若有形成)被開口34B暴露出來。根據一些實施例,開口34具有與半導體基底5的頂面齊平或基本上齊平的底面。根據替代的實施例,開口34延伸到半導體基底5中以形成具有深度D1的凹槽,其可大於約10埃。深度D1也可在約10埃和約100埃之間的範圍內。虛線代表凹槽的相應底部和側壁。
參照圖5,形成深接合墊36(包括36A和36B)。如圖22所示,相應的製程在製程流程200中顯示為製程212。形成製程還可包括沉積共形阻障層(例如TiN、TaN、Ti、Ta等)、沉積金屬材料(例如銅、鎢、鈷等)以及進行平坦化製程以去除多餘的材料。所得的深接合墊36A的整個底面與半導體基底5的頂面接觸。此外,深接合墊36A的側壁可不連接到任何其他的導電特徵(例如金屬特徵)。另一方面,深接合墊36B電性連接到下伏的穿孔6。可理解的是,使用虛線來說明對應的穿孔6以代表它可形成也可
不形成。深接合墊36可具有從表面介電層24的頂面延伸到半導體基底5的頂面的豎直側壁。
接著,如圖6所示,對半導體基底5的背側(所示出的底側)進行背側研磨製程,以去除半導體基底5的一部分,直到顯露出穿孔6。如圖22所示,相應的製程在製程流程200中顯示為製程214。然後,半導體基底5從背側略微凹陷(例如藉由蝕刻),使得穿孔6從半導體基底5的背面(所示出的底面)突出。
根據替代的實施例,不形成穿孔6,並且跳過對晶圓2的背側執行的製程(如圖6至9所示)。
接下來,同樣如圖6所示,沉積介電層38,然後進行CMP製程或機械研磨製程以重新暴露出穿孔6。如圖22所示,相應的製程在製程流程200中顯示為製程216。因此,穿孔6也穿透了介電層38。根據一些實施例,介電層38由氧化矽、氮化矽、氮氧化矽、碳氮化矽等來形成。
參照圖7,可形成背側重分佈線(重佈線路層)40,其包括接觸穿孔6的接墊部分。如圖22所示,相應的製程在製程流程200中顯示為製程218。根據一些實施例,重佈線路層40可由鋁、銅、鎳、鈦等形成。可形成介電層42,其中重佈線路層40延伸到介電層42。雖然形成了一層介電層42和一層重佈線路層40作為示例,但是根據佈線需求,可形成多個介電層和多個重佈線路層。
圖8進一步示出了主動接合墊45、淺接合墊47和接合墊46的形成。如圖22所示,相應的製程在製程流程200中顯示為製程220。主動接合墊45電性連接到穿孔6,其進一步連接到積體電路8及/或主動接合墊30。接合墊46電性連接到穿孔6和深接
合墊36B。淺接合墊47是虛設接合墊,在最後的封裝中是電性浮置的,每個淺接合墊47都被介電材料完全包圍。根據一些實施例,接合墊46由以下形成或包括以下:氮化鈦、銅、鎢等、其多層及/或其合金。
根據一些實施例,在表面介電層44中形成接合墊46,其可包括或可由氧化矽、SiN、SiC、SiOC、SiON、SiOCN等形成。接合墊46的底面可與表面介電層44的底面共面。
圖9示出了深接合墊48A的形成。如圖22所示,相應的製程在製程流程200中顯示為製程222。根據一些實施例,深接合墊48A的形成包括蝕刻介電層38、42和44以在半導體基底5的背側形成開口,使得半導體基底5的背面(所示出的底面)被開口暴露出來、用導電材料填充開口以及執行平坦化製程。深接合墊48A中的導電材料可從用於形成深接合墊36A的同一組候選材料中選出。根據這些實施例,深接合墊48A可以藉由半導體基底5與深接合墊36A熱連接,以形成導熱通道。
根據替代的實施例,代替形成接合墊46和重佈線路層40以連接到穿孔6和深接合墊36B,使用虛線示出的深接合墊48B形成在半導體基底的背側上。深接合墊48B可與深接合墊48A同時形成。因此,深接合墊36B和48B以及對應的穿孔6形成導熱通道。
根據一些實施例,深接合墊36的側向尺寸W3和深接合墊48的側向尺寸W3’大於主動接合墊30的側向尺寸W4和主動接合墊45的側向尺寸W4’。相應地,提高了導熱路徑的導熱效率,同時可形成更多的訊號路徑。側向尺寸W3和W3’也可等於或大
於淺接合墊32的側向尺寸W5和淺接合墊47的側向尺寸W5’。
在隨後的製程中,晶圓2可藉由沿切割道50的鋸切製程被分割,並且裝置晶粒4彼此分離。如圖22所示,相應的製程在製程流程200中顯示為製程224。
裝置晶粒4可包括四種類型的接合墊,其包括主動接合墊30、(虛設)淺接合墊32、深接合墊36A和深接合墊36B的任意組合,這意味著在一個晶粒中,一、二、三或所有四種類型的接合墊可任意組合形成在裝置晶粒4的同一側。接合墊的這些組合可形成在前側(或稱為主動側)、背側或半導體基底5的前側和背側兩者上。在整個描述中,具有主動積體電路8的半導體基底5的一側稱為主動側或前側,而相反側稱為非主動側或背側。當形成在背側上時,裝置晶粒4可包括一、二、三或四種類型的主動接合墊45、淺接合墊47、接合墊46和深接合墊48的任意組合。
此外,裝置晶粒4可包括積體電路8,其可包括主動裝置,也可包括或不包括被動裝置。對應的裝置晶粒4就是主動裝置晶粒。根據替代的實施例,裝置晶粒4包括被動裝置且不包括主動裝置。根據又一替代實施例,裝置晶粒4不含主動裝置和被動裝置。在這種情況下,裝置晶粒4是虛設晶粒。一些示例的虛設晶粒4如圖13、14和15所示。
在一些裝置晶粒4中,形成穿孔6並在各個裝置晶粒4的前側和背側上都形成接合墊。所得的裝置晶粒4稱為雙側裝置晶粒,一些示例如圖10、11和13-15所示。在一些其他的裝置晶粒4中,不形成穿孔6,並且跳過對晶圓2的背側進行的製程(如圖6-9所示)。所得的裝置晶粒4是單側的,單側裝置晶粒4的示
例如圖12和15所示。
圖10到14示出了一些示例裝置晶粒4,其可使用參照圖1到9所討論的製程來形成。示例的裝置晶粒4堆疊形成封裝,如圖15所示。與這些實施例一致的裝置晶粒4具有不同的特徵組合,如上文所述。應當理解的是,同樣如前所述,還可採用任何其他組合來形成不同的裝置晶粒,這也在本揭露的範圍內。這些圖中的裝置晶粒的細節(如介電層、金屬線、通孔、重佈線路層等)均未示出,細節可參考之前所討論的實施例。
圖10示出了根據一些實施例的雙側裝置晶粒4(也表示為4-3)。對應的裝置晶粒4所示出的底側可以是前側,各個積體電路8位在實線所示的位置處。根據替代的實施例,對應的裝置晶粒4所示出的頂側可以是前側,並且各個積體電路8位在虛線所示的位置處。
在圖11中,對應的裝置晶粒4(也表示為4-2A)所示出的頂側可以是前側,並且還示出了虛線框以顯示圖示的底側可替代地是各個裝置晶粒4的前側。被動裝置33也被示意性地示出。
圖12示出了根據一些實施例的單側裝置晶粒4(也表示為4-1)。圖示了深接合墊36。還示出了一些淺接合墊32。淺接合墊32中的一者下面的虛線(標記為36)表示這些淺接合墊也可形成為深接合墊,在圖15中用於顯示深接合墊36也可以用作與積體電路8的電性連接。
圖13和14示出了一些示例虛設晶粒4,其不具有主動裝置和被動裝置。圖13示出了虛設晶粒,其中背側特徵(例如接合墊46和深接合墊48)顯示為虛線,表示虛設晶粒4可以是雙側的
或單側的。圖14示出了一個雙側虛設晶粒4(也表示為4-2B)的例子,其中包括如圖13所示的部分特徵。穿孔6使用虛線示出,以說明穿孔可形成也可不形成。當有形成時,這些穿孔以及上覆和下伏的深接合墊36和48可用作電性連接或導熱路徑,以互連上覆的晶粒和下伏的晶粒。未連接任何穿孔的接合墊36A(圖13)用作導熱通道。根據一些實施例,在裝置晶粒的前側上,有一個由均質介電材料形成的表面介電層24,深(虛設)接合墊36A和36B貫穿單一的表面介電層24。根據替代的實施例,虛設晶粒4的前側上有兩個介電層24A和24B,淺接合墊32在上部介電層24B。在基板5的背側上,也可有一個介電層或兩個介電層。
圖15示出了由接合多個層的裝置晶粒4所形成的封裝52,如圖10-12和14所示。為了區分在封裝52中的裝置晶粒,可在每個裝置晶粒4後面加上一個連接號“-”和一個層數來表示裝置晶粒的層數。可有“n”層的裝置晶粒4堆疊,整數n可以是2、3、4、5或更多。此外,在同一層中,使用字母A、B、C等來區分裝置晶粒4。舉例來說,在封裝52中,第二層裝置晶粒包括主動裝置晶粒4-2A和虛設晶粒4-2B和4-C。包封體54可以是模塑化合物、模塑底部填充物等,並可用於填充相鄰的裝置晶粒4之間的間隙。所示出的裝置晶粒4的例子除了包括積體電路8之外,還可包括被動裝置33。接合的裝置晶粒包括主動裝置晶粒4-1、4-2A、4-3和4-n。此外,雙側虛設裝置晶粒4-2B和單側虛設裝置晶粒4-2C也接合在晶粒堆疊中。
根據一些實施例,電性連接件58可以是焊料區、金屬柱、接合墊等並形成在頂部裝置晶粒4-n的頂面上。根據一些實施例,
底部裝置晶粒4-1在其底面處沒有電性連接件,並且在其中不具有穿孔。在主動裝置晶粒4-1、4-2A、4-3的每一個中都有一個實心框標示出積體電路8的位置,也標示出對應的裝置晶粒4的哪一邊是前側。在裝置晶粒4-2A和4-2的每一個中也有一個虛線框來表示替代的實施例,其中積體電路8不是在實心框所在的地方形成,而是在虛線框所在的地方形成。因此,圖15示出了前側對前側接合、背側對背側接合和前側對背側接合方案,其具體取決於積體電路8的位置。
根據一些實施例,裝置晶粒4之間的接合是藉由混合接合,其中包括接合的金屬接墊到金屬接墊藉由直接金屬對金屬的接合,以及表面介電層的熔融接合(fusion bonding)。舉例來說,一個裝置晶粒4或虛設晶粒4(4-2B或4-2C)中的深接合墊36(參見圖9)和淺接合墊32中的每一個可藉由金屬對金屬接合與深接合墊36和48以及淺接合墊32和47中的任何一個接合。每個主動接合墊30(參見圖9)都可連接到另一個裝置晶粒中的主動接合墊30或45。表面介電層24(圖9)可與相鄰的晶粒中的表面介電層24或表面介電層44接合,產生Si-O-Si鍵。
一些示例的接合方案簡要討論如下。可以理解的是,裝置晶粒4中的每一個的前側和背側也可被翻轉,如前所述。因此,所示出的前側接合墊可替代地是背側接合墊,反之亦然。接合結構60-1代表第一裝置晶粒4-1中的深接合墊36與第二裝置晶粒4-2A中的深接合墊48的接合。接合結構60-2代表第一裝置晶粒4-2A中的深接合墊36與第三裝置晶粒4-3中的深接合墊36的接合。
接合結構60-3代表第一裝置晶粒4-3中的深接合墊36與第二裝置晶粒4-2A中的淺接合墊32的接合。接合結構60-1、60-2、60-3與對應的裝置晶粒4的半導體基底5電性連接。接合結構60-4代表第一裝置晶粒4-3中的淺接合墊(例如圖10中的接合墊32)與第二裝置晶粒4-2A中的淺接合墊32的接合。接合結構60-4是電性浮置的。接合結構60-5和60-6代表相鄰的裝置晶粒4中的主動接合墊(例如接合墊30及/或45)中的接合,使相鄰的裝置晶粒中的積體電路電性互連。
虛設晶粒4-2B和4-2C沒有主動裝置和被動裝置,可用來填補比較小的裝置晶粒4-2A所留下來的空間。虛設晶粒4-2B是雙側虛設晶粒,對應的半導體基底5的一側或兩側有深(虛設)接合墊。當形成穿孔6時,對應的接合墊既可以是沒有電性功能的虛設接合墊,也可作為裝置晶粒4-1與裝置晶粒4-3電性連接的訊號路徑或電源路徑(VDD或接地)。舉例來說,當深接合墊形成為接合結構60-7的一部分時,對應的深接合墊36(虛線)可用於連接到裝置晶粒4-1的半導體基底5。當虛設晶粒4-2B中未形成穿孔6時,虛設晶粒4-2B中的深接合墊可用於散熱,例如將裝置晶粒4-3中產生的熱量傳導至裝置晶粒4-1,然後傳導至下方的散熱片(未示出)。淺接合墊32及/或47也可形成在虛設晶粒4-2B中以提高接合強度。
虛設晶粒4-2C是單側晶粒,在對應的半導體基底5的一側形成深(虛設)接合墊和淺接合墊。同樣,穿孔6可形成在半導體基底5中,或者半導體基底5可不具有穿孔6。
圖16和17示出了圖15中兩個接合晶粒的一些細節。圖
16示出了根據一些實施例通過前側對背側的接合彼此接合的兩個晶圓2-1’和2-2'(及/或裝置晶粒4-1’和4-2')。裝置晶粒4-1’和4-2'可代表圖15中的兩個裝置晶粒(如裝置晶粒4-2A和4-3)。箭頭66的方向表示對應的裝置晶粒4的前側所面對的方向。在所示出的示例中,下部裝置晶粒4-1’的前側接合到上部裝置晶粒4-2’的背側。
圖17示出了根據一些實施例藉由前側對前側的接合彼此接合的兩個晶圓2-1”和2-2”(及/或裝置晶粒4-1”和4-2”)。裝置晶粒4-1’和4-2'也可代表圖15中的兩個裝置晶粒(如裝置晶粒4-2A和4-3)。箭頭68的方向表示對應的裝置晶粒4的前側所面對的方向。在所示出的示例中,下部裝置晶粒4-1”的前側接合到上部裝置晶粒4-2”的背側。
圖18-21示出了一些接合墊64與一些實施例的俯視圖。接合墊64中的每一個都可代表主動接合墊30和45(圖9)、淺接合墊32和47、接合墊46和深接合墊48中的任一個。可以理解的是,雖然以圓形和矩形為例來繪示接合墊64的俯視形狀,但也可採用其他形狀,例如六邊形、橢圓形、八邊形等。
參照圖18,接合墊64可佈置為具有諸如陣列的重複圖案。接合墊64可具有彼此相同的尺寸和形狀。參照圖19,接合墊64可佈置為具有交錯圖案,其包括彼此錯位的兩個陣列。接合墊64可具有相同的尺寸。此外,接合墊64可具有彼此相同的形狀。圖20示出了交錯排列的接合墊64,其中一個陣列中的接合墊64A的尺寸不同於另一陣列中的接合墊64B的尺寸。圖21示出了交錯排列的接合墊64,其中一個陣列中的接合墊64C具有與另一陣列
中的接合墊64D的尺寸不同的形狀。
在上面所示的實施例中,根據本公開的一些實施例討論了一些製程和特徵以形成三維(three-dimensional,3D)封裝。其他功能和製程也可包括在內。舉例來說,可包括測試結構以幫助對3D封裝或3DIC裝置進行驗證測試。測試結構可包括例如形成在重佈線層中或允許測試3D封裝或3DIC、使用探針及/或探針卡等的基板上的測試墊。驗證測試可在中間結構以及最終結構上執行。此外,本文公開的結構和方法可與結合已知良好晶粒的中間驗證的測試方法結合使用,以提高產量並降低成本。
本公開的實施例具有一些的有利特徵。藉由形成深接合墊,從一個裝置晶粒到另一個(以及到散熱件)的散熱得到改善,因為熱量可藉由這些接合墊直接傳導到半導體基底,而不通過低導熱性的介電層。由於深接合墊與相應的半導體基底的良好錨定,接合的可靠性也得到了提高。此外,淺接合墊與深接合墊和主動接合墊相結合,進一步提高了接合的可靠性。
根據本公開的一些實施例,一種方法包括:在第一晶圓上形成第一介電層,其中第一晶圓包括第一半導體基底;形成貫穿第一介電層的第一接合墊,其中第一接合墊與第一半導體基底的第一表面接觸;在第二晶圓上形成第二介電層,其中第二晶圓包括第二半導體基底;形成延伸到第二介電層中的第二接合墊;將第一晶圓鋸切成多個晶粒,且第一接合墊在該些晶粒中的第一晶粒中;以及將第一接合墊接合到第二接合墊。
在一實施例中,方法還包括藉由熔融接合將第一介電層接合到第二介電層。在一實施例中,第二接合墊物理接觸第二半
導體基底。在一實施例中,第一多個介電層形成在第一半導體基底上,第一介電層是第一多個介電層的表面層,其中第一接合墊穿透第一多個介電層中的每一個。在一實施例中,方法還包括在第一半導體基底的前側上形成積體電路;以及在第一介電層中形成主動接合墊,其中主動接合墊電性連接至積體電路。
在一實施例中,第一接合墊和第一介電層形成在第一晶粒的前側上。在一實施例中,第一接合墊形成在第一晶粒的背側上,其中背側與前側相對。在一實施例中,方法還包括在第一介電層中形成淺接合墊,其中淺接合墊是電性浮置的。在一實施例中,第二多個介電層形成在第二半導體基底上,第二介電層是第二多個介電層的表面層,其中第二接合墊具有接觸第二多個介電層中的附加介電層的頂面的底面。在一實施例中,第一晶圓中沒有主動裝置和被動裝置。
根據本公開的一些實施例,一種封裝包括包含第一半導體基底的第一晶粒;第一介電層在第一半導體基底之上;以及第一接合墊物理連接到第一半導體基底,其中第一接合墊延伸到第一介電層中;以及第二晶粒在第一晶粒之上,第二晶粒包括第二半導體基底;第二介電層在第二半導體基底之下,其中第二介電層與第一介電層接合;並且第二接合墊在第二半導體基底之下,其中第二接合墊延伸到第二介電層中,並且第二接合墊與第一接合墊接合。在一實施例中,第二接合墊物理接觸第二半導體基底。
在一實施例中,第二晶粒還包括在第二介電層之上並接觸第二介電層的附加介電層,其中第二接合墊是淺接合墊,淺接合墊包括與附加介電層的底面接觸的頂面。在一實施例中,第二
接合墊完全被介電材料包圍。在一實施例中,第一晶粒是不具有主動裝置和被動裝置的虛設晶粒。在一實施例中,第一晶粒還包括在第一半導體基底上的積體電路。在一實施例中,封裝還包括穿過第一半導體基底的穿孔,其中第一接合墊進一步與穿孔物理接觸。
根據本公開的一些實施例,一種封裝包括包含第一半導體基底的第一晶粒;積體電路在第一半導體基底的前側之上;多個介電層在第一半導體基底的前側之上;第一深接合墊貫穿多個介電層;以及第一主動接合墊在第一多個介電層的第一頂面層中,其中第一主動接合墊包括與第一深接合墊的第二頂面共面的第一頂面。在一實施例中,封裝還包括在第一晶粒之上的第二晶粒,其中第二晶粒包括第二半導體基底、與第二半導體基底接觸的第二深接合墊,其中第二深接合墊與第一深接合墊接合且物理接觸;並且第二主動接合墊接合到第一主動接合墊。在一實施例中,封裝還包括在第一晶粒之上的第二晶粒,其中第二晶粒包括第二半導體基底、與第一深接合墊接合且物理接觸的淺接合墊,其中淺接合墊與第二半導體基底物理上隔開至少一個介電層;並且第二主動接合墊接合到第一主動接合墊。
以上概略描述了幾個實施例的特徵,使得所屬技術領域中具有通常知識者可以更好地理解本揭露的各個面向。所屬技術領域中具有通常知識者應該理解的是,他們可以使用本揭露內容作為設計或修改其他製程及結構的基礎,以實現與本文說明的實施例相同的目的及/或達成相同的優點。所屬技術領域中具有通常知識者應該知道,等效的構成並不脫離本揭露的精神和範圍,因
此在不背離本揭露的精神和範圍的情況下,可以進行各種改變、替換及變更。
2:晶圓
4:晶片(晶粒)
5:半導體基底
6:穿孔
8:積體電路裝置
10:層間介電質(ILD)
12:接觸插栓
16:內連線結構
18:金屬線
20:通孔
22、38、42:介電層
24、44:表面介電層
30、45:主動接合墊
32、47:淺接合墊
36、36A、36B、48、48A、48B:深接合墊
40:背側重分佈線(重佈線路層)
46:接合墊
50:切割道
W3、W3’、W4、W4’、W5、W5’:側向尺寸
Claims (10)
- 一種封裝的形成方法,包括:在第一晶圓上形成第一介電層,其中所述第一晶圓包括第一半導體基底;形成貫穿所述第一介電層的第一接合墊和深接合墊,其中所述第一接合墊與所述第一半導體基底的第一表面接觸,所述深接合墊的整個底面與所述第一半導體基底的所述第一表面物理接觸;在第二晶圓上形成第二介電層,其中所述第二晶圓包括第二半導體基底;形成延伸到所述第二介電層中的第二接合墊;將所述第一晶圓鋸切成多個晶粒,所述第一接合墊在所述晶粒中的第一晶粒中;以及將所述第一接合墊接合到所述第二接合墊。
- 如請求項1所述的封裝的形成方法,其中所述第二接合墊物理接觸所述第二半導體基底。
- 如請求項1所述的封裝的形成方法,其中第一多個介電層形成在所述第一半導體基底之上,所述第一介電層是所述第一多個介電層的表面層,其中所述第一接合墊貫穿所述第一多個介電層中的每一個。
- 如請求項3所述的封裝的形成方法,還包括:在所述第一介電層中形成淺接合墊,其中所述淺接合墊是電性浮置的。
- 一種封裝,包括: 第一晶粒,包括:第一半導體基底;第一介電層,在所述第一半導體基底之上;深接合墊,所述深接合墊的整個底面與所述第一半導體基底的最頂部表面物理接觸;及第一接合墊,在所述第一半導體基底之上並物理連接到所述第一半導體基底的所述最頂部表面,其中所述第一接合墊延伸到所述第一介電層中;以及第二晶粒,在所述第一晶粒之上,所述第二晶粒包括:第二半導體基底;第二介電層,在所述第二半導體基底之下,其中所述第二介電層與所述第一介電層接合;以及第二接合墊,在所述第二半導體基底之下,其中所述第二接合墊延伸到所述第二介電層中,並且所述第二接合墊與所述第一接合墊接合。
- 如請求項5所述的封裝,其中所述第二接合墊被介電材料完全包圍。
- 如請求項5所述的封裝,還包括貫穿所述第一半導體基底的穿孔,其中所述第一接合墊進一步與所述穿孔物理接觸。
- 一種封裝,包括:第一晶粒,包括:第一半導體基底;積體電路,在所述第一半導體基底的前側之上;多個介電層,在所述第一半導體基底的所述前側之上; 第一深接合墊,貫穿所述介電層,所述第一深接合墊的整個底面與所述第一半導體基底的最頂部表面物理接觸;以及第一主動接合墊,在所述介電層的第一頂面層中,其中所述第一主動接合墊包括第一頂面,所述第一頂面與所述第一深接合墊的第二頂面共面。
- 如請求項8所述的封裝,還包括在所述第一晶粒之上的第二晶粒,其中所述第二晶粒包括:第二半導體基底;第二深接合墊,與所述第二半導體基底接觸,其中所述第二深接合墊與所述第一深接合墊接合且物理接觸;以及第二主動接合墊,接合至所述第一主動接合墊。
- 如請求項8所述的封裝,還包括在所述第一晶粒之上的第二晶粒,其中所述第二晶粒包括:第二半導體基底;淺接合墊,與所述第一深接合墊接合且物理接觸,其中所述淺接合墊與所述第二半導體基底物理上隔開至少一個介電層;以及第二主動接合墊,接合到所述第一主動接合墊。
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US (1) | US20230187406A1 (zh) |
KR (1) | KR20230090970A (zh) |
CN (1) | CN115881688A (zh) |
DE (1) | DE102022104263A1 (zh) |
TW (1) | TWI830178B (zh) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWM269437U (en) * | 2004-08-10 | 2005-07-01 | Luo Wen He | Cylinder gear device for electric toy gun |
CN104576637A (zh) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3d集成电路及其形成方法 |
TW201933593A (zh) * | 2017-11-21 | 2019-08-16 | 台灣積體電路製造股份有限公司 | 影像感測裝置、其形成方法及影像感測系統 |
TW202013667A (zh) * | 2018-09-19 | 2020-04-01 | 台灣積體電路製造股份有限公司 | 半導體結構、封裝結構及其製造方法 |
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US11094613B2 (en) | 2019-08-22 | 2021-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
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- 2022-02-23 DE DE102022104263.4A patent/DE102022104263A1/de active Pending
- 2022-03-21 TW TW111110295A patent/TWI830178B/zh active
- 2022-04-04 KR KR1020220041881A patent/KR20230090970A/ko not_active Application Discontinuation
- 2022-06-21 CN CN202210707612.9A patent/CN115881688A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWM269437U (en) * | 2004-08-10 | 2005-07-01 | Luo Wen He | Cylinder gear device for electric toy gun |
CN104576637A (zh) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3d集成电路及其形成方法 |
TW201933593A (zh) * | 2017-11-21 | 2019-08-16 | 台灣積體電路製造股份有限公司 | 影像感測裝置、其形成方法及影像感測系統 |
TW202013667A (zh) * | 2018-09-19 | 2020-04-01 | 台灣積體電路製造股份有限公司 | 半導體結構、封裝結構及其製造方法 |
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TW202339180A (zh) | 2023-10-01 |
US20230187406A1 (en) | 2023-06-15 |
KR20230090970A (ko) | 2023-06-22 |
DE102022104263A1 (de) | 2023-06-15 |
CN115881688A (zh) | 2023-03-31 |
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