TW201923992A - 封裝體及其製造方法 - Google Patents

封裝體及其製造方法 Download PDF

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Publication number
TW201923992A
TW201923992A TW107134148A TW107134148A TW201923992A TW 201923992 A TW201923992 A TW 201923992A TW 107134148 A TW107134148 A TW 107134148A TW 107134148 A TW107134148 A TW 107134148A TW 201923992 A TW201923992 A TW 201923992A
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Taiwan
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device die
die
passive
passive device
dielectric layer
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TW107134148A
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TWI676242B (zh
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胡致嘉
陳明發
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括將第一裝置晶粒與第二裝置晶粒接合在一起。第二裝置晶粒位於第一裝置晶粒上方。被動裝置形成於包括第一裝置晶粒以及第二裝置晶粒的組合的結構中。被動裝置包括第一末端以及第二末端。於第一裝置晶粒上方形成間隙填充材料，其中間隙填充材料包括第二裝置晶粒的相對側上的部分。方法還包括：進行平坦化以暴露出第二裝置晶粒，其中間隙填充材料的剩餘部分形成隔離區；形成貫穿隔離區的第一穿孔以及第二穿孔以電耦接至第一裝置晶粒；以及形成第一電連接件以及第二電連接件，以電耦接至被動裝置的第一末端以及第二末端。

Description

整合封裝結構中的被動裝置
由於將更多的裝置晶粒封裝於同一封裝體中以達成更多的功能，因此積體電路的封裝體變得愈來愈複雜。舉例而言，封裝結構已被開發成在同一封裝體中包括多個裝置晶粒（例如，處理器以及記憶體立方體）。封裝結構可包括使用不同技術所形成的裝置晶粒，且具有接合至同一裝置晶粒的不同功能，從而形成系統。此可節省製造成本並優化裝置效能。
以下揭露內容提供用於實施所提供的目標的不同特徵的許多不同實施例或實例。以下所描述構件與配置的具體實例來簡化本揭露。當然，這些僅僅是示例，而非用以限制。舉例而言，在以下的描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，並且還可以包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件標號及/或字母。元件標號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，如「在...下方」、「下面」、「下部」、「在...上方」、「上部」等空間相對術語來闡述圖中所示的一個元件或特徵與另一（些）元件或特徵的關係。除圖式中所描繪之定向以外，空間相對術語意欲涵蓋裝置或設備在使用或操作中之不同定向。裝置或設備可以其他方式定向（旋轉90度或位於其他定向），且本文中所使用之空間相對描述詞可同樣相應地進行解釋。
根據各種例示性實施例提供封裝體以及其形成方法。根據一些實施例繪示出形成封裝體的中間階段。一些實施例的一些變化型亦被討論。在各視圖以及說明性實施例中，相同的元件標號用以表示相同元件。
圖1至圖10繪示出根據本發明的一些實施例的在封裝體的形成中的中間階段的橫截面圖。圖1至圖10中所示的步驟亦示意性地反映在圖21中所示的製程流程200中。
圖1繪示出封裝組件2的形成的橫截面圖。根據本發明的一些實施例，封裝組件2為裝置晶圓，其包括例如電晶體及/或二極體的主動裝置（或積體電路裝置）22，且可能包括諸如電容器、電感器、電阻器或其類似者的被動裝置。封裝組件2可包括多個晶片4於其中，以下說明晶片4中的一個。晶片4在下文中被替代地稱作（裝置）晶粒。根據本發明的一些實施例，裝置晶粒4為邏輯晶粒，其可以是中央處理單元（Central Processing Unit，CPU）晶粒、微控制單元（Micro Control Unit，MCU）晶粒、輸入-輸出（input-output，IO）晶粒、基頻（BaseBand，BB）晶粒、應用處理器（Application processor，AP）晶粒或其類似者。裝置晶粒4亦可為記憶體晶粒，例如動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）晶粒或靜態隨機存取記憶體（Static Random Access Memory，SRAM）晶粒，或可為其他類型的晶粒。在後續論述中，裝置晶圓被論述為例示性封裝組件2。本發明的實施例亦可應用於其他類型的封裝組件，例如中介件晶圓（interposer wafers）。
根據本發明的一些實施例，例示性晶圓2包括半導體基底20，以及形成於半導體基底20的頂表面處的特徵。半導體基底20可由結晶矽、結晶鍺、結晶矽鍺及/或III-V族化合物半導體形成，所述III-V族化合物半導體例如是GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或類似者。半導體基底20亦可以是塊狀矽基底或絕緣層上矽（Silicon-On-Insulator，SOI）基底。淺溝渠隔離（Shallow Trench Isolation，STI）區（未繪示）可形成於半導體基底20中，以隔離半導體基底20中的主動區。儘管未繪示，但穿孔可形成為延伸至半導體基底20中，且穿孔用以將晶圓2的相對側上的特徵相互電耦接。
根據本發明的一些實施例，晶圓2包括積體電路裝置22，其形成於半導體基底20的頂表面上。例示性積體電路裝置22可包括互補金屬氧化物半導體（Complementary Metal-Oxide Semiconductor，CMOS）電晶體、電阻器、電容器、二極體及/或其類似者。本文中並不贅述積體電路裝置22的細節。根據替代實施例，晶圓2用於形成中介件，其中基底20可為半導體基底或介電基底。
層間介電質（Inter-Layer Dielectric，ILD）24形成於半導體基底20上方，且填入積體電路裝置22中的電晶體（未繪示）的閘極堆疊之間的空間。根據一些例示性實施例，ILD 24由磷矽酸鹽玻璃（Phospho Silicate Glass，PSG）、硼矽酸鹽玻璃（Boro Silicate Glass，BSG）、硼摻雜磷矽酸鹽玻璃（Boron-Doped Phospho Silicate Glass，BPSG）、氟摻雜矽酸鹽玻璃（Fluorine-Doped Silicate Glass，FSG）、四乙氧基矽烷（Tetra Ethyl Ortho Silicate，TEOS）或其類似者形成。ILD 24可使用旋塗法、可流動化學氣相沈積法（Flowable Chemical Vapor Deposition，FCVD）、化學氣相沈積法（Chemical Vapor Deposition，CVD）、電漿增強式化學氣相沈積法（Plasma Enhanced Chemical Vapor Deposition，PECVD）、低壓化學氣相沈積法（Low Pressure Chemical Vapor Deposition，LPCVD）或其類似方法來形成。
接觸插塞28形成於ILD 24中，且用以將積體電路裝置22電連接至上覆金屬線34以及通孔36。根據本發明的一些實施例，接觸插塞28由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金及/或其多層的導電材料形成。接觸插塞28的形成可包括在ILD 24中形成接觸開口、將導電材料填入至接觸開口中，以及進行平坦化（例如化學機械研磨（Chemical Mechanical Polish，CMP）製程），以使接觸插塞28的頂表面與ILD 24的頂表面齊平。
在ILD 24以及接觸插塞28上方具有內連線結構30。內連線結構30包括介電層32，以及形成於介電層32中的金屬線34以及通孔36。介電層32在下文中被替代地稱作金屬間介電（Inter-Metal Dielectric，IMD）層32。根據本發明的一些實施例，介電層32中的至少下部層由具有低於約3.0或低於約2.5的介電常數（k值）的低介電常數介電材料形成。介電層32可由黑金剛石（應用材料公司（Applied Materials）的註冊商標）、含碳低介電常數介電材料、氫矽倍半氧烷（Hydrogen SilsesQuioxane，HSQ）、甲基矽倍半氧烷（MethylSilsesQuioxane，MSQ）或其類似者形成。根據本發明的替代實施例，介電層32中的一些或全部由非低介電常數介電材料形成，所述材料例如氧化矽、碳化矽（silicon carbide，SiC）、碳氮化矽（silicon carbo-nitride，SiCN）、氧碳氮化矽（silicon oxy-carbo-nitride，SiOCN）或其類似者。根據本發明的一些實施例，介電層32的形成包括沈積含致孔劑的介電材料，且接著進行固化製程以驅除致孔劑，因此剩餘的介電層32變為多孔的。可由碳化矽、氮化矽或其類似者所形成的蝕刻停止層（未繪示）形成於IMD層32之間，且為簡單起見而未示出。
金屬線（亦包括金屬墊）34以及通孔36形成於介電層32中。以下將處在相同高度處的金屬線34統稱為金屬層。根據本發明的一些實施例，內連線結構30包括通過通孔36互連的多個金屬層。金屬線34以及通孔36可由銅或銅合金形成，且其亦可由其他金屬形成。形成製程可包括單金屬鑲嵌製程以及雙重金屬鑲嵌製程。在例示性單金屬鑲嵌製程中，首先在介電層32中的一者中形成溝渠，接著用導電材料填入溝渠。接著進行例如CMP製程的平坦化製程，以移除高於IMD層的頂表面的導電材料的多餘部分，從而在溝渠中留下金屬線。在雙重金屬鑲嵌製程中，在IMD層中形成溝渠以及通孔開口兩者，其中通孔開口位於溝渠之下且與溝渠連接。接著將導電材料填入至溝渠以及通孔開口中，以分別形成金屬線以及通孔。導電材料可包括擴散阻障材料以及在擴散阻障材料上方的含銅金屬材料。擴散阻障材料可包括鈦、氮化鈦、鉭、氮化鉭或其類似者。
金屬線34包括金屬線34A，其有時被稱作頂部金屬線。頂部金屬線34A亦被統稱作頂部金屬層。各別介電層32A可由例如未摻雜矽酸鹽玻璃（Un-doped Silicate Glass，USG）、氧化矽、氮化矽或其類似者的非低介電常數介電材料形成。介電層32A亦可由低介電常數介電材料形成，所述介電材料可選自底層IMD層32的相似材料。
根據本發明的一些實施例，介電層38、介電層40以及介電層42形成於頂部金屬層上方。介電層38以及介電層42可由氧化矽、氮氧化矽、碳氧化矽或其類似者形成。形成介電層40的介電材料與介電層42的介電材料不同。舉例來說，介電層42可由氮化矽、碳化矽或其類似者形成。
通孔44以及金屬墊46A、金屬墊46B以及金屬墊46C形成於介電層38、介電層40以及介電層42中。各別製程繪示為圖21中所示的製程流程中的步驟202。以下將金屬墊46A、金屬墊46B以及金屬墊46C統稱為及個別地稱為金屬墊46。通孔44及金屬墊46可使用雙重金屬鑲嵌製程而形成，雙重金屬鑲嵌製程包括在介電層38以及介電層40中形成通孔開口、在介電層42中形成溝渠，以及將導電材料填入通孔開口以及溝渠。進行平坦化製程（例如，CMP製程或機械研磨製程），以使介電層42的頂表面與金屬墊46的頂表面齊平。導電材料的填入可包括沈積例如氮化鈦層、氮化鉭層、鈦層、鉭層或其類似者的擴散阻障層，以及將含銅材料沈積於擴散阻障層上方。
根據一些實施例，裝置晶粒4亦可包括形成於介電層38中的金屬墊，例如鋁墊或鋁銅墊。為簡潔起見，並未繪示出鋁（銅）墊。
根據本發明的一些實施例，晶圓2中不存在例如聚合物層的有機介電材料。有機介電層通常具有高的熱膨脹係數（Coefficient of Thermal Expansion，CTE），其可為10 ppm/°C或更高。此顯然大於矽基底（例如基底20）的CTE，矽基底的CTE約為3 ppm/°C。因此，有機介電層趨向於造成晶圓2翹曲。不包括有機材料於其中的晶圓2有助於減少晶圓2中的層之間的CTE失配，並使得翹曲情況減少。另外，不包括有機材料於其中的晶圓2有可能形成精細間距金屬線（例如圖10中的金屬線66以及金屬線70）以及高密度接合墊，並進而改善佈線能力。
圖1亦繪示出與頂部金屬層以及金屬墊46的形成同時形成的被動裝置48A的形成。在本文中，被動裝置可被標示為48A、48B、48C、48D、48E、48F、48G（如圖10至圖14中所示）或其類似者，其可被統稱為及個別地稱作被動裝置48。根據本發明的一些實施例，被動裝置48A（以及任何其他被動裝置48）可為電容器、電感器、變壓器、電阻器或其類似者。圖15繪示出例示性被動裝置48，其為電容器。電容器48包括電容器板160、電容器板164以及電容器絕緣體162。電容器板160以及電容器板164亦分別被稱作電容器48的兩個端子（或稱為兩個末端）TB以及TA。當電容器48A（圖1）為如圖15中所示的結構的電容器時，頂部電容器板164與金屬墊46（圖1）是同時地形成，且底部電容器板160與頂部金屬層34A（圖1）是同時地形成，且電容器絕緣體為介電層38以及介電層40的一部分。
圖16繪示出例示性被動裝置48，其為電感器。電感器可包括底板166、頂板170以及通孔168。通孔168將底板166與頂板170互連以形成電感器。當電容器48A（圖1）為如圖16中所示的結構的電感器時，頂板170與金屬墊46是同時地形成、底板166與頂部金屬層34A是同時地形成，且通孔168（圖16）與通孔44（圖1）同時地形成。圖16中的被動裝置48亦具有兩個端子TA以及TB。在本文中，可形成更多被動裝置，且可藉由參照圖15以及圖16作為實例來尋找例示性結構以及對應層。應瞭解，被動裝置可具有與圖15以及圖16中所示的結構不同的許多結構。
圖2繪示出裝置晶粒112接合至裝置晶粒4。各別製程繪示為圖21中所示的製程流程中的步驟204。根據本發明的一些實施例，裝置晶粒112為邏輯晶粒，其可為CPU晶粒、MCU晶粒、IO晶粒、基頻晶粒、AP晶粒或其類似者。裝置晶粒112亦可為記憶體晶粒。裝置晶粒112包括半導體基底114，其可為矽基底。有時被稱作半導體穿孔或穿孔的矽穿孔（Through-Silicon Via，TSV）116被形成以貫穿半導體基底114。TSV 116用以將形成於半導體基底114的前側（所繪示的底側）上的裝置以及金屬線連接至背側。另外，裝置晶粒112包括內連線結構130，其用以連接至裝置晶粒112中的主動裝置以及被動裝置。內連線結構130包括金屬線以及通孔（未繪示）。
裝置晶粒112可包括介電層138、介電層142以及在介電層138與介電層142之間的蝕刻停止層140。接合墊146以及通孔144形成於介電層138、蝕刻停止層140以及介電層142中。根據本發明的一些實施例，晶粒112不具有例如聚合物的有機介電材料。介電層138、介電層142、接合墊146以及通孔144的材料以及形成方法可類似於其在裝置晶粒4中的對應部分，於此便不再贅述。
可藉由混合接合方式將裝置晶粒112接合至晶粒4。舉例而言，接合墊146藉由金屬對金屬直接接合方式（metal-to-metal direct bonding）接合至接合墊46A及接合墊46C。根據本發明的一些實施例，金屬對金屬直接接合方式包括銅對銅直接接合方式。接合墊146的尺寸可大於、等於或小於各別接合墊46A及接合墊46C的尺寸。雖然僅繪示出一個裝置晶粒112，但可具有多個裝置晶粒112接合至晶圓2，且在相鄰裝置晶粒112之間具有間隙53。此外，介電層142藉由介電質對介電質接合方式（dielectric-to-dielectric bonding）而接合至表面介電層42。介電質對介電質接合方式可以是熔融接合方式（fusion bonding），舉例來說，其中具有Si-O-Si鍵結。為了達成混合接合方式，首先藉由輕微按壓裝置晶粒112來抵靠晶粒4，以將裝置晶粒112預接合（pre-bonded）至介電層42以及接合墊46A。接著，進行退火以使得接合墊46A/接合墊46C以及相對應的上覆接合墊146中的金屬相互擴散。
返回參照圖2，根據一些實施例，在接合製程之後，可進行背側研磨，以將裝置晶粒112薄化至例如介於約15 µm與約30 µm之間的厚度。圖2示意地繪示出虛線112-BS1，其為裝置晶粒112在背側研磨之前的背表面。背表面112-BS2為裝置晶粒112在背側研磨之後的背表面。經由薄化裝置晶粒112，間隙53的深寬比（high aspect ratio）減小，以便進行間隙填充。否則，由於間隙53的其他深寬比，使得間隙填充可能是困難的。在背側研磨之後，可暴露出TSV 116。另外，當存在有基底114的薄層覆蓋TSV 116時背側研磨停止，此時TSV 116不會被暴露出來。根據此等實施例，TSV 116可在圖4中所示的步驟中暴露出來。根據其他實施例，對於間隙填充而言間隙53的深寬比並不過高的情況下，可跳過背側研磨。
根據本發明的一些實施例，裝置晶粒112包括被動裝置48B的一部分。在裝置晶粒112與裝置晶粒4接合之後，將裝置晶粒4的金屬墊接合至裝置晶粒112中的被動裝置48B的所述部分，以形成整個被動裝置48B。舉例而言，當被動裝置48B為電容器時，頂部電容器板可為頂部金屬層134A的一部分。底部電容器板包括上部部分以及底部部分，其分別為裝置晶粒112的金屬墊以及裝置晶粒4的金屬墊。當被動裝置48B為電感器時，舉例來說，如圖16中所示，頂板170（圖16）將處於裝置晶粒112中的頂部金屬層134A（圖2）中，通孔168（圖16）將處於裝置晶粒112中的介電層138以及介電層140（圖2）中，且底板166（圖16）中的每一者亦將包括上部部分以及底部部分，所述上部部分以及底部部分分別為裝置晶粒112的金屬墊以及裝置晶粒4的金屬墊。
在裝置晶粒112接合至裝置晶粒4之後，形成電連接通道52（各自包括堆疊金屬墊/線以及通孔），使得形成於裝置晶粒112以及裝置晶粒4中的被動裝置48可連接至將在後續步驟中形成的上覆電連接件（例如，焊料區）。形成屏蔽環50，其各自包圍電通道52中的一者。當俯視圖2中所示的結構時，屏蔽環50具有環的形狀。屏蔽環50是由金屬線以及通孔形成，其在一些金屬層以及一些通孔層中可為實心環（無斷口）。為了電連接至被動裝置，屏蔽環50具有一些斷口，從而允許金屬線穿過以將被動裝置48連接至電通道52。連接至被動裝置48的金屬線藉由介電材料與屏蔽環電絕緣。舉例而言，圖10匯示出自一平面獲得的橫截面圖，在所述平面中，金屬線穿過屏蔽環50中的斷口，以將被動裝置48B與電連接通道52互連。圖10中的虛線（其示出部分屏蔽環50）表示在所說明平面前方及後方的部分屏蔽環。屏蔽環50為電接地，使得被動裝置（例如被動裝置48B）不會干擾裝置晶粒112以及裝置晶粒4中的其他裝置，且並不受到裝置晶粒112以及裝置晶粒4中的其他裝置干擾。
圖3繪示出包括介電層56以及下方的蝕刻停止層54的間隙填充層的形成。各別製程繪示為圖21中所示的製程流程中的步驟206。蝕刻停止層54可使用例如原子層沈積法（Atomic Layer Deposition，ALD）或化學氣相沈積法（Chemical Vapor Deposition，CVD）的保形沈積方法來沈積。蝕刻停止層54由對裝置晶粒112的側壁以及介電層42與接合墊46B的頂表面具有良好黏附性的介電材料形成。根據本發明的一些實施例，蝕刻停止層54由例如氮化矽的含氮化物材料形成。蝕刻停止層54可為保形層，其水平部分的厚度T1A與垂直部分的厚度T1B實質上彼此相等。舉例來說，厚度T1A與厚度T1B兩者的差（T1A-T1B）具有小於約20%或小於約10%的絕對值。
形成介電層56的材料不同於蝕刻停止層54的材料。根據本發明的一些實施例，介電層56由氧化矽形成，所述氧化矽可由TEOS形成，且亦可使用例如碳化矽、氮氧化矽、氧碳氮化矽、PSG、BSG、BPSG或其類似者的其他介電材料。介電層56可使用CVD、高密度電漿化學氣相沈積法（High-Density Plasma Chemical Vapor Deposition，HDPCVD）、可流動CVD、旋塗式塗佈法或其類似方法來形成。介電層56完全填入剩餘間隙53（圖2）。
參照圖4，進行例如CMP製程或機械研磨製程的平坦化製程，以移除間隙填充層54、56的多餘部分，以暴露出裝置晶粒112。各別製程亦繪示為圖21中所示的製程流程中的步驟206。並且穿孔116被暴露。層54以及層56的剩餘部分被統稱為（間隙填充）隔離區58。
根據本發明的一些實施例，如圖5中所示，輕微地蝕刻基底114，使得穿孔116具有自基底114的頂表面突出的頂部部分。形成介電層60，並將其輕微研磨以移除覆蓋穿孔116的部分介電層60。介電層60可由氧化矽、氮化矽、氮氧化矽或其類似材料形成。根據本發明的一些實施例，蝕刻基底114以及形成介電層60的步驟可被省略。
圖6繪示出蝕刻介電層60、介電層56以及介電層54以形成開口61。各別製程繪示為圖21中所示的製程流程中的步驟208。根據本發明的一些實施例，形成且圖案化光阻（未繪示），且將經圖案化的光阻用以當作作蝕刻罩幕來蝕刻介電層60以及介電層56。由此形成了開口61，且其向下延伸至充當蝕刻停止層的蝕刻停止層54。根據本發明的一些實施例，層60以及層56包括氧化物，且可經由乾式蝕刻來進行蝕刻。蝕刻氣體可包括NF3 與NH3 的混合物或HF與NH3 的混合物。接下來，對蝕刻停止層54進行蝕刻，使得開口61向下延伸至接合墊46B。根據本發明的一些實施例，蝕刻停止層54由氮化矽形成，且使用乾式蝕刻來進行蝕刻。蝕刻氣體可包括CF4 、O2 與N2 的混合物、NF3 與O2 、SF6 的混合物、SF6 與O2 的混合物或其類似者。
圖7繪示出填入開口61（圖6）以形成穿孔64（包括穿孔64-1以及穿孔64-2）以及介電穿孔（Through-Dielectric Via，TDV）65。各別製程繪示為圖21中所示的製程流程中的步驟210。穿孔64以及TDV 65連接至接合墊46B。使TDV 65電接地，以形成屏蔽結構，使得被動裝置（例如圖10中的被動裝置48C）並不會干擾裝置晶粒112以及裝置晶粒4中的其他裝置，且並不受到裝置晶粒112以及裝置晶粒4中的其他裝置干擾。根據本發明的一些實施例，形成穿孔64以及TDV 65包括進行例如電化學電鍍製程或無電電鍍製程的鍍覆製程。穿孔64以及TDV 65可包括例如鎢、鋁、銅或其類似者的金屬材料。亦可在金屬材料之下形成導電阻障層（例如鈦、氮化鈦、鉭、氮化鉭或其類似者）。進行例如CMP的平坦化，以移除經鍍覆的金屬材料的多餘部分，而金屬材料的剩餘部分形成穿孔64以及TDV 65。穿孔64以及TDV 65可具有實質上筆直且垂直的側壁。另外，穿孔64以及TDV 65可具有錐形輪廓，其中頂部寬度略大於相對應的底部寬度。
根據替代實施例，TSV 116並非預先形成在裝置晶粒112中。相對地，TSV 116可在形成隔離區58之後形成。舉例而言，在形成開口61（圖6）之前或之後，蝕刻裝置晶粒112以形成額外開口（由所繪示的TSV 116所佔據）。可同時填入裝置晶粒112中的額外開口以及開口61，以形成TSV 116以及穿孔64。所得的穿孔116可具有寬於相對應的下部部分的上部部分，其與圖10中所示的穿孔相反。
參照圖8，形成介電層62、介電層63、重佈線（Redistribution Line，RDL）66、重佈線（RDL）70以及通孔68。各別製程繪示為圖21中所示的製程流程中的步驟212。根據本發明的一些實施例，介電層62以及介電層63由氧化物（例如氧化矽）、氮化物（例如氮化矽）或其類似者形成。雖然繪示了兩個RDL層，但可存在多於兩個RDL層。可使用單金屬鑲嵌製程及/或雙重金屬鑲嵌製程來形成RDL 70，所述金屬鑲嵌製程包括蝕刻介電層，以形成通孔開口以及溝渠、將導電阻障層沈積至開口中、電鍍例如銅或銅合金的金屬材料，以及進行平坦化以移除金屬材料的多餘部分。在介電層60、介電層62與介電層63之間可存在蝕刻停止層，所述蝕刻停止層並未被繪示出。
圖8繪示出被動裝置48C，其亦可以是電容器、電感器、或其類似者，如圖15以及圖16中的一些例示性實施例中所示。被動裝置48C與其他重佈線同時地形成。
圖9繪示出形成鈍化層、金屬墊以及上覆介電層。各別製程繪示為圖21中所示的製程流程中的步驟214。鈍化層72形成於介電層63上方。金屬墊74形成於鈍化層72下方，且電耦接至RDL 70。金屬墊74可為鋁墊或鋁銅墊，且可使用其他金屬材料。根據本發明的一些實施例，可不形成金屬墊74，而形成鈍化後互連件（Post-Passivation Interconnect，PPI）。鈍化層72可為單層或複合層，且可由無孔材料形成。根據本發明的一些實施例，鈍化層72為包括氧化矽層（未單獨示出）以及氧化矽層上方的氮化矽層（未單獨示出）的複合層。鈍化層72亦可由例如未摻雜矽酸鹽玻璃（USG）、氮氧化矽及/或其類似者的其他無孔介電材料形成。接下來，形成聚合物層76，且接著將其圖案化以暴露金屬墊74。聚合物層76可由聚醯亞胺、聚苯并噁唑（polybenzoxazole，PBO）或其類似者形成。
根據本發明的一些實施例，金屬墊74之下的結構不含有機材料（例如聚合物層），使得用以在金屬墊74下方所形成結構的製程可適用於用以形成裝置晶粒的製程，且可能製成具有小間距以及線寬的精細間距RDL（例如RDL 66以及RDL 70）。
參照圖10，形成凸塊下金屬層（Under-Bump Metallurgy，UBM）77，且UBM 77延伸至聚合物層76中以連接至金屬墊74或PPI。各別製程繪示為圖21中所示的製程流程中的步驟214。根據本發明的一些實施例，每一UBM 77包括阻障層（未繪示）以及在阻障層上方的晶種層（未繪示）。阻障層可為鈦層、氮化鈦層、鉭層、氮化鉭層，或由鈦合金或鉭合金形成的層。晶種層的材料可包括銅或銅合金。例如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金以及其組合的其他金屬亦可包括於UBM 77中。
亦如圖10中所示，形成電連接件78（包括電連接件78-1至電連接件78-5）。各別製程繪示為圖21中所示的製程流程中的步驟214。用於形成UBM 77以及電連接件78的例示性形成製程包括沈積毯覆式UBM層、形成並圖案化罩幕（其可為光阻，未繪示），其中通過罩幕中的開口暴露出部分毯覆式UBM層。在形成UBM 77之後，將所示的封裝體置放於鍍覆溶液（未繪示）中，且進行鍍覆步驟以在UBM 77上形成電連接件78。根據本發明的一些例示性實施例，電連接件78包括非焊料部分（未繪示），所述部分在後續回焊製程中並不熔融。非焊料部分可由銅形成，且因此在下文中被稱作銅凸塊，但其可由其他非焊料材料形成。每一電連接件78亦可包括選自鎳層、鎳合金、鈀層、金層、銀層或其多層的頂蓋層（未繪示）。頂蓋層形成於銅凸塊上方。電連接件78可更包括焊料蓋。在前述步驟中形成的結構被稱作複合晶圓80。對複合晶圓80進行晶粒鋸切（單體化）步驟，以將複合晶圓80分離成多個封裝體82。各別製程繪示為圖21中所示的製程流程中的步驟216。
如圖10中所示，每一被動裝置48（例如圖11至圖13中所示的被動裝置48A、被動裝置48B、被動裝置48C以及被動裝置48D至被動裝置48G）包括兩個端子（圖15以及圖16中的端子TA以及端子TB），每一被動裝置電連接至電連接件78中的一者以及TSV 116中的一者。舉例而言，圖10繪示出分別連接至TSV 116-1、TSV 116-2、TSV 116-3、TSV 64-1以及TSV 64-2的例示性電連接件78-1、78-2、78-3、78-4以及78-5。根據本發明的一些實施例，被動裝置48A以及被動裝置48C中的每一者電連接至穿孔64-1以及穿孔64-2，所述穿孔64-1以及穿孔64-2進一步連接至電連接件78-4以及電連接件78-5。應瞭解，可根據一些實施例而形成被動裝置48A以及被動裝置48C中的一者或兩者。並且，當形成被動裝置48A以及被動裝置48C兩者時，被動裝置48A與被動裝置48C可為不同類型的被動裝置以形成電路，例如LC電路、RC電路、RL電路。被動裝置48A與被動裝置48C亦可為相同類型的被動裝置，例如電容器。此可導致電容增加，而不增加晶片使用面積。相似地，其他被動裝置（例如被動裝置48B）亦連接兩個焊料區（例如焊料區78-2以及焊料區78-3）。
根據本發明的一些實施例，如圖10中所示，被動裝置48形成於封裝體82中，且可以或可以不電連接至封裝體82內部的積體電路且可以或可以不被所述積體電路使用。每一被動裝置48的兩個端子在封裝體82外部連接。因此，被動裝置48亦具有與表面黏著裝置（Surface-Mount Device，SMD）相同的功能，其中表面黏著裝置亦被稱作整合式被動裝置（Integrated Passive Device，IPD）。當封裝體82與其他封裝組件封裝，以形成更大的封裝體時，所述其他封裝組件可直接通過焊料區以及TSV存取及使用被動裝置。
再次參照圖10，TDV 65貫穿隔離區58且環繞被動裝置48。圖17繪示出TDV 65、穿孔64-1以及穿孔64-2以及被動裝置48的例示性佈局的俯視圖。根據一些實施例，多個TDV 65形成為包圍穿孔64-1、穿孔64-2以及在被動裝置48正下方的區域（如圖10中所示）。TDV 65彼此靠近，例如其中距離D1小於約10 μm。使TDV 65電接地，以形成屏蔽結構，進而防止被動裝置48與在TDV 65包圍的區域之外的積體電路裝置之間的干擾。圖18繪示出包圍穿孔64以及被動裝置48正下方的區域的全環狀的TDV 65的俯視圖。
根據本發明的一些實施例，在被動裝置48正上方及在被動裝置48正下方的區域不含例如電晶體以及二極體的主動裝置，以便減少被動裝置48與積體電路之間的干擾。因此，在裝置晶粒4以及裝置晶粒112中設計一些禁區（exclusion zones），且在禁區中不設計有主動裝置。在不與裝置晶粒112重疊的部分裝置晶粒4中堆疊被動裝置以及設計被動裝置可最小化所需的禁區。
圖11至圖13繪示出形成被動裝置48的一些可能的位置。舉例而言，圖11繪示出被動裝置48D處於金屬層（其可能包括或可能不包括介電層32A中的頂部金屬層）中，且在隔離區58正下方形成。被動裝置48D連接至穿孔64-1及穿孔64-2以及電連接件78-4及電連接件78-5。
圖12繪示出被動裝置48E以及被動裝置48F。被動裝置48E包括裝置晶粒4以及裝置晶粒112的接合墊，所述接合墊接合以形成被動裝置48E的頂板。底板以及通孔（若存在）則形成於裝置晶粒4中。被動裝置48F位於裝置晶粒4中且在裝置晶粒112正下方的金屬層（其可能包括或可能不包括介電層32A中的頂部金屬層）中，且電連接至TSV 116-2以及TSV 116-3。被動裝置48D連接至穿孔64-1及穿孔64-2以及電連接件78-4及電連接件78-5。被動裝置48E包括裝置晶粒4以及裝置晶粒112的接合墊，所述接合墊接合以形成被動裝置48E的頂板。底板以及通孔（若存在）則形成於裝置晶粒4中。被動裝置48D亦在隔離區58正下方形成。
圖13繪示出被動裝置48G在與裝置晶粒112重疊的RDL層中，且電連接至TSV 116-2以及TSV 116-3。被動裝置48G可與被動裝置48B重疊，且可與被動裝置48B並聯連接。應瞭解，如圖10至圖13中所示的被動裝置48可以任何組合形成在同一晶片中。
圖1至圖13中所示的封裝體具有面對面（face-to-face）結構，其中裝置晶粒112的前表面面向裝置晶粒4的前表面。圖14繪示出面對背（face-to-back）結構，其中裝置晶粒112的前表面面向裝置晶粒4的背表面。裝置晶粒4包括TSV 16，其延伸穿過基底20以及介電層17。被動裝置48被示出作為示例。應瞭解，如圖10至圖13中所示的被動裝置48可在適用時形成於圖14中的封裝體中，且被動裝置48的細節可與圖10至圖13中基本上相同，於此便不再贅述。
圖19以及圖20繪示出封裝體82接合至其他封裝組件。各別製程繪示為圖21中所示的製程流程中的步驟218。圖19繪示為嵌入有封裝體82（圖10至圖14）的封裝體84。封裝體包括記憶體立方體（memory cubes）86，其包括多個堆疊式記憶體晶粒（未單獨繪示）。封裝體82以及記憶體塊86包封於可以是模製化合物的包封材料88中。介電層以及RDL（被統稱為89）位於封裝體82以及記憶體立方體86之下且連接至所述封裝體82以及記憶體立方體86。封裝體82中的被動裝置48可由記憶體立方體86或接合至封裝體84的封裝組件存取。
圖20說明疊層封裝（Package-on-Package，PoP）結構90，其具有與頂部封裝體93接合的整合式扇出（Integrated Fan-Out，InFO）封裝體92。InFO封裝體90亦包括嵌入於其中的封裝體82。封裝體82以及穿孔94包封於可以是模製化合物的包封材料96中。封裝體82接合至介電層以及RDL，其被統稱為內連線結構95。封裝體82中的被動裝置48（圖20中未繪示，參照圖10至圖14）可由頂部封裝體93或接合至封裝體90的封裝組件存取。
本發明的實施例具有一些優勢特徵。藉由將被動裝置整合在封裝體中，無需SMD，且節省了製造成本。因此，在封裝體中設計被動裝置變得相當有彈性。
根據本發明的一些實施例，一種方法包括：將第一裝置晶粒與第二裝置晶粒接合，其中所述第二裝置晶粒在所述第一裝置晶粒上方，且其中第一被動裝置形成於包括所述第一裝置晶粒以及所述第二裝置晶粒的組合的結構中，且所述第一被動裝置包括第一末端以及第二末端；在所述第一裝置晶粒上方填入間隙填充材料，其中所述間隙填充材料包括所述第二裝置晶粒的相對側上的部分；進行平坦化以暴露出所述第二裝置晶粒，其中所述間隙填充材料的剩餘部分形成隔離區；形成第一穿孔以及第二穿孔，其貫穿所述隔離區以電耦接至所述第一裝置晶粒；以及形成第一電連接件以及第二電連接件，以電耦接至所述第一被動裝置的所述第一末端以及所述第二末端。在一實施例中，所述第一電連接件以及所述第二電連接件包括焊料區。在一實施例中，所述第一被動裝置的所述第一末端以及所述第二末端分別連接至所述第一穿孔以及所述第二穿孔。在一實施例中，所述第一被動裝置包括電容器。在一實施例中，所述第一被動裝置包括電感器。在一實施例中，所述第一裝置晶粒包括第一金屬墊，且所述第二裝置晶粒包括接合至所述第一金屬墊的第二金屬墊，且所述接合進一步導致第二被動裝置的形成，且所述第一金屬墊以及所述第二金屬墊的組合形成所述第二被動裝置的板。在一實施例中，所述第一裝置晶粒包括屏蔽環的第一部分，且所述第二裝置晶粒包括所述屏蔽環的第二部分，且所述第一部分接合至所述屏蔽環的所述第二部分，且其中所述屏蔽環包圍所述第二被動裝置。在一實施例中，所述第一裝置晶粒包括第三被動裝置，所述第三被動裝置包括導電板，且所述間隙填充材料與所述第三被動裝置的所述導電板接觸。在一實施例中，所述方法更包括在所述隔離區中形成多個額外穿孔，其中所述多個額外穿孔為電接地，且所述多個額外穿孔組合在一起以包圍所述第一被動裝置正下方的區域。
根據本發明的一些實施例，一種方法包括：將第一裝置晶粒與第二裝置晶粒接合在一起，其中將所述第一裝置晶粒中的第一金屬墊接合至所述第二裝置晶粒中的第二金屬墊；將所述第二裝置晶粒包封於隔離區中；在所述第二裝置晶粒以及所述隔離區上方形成介電層；在所述介電層中形成第一被動裝置；以及在所述介電層上方形成第一焊料區以及第二焊料區，其中所述第一焊料區以及所述第二焊料區電連接至所述第一被動裝置的相對端子。在一實施例中，所述方法更包括：蝕刻所述隔離區以形成第一開口以及第二開口；以及分別在所述第一開口以及所述第二開口中形成第一穿孔以及第二穿孔，其中所述第一穿孔以及所述第二穿孔電連接至所述第一被動裝置的所述相對端子。在一實施例中，所述第一被動裝置與所述隔離區重疊，且所述第一被動裝置與所述第二裝置晶粒在垂直方向上未對準。在一實施例中，所述第一被動裝置與所述第二裝置晶粒重疊。在一實施例中，經由混合接合方式將所述第一裝置晶粒接合至所述第二裝置晶粒，且將所述第一裝置晶粒的第一表面介電層接合至所述第二裝置晶粒的第二表面介電層。
根據本發明的一些實施例，一種封裝體包括：第一裝置晶粒；第二裝置晶粒，位於所述第一裝置晶粒上方且接合至所述第一裝置晶粒；隔離區，包圍所述第二裝置晶粒；第一穿孔以及第二穿孔，貫穿所述隔離區以分別連接至所述第一裝置晶粒中的第一接合墊以及第二接合墊；以及第一被動裝置，包括分別連接至所述第一穿孔以及所述第二穿孔的第一端子以及第二端子。在一實施例中，所述封裝體更包括第一焊料區以及第二焊料區，所述第一焊料區以及第二焊料區分別電連接至所述第一被動裝置的所述第一端子以及所述第二端子。在一實施例中，所述封裝體更包括所述第一裝置晶粒中的第二被動裝置，其中所述第二被動裝置的端子連接至所述第一穿孔以及所述第二穿孔。在一實施例中，所述第二被動裝置的頂板與所述隔離區的底表面接觸，且所述頂板的頂表面與所述第一裝置晶粒與所述第二裝置晶粒之間的界面共平面。在一實施例中，所述第一裝置晶粒與所述第二裝置晶粒經由混合接合方式而接合，其中所述第一裝置晶粒的接合墊接合至所述第二裝置晶粒的接合墊，且所述第一裝置晶粒的第一表面介電層接合至所述第二裝置晶粒的第二表面介電層，且所述第二被動裝置包括所述第一表面介電層下方的板。在一實施例中，所述封裝體更包括所述隔離區中的屏蔽結構，其中所述屏蔽結構包圍所述第一穿孔以及所述第二穿孔。
前文概述若干實施例的特徵使得本領域的技術人員可更佳地理解本揭露的態樣。本領域的技術人員應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。本領域的技術人員亦應認識到，這些等效構造並不脫離本揭露的精神及範疇，且本領域的技術人員可在不脫離本揭露的精神及範疇的情況下在本文中進行各種改變、替代及更改。
2‧‧‧封裝組件
4‧‧‧裝置晶粒
20‧‧‧半導體基底
22‧‧‧積體電路裝置
24‧‧‧層間介電質（ILD）
28‧‧‧接觸插塞
30‧‧‧內連線結構
32‧‧‧金屬間介電（IMD）層
32A、38、40、42、60、62、63‧‧‧介電層
34‧‧‧金屬線
34A‧‧‧頂部金屬線
36、44‧‧‧通孔
46、46A、46B、46C‧‧‧金屬墊
48、48A、48B、48C、48D、48E、48F、48G‧‧‧被動裝置
50‧‧‧屏蔽環
52‧‧‧電連接通道
53‧‧‧間隙
54‧‧‧蝕刻停止層
56‧‧‧介電層
58‧‧‧隔離區
61‧‧‧開口
64-1、64-2‧‧‧穿孔
65‧‧‧介電穿孔（TDV）
66、70‧‧‧重佈線（RDL）
68‧‧‧通孔
72‧‧‧鈍化層
74‧‧‧金屬墊
76‧‧‧聚合物層
77‧‧‧凸塊下金屬層（UBM）
78、78-1、78-2、78-3、78-4、78-5‧‧‧電連接件
80‧‧‧複合晶圓
82、84‧‧‧封裝體
86‧‧‧記憶體立方體
88‧‧‧包封材料
89‧‧‧介電層以及重佈線（RDL）
90‧‧‧疊層封裝（PoP）結構
92‧‧‧整合式扇出（InFO）封裝體
93‧‧‧頂部封裝體
94‧‧‧穿孔
95‧‧‧內連線結構
96‧‧‧包封材料
112‧‧‧裝置晶粒
112-BS1、112-BS2‧‧‧背表面
114‧‧‧半導體基底
116、116-1、116-2、116-3‧‧‧矽穿孔（TSV）
130‧‧‧內連線結構
134A‧‧‧頂部金屬層
138、142‧‧‧介電層
140‧‧‧蝕刻停止層
144‧‧‧通孔
146‧‧‧接合墊
160‧‧‧底部電容器板
162‧‧‧電容器絕緣體
164‧‧‧頂部電容器板
166‧‧‧底板
168‧‧‧通孔
170‧‧‧頂板
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218‧‧‧步驟
D1‧‧‧距離
T1A、T1B‧‧‧厚度
TA、TB‧‧‧端子
當結合附圖閱讀時，自以下實施方式最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見，任意地增大或減小各種特徵的尺寸。 圖1至圖10為根據一些實施例的在封裝體的製造中的中間階段的橫截面圖。 圖11至圖13繪示出根據一些實施例的具有經由面對面接合方式而接合在一起的裝置晶粒的封裝體的橫截面圖。 圖14繪示出根據一些實施例的具有經由面對背接合方式而接合在一起的裝置晶粒的封裝體的橫截面圖。 圖15及圖16繪示出根據一些實施例的例示性被動裝置。 圖17以及圖18繪示出根據一些實施例的形成於屏蔽結構中的例示性被動裝置。 圖19以及圖20繪示出根據一些實施例的嵌入有封裝體的封裝體的橫截面圖。 圖21繪示出形成根據一些實施例的封裝體的製程流程。

Claims (20)

  1. 一種方法，包括： 將第一裝置晶粒與第二裝置晶粒接合在一起，其中所述第二裝置晶粒位於所述第一裝置晶粒上方，且其中第一被動裝置形成於包括所述第一裝置晶粒以及所述第二裝置晶粒的組合的結構中，且所述第一被動裝置包括第一末端以及第二末端； 在所述第一裝置晶粒上方填入間隙填充材料，其中所述間隙填充材料包括所述第二裝置晶粒的相對側上的部分； 進行平坦化以暴露出所述第二裝置晶粒，其中所述間隙填充材料的剩餘部分形成隔離區； 形成第一穿孔以及第二穿孔，其貫穿所述隔離區以電耦接至所述第一裝置晶粒；以及 形成第一電連接件以及第二電連接件，以電耦接至所述第一被動裝置的所述第一末端以及所述第二末端。
  2. 如申請專利範圍第1項所述的方法，其中所述第一電連接件以及所述第二電連接件包括焊料區。
  3. 如申請專利範圍第1項所述的方法，其中所述第一被動裝置的所述第一末端以及所述第二末端分別連接至所述第一穿孔以及所述第二穿孔。
  4. 如申請專利範圍第1項所述的方法，其中所述第一被動裝置包括電容器。
  5. 如申請專利範圍第1項所述的方法，其中所述第一被動裝置包括電感器。
  6. 如申請專利範圍第1項所述的方法，其中所述第一裝置晶粒包括第一金屬墊，且所述第二裝置晶粒包括接合至所述第一金屬墊的第二金屬墊，且所述接合進一步導致第二被動裝置的形成，且所述第一金屬墊以及所述第二金屬墊的組合形成所述第二被動裝置的板。
  7. 如申請專利範圍第6項所述的方法，其中所述第一裝置晶粒包括屏蔽環的第一部分，且所述第二裝置晶粒包括所述屏蔽環的第二部分，且所述屏蔽環的所述第一部分接合至所述屏蔽環的所述第二部分，且其中所述屏蔽環包圍所述第二被動裝置。
  8. 如申請專利範圍第1項所述的方法，其中所述第一裝置晶粒包括第三被動裝置，所述第三被動裝置包括導電板，且所述間隙填充材料與所述第三被動裝置的所述導電板接觸。
  9. 如申請專利範圍第1項所述的方法，更包括在所述隔離區中形成多個額外穿孔，其中所述多個額外穿孔為電接地，且所述多個額外穿孔組合在一起以包圍所述第一被動裝置正下方的區域。
  10. 一種方法，包括： 將第一裝置晶粒與第二裝置晶粒接合在一起，其中所述第一裝置晶粒中的第一金屬墊接合至所述第二裝置晶粒中的第二金屬墊； 將所述第二裝置晶粒包封於隔離區中； 在所述第二裝置晶粒以及所述隔離區上方形成介電層； 在所述介電層中形成第一被動裝置；以及 在所述介電層上方形成第一焊料區以及第二焊料區，其中所述第一焊料區以及所述第二焊料區電連接至所述第一被動裝置的相對端子。
  11. 如申請專利範圍第10項所述的方法，更包括： 蝕刻所述隔離區以形成第一開口以及第二開口；以及 分別在所述第一開口以及所述第二開口中形成第一穿孔以及第二穿孔，其中所述第一穿孔以及所述第二穿孔電連接至所述第一被動裝置的所述相對端子。
  12. 如申請專利範圍第10項所述的方法，其中所述第一被動裝置與所述隔離區重疊，且所述第一被動裝置與所述第二裝置晶粒在垂直方向上未對準。
  13. 如申請專利範圍第10項所述的方法，其中所述第一被動裝置與所述第二裝置晶粒重疊。
  14. 如申請專利範圍第10項所述的方法，其中經由混合接合方式將所述第一裝置晶粒接合至所述第二裝置晶粒，且將所述第一裝置晶粒的第一表面介電層接合至所述第二裝置晶粒的第二表面介電層。
  15. 一種封裝體，包括： 第一裝置晶粒； 第二裝置晶粒，位於所述第一裝置晶粒上方且接合至所述第一裝置晶粒； 隔離區，包圍所述第二裝置晶粒； 第一穿孔以及第二穿孔，貫穿所述隔離區以分別連接至所述第一裝置晶粒中的第一接合墊以及第二接合墊；以及 第一被動裝置，包括分別連接至所述第一穿孔以及所述第二穿孔的第一端子以及第二端子。
  16. 如申請專利範圍第15項所述的封裝體，更包括： 第一焊料區以及第二焊料區，分別電連接至所述第一被動裝置的所述第一端子以及所述第二端子。
  17. 如申請專利範圍第15項所述的封裝體，更包括： 所述第一裝置晶粒中的第二被動裝置，其中所述第二被動裝置的端子連接至所述第一穿孔以及所述第二穿孔。
  18. 如申請專利範圍第17項所述的封裝體，其中所述第二被動裝置的頂板與所述隔離區的底表面接觸，且所述頂板的頂表面與所述第一裝置晶粒與所述第二裝置晶粒之間的界面共平面。
  19. 如申請專利範圍第17項所述的封裝體，其中所述第一裝置晶粒與所述第二裝置晶粒經由混合接合方式而接合在一起，其中所述第一裝置晶粒的接合墊接合至所述第二裝置晶粒的接合墊，且所述第一裝置晶粒的第一表面介電層接合至所述第二裝置晶粒的第二表面介電層，且所述第二被動裝置包括所述第一表面介電層下方的板。
  20. 如申請專利範圍第15項所述的封裝體，更包括所述隔離區中的屏蔽結構，其中所述屏蔽結構包圍所述第一穿孔以及所述第二穿孔。
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