JP2011515843A - 基板貫通バイアの作製方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
Description
・基板中または基板を貫通する深いホールの形成(一般にはレーザドリル、DRIE等を使用)、
・絶縁体または誘電体材料(一般にはSiO2、SiN、ポリマー等)を用いたホールの分離、
・バイアホール中への導電性材料の適用またはメタライゼーション(一般には、Cu、Wであるが、Al、Au、Sn、多結晶Si等でも良い)、
を含む。
・基板の型(Si、SOI等)、
・TSVが処理されるデバイスの製造のためのプロセスフロー中での位置(例としては、フロントエンドオブライン(FEOL)の前、FEOLの後でバックエンドオブライン(BEOL)の前、BEOLの後、積層の後、薄層化の前/後等である)、
・互いの上にデバイスまたは基板を積層する方法、およびTSVがスタック中の次のレベルに相互接続される方法(酸化物/金属接続と組み合わせた酸化物積層、導電性ポリマー接着剤、Cu/Cu金属融合、はんだ(マイクロバンプ)、ハイブリッドの金属/誘電体ボンド等)、
・TSVホールがそこから処理されるウエハの面(ウエハ/基板表面、またはウエハ/基板裏面)、に関して異なる。
・例えばシリコンウエハのような半導体基板を選択する工程と、
・半導体ウエハの第1面で、フロントエンドオブラインプロセスとバックエンドオブラインプロセスとを含むICを作製する工程と、
・ICの作製後に、ウエハの第1面と本質的に平行であるウエハの第2面で半導体ウエハを薄膜化する工程と、
・ウエハの薄膜化の後に、第2面に基板貫通バイアホールを作製し、これにより、基板貫通バイアがコンタクトレベルまで貫通する工程と、
・導電性材料で、基板貫通バイアホールを埋める工程と、
・1つの面で、少なくとも1つの第2コンタクトと相互接続する金属ボンドパッドと電気的に接続し、他の面で、TSVと電気的に接続する、少なくとも1つの第2コンタクトを作製する工程と、
・バックエンドオブラインプロセスで、電気ワイアリング中に金属ボンドパッドを集積する工程と、を含む。
・50nmのPECVD−SiC61の堆積、
・700nmの高密度プラズマ(HDP)ホウ素ドープのフォスフォシリケイトガラス(B−PSG)13の堆積、
・500nmの膜厚までのPSG層の化学機械研磨(CMP)、
・20nmのPECVD窒化物の堆積。
Claims (14)
- 基板(5)、チップ(11)の少なくとも1つのデバイスを含むFEOL(1)、金属1層(16)を含むBEOL(3)、基板(5)とBEOL(3)の金属1層(16)との間のプレメタル誘電体(13)、少なくとも1つのデバイス(1)への少なくとも1つの第1コンタクト(2)およびプレメタル誘電体(13)を通り金属1層(16)と電気的に接続する少なくとも1つの第2コンタクトプラグ(50)を含む半導体チップ(11)中に、基板貫通バイア(75)を作製する方法であって、
BEOL(3)の金属1層(16)まで延びない、基板(5)を通るバイアホール(60)を形成する工程と、
導電性材料でバイアホール(60)を埋め込み、これにより金属1層(16)との電気的接続が、プレメタル誘電体(13)中の少なくとも1つの第2コンタクトプラグ(50)を介して実現される工程を含む方法。 - 更に、プレメタル誘電体(13)の中に、少なくとも1つの第2コンタクトプラグ(50)を形成する工程を含む請求項1に記載の方法。
- 少なくとも1つの第2コンタクトプラグ(50)を形成する工程は、少なくとも1つのFEOLデバイス(1)に少なくとも1つの第1コンタクト(2)を形成する工程と同時に行われる請求項2に記載の方法。
- 少なくとも1つの第2コンタクトプラグ(50)を形成する工程は、後にその上に基板貫通バイア(75)が載せられる位置に、少なくとも1つの第2コンタクトプラグ(50)を形成する工程を含む請求項2または3のいずれかに記載の方法。
- 更に、少なくとも1つの第2コンタクトプラグ(50)の下方に、これと電気的に接続するように、基板(5)中にシリサイド化された領域(56)を形成する工程を含む請求項2〜4のいずれかに記載の方法。
- 更に、シリサイド化された領域(56)を含むダイオード(58)を、シリサイド化された領域(56)の位置に形成する工程を含む請求項5に記載の方法。
- 基板貫通バイアを作製する工程は、バイアホール(60)を形成する工程と、他のチップ上にチップ(11)を積層する前にバイアホールを充填する工程とを含む請求項1〜6のいずれかに記載の方法。
- 更に、バイアホール(60)を形成する前に、基板(5)を薄膜化する工程を含む請求項1〜7のいずれかに記載の方法。
- 少なくとも1つのFEOLデバイス(1)を有する基板(5)、
金属パッド(55)を含むBEOL(3)、
少なくとも1つのFEOLデバイス(1)と接続する少なくとも1つの第1コンタクト(2)、および、
金属パッド(55)の下方にあり、それと電気的に接続する少なくとも1つの第2コンタクトプラグ(50)、を含む半導体チップ(11)であって、
少なくとも1つの第2コンタクトプラグ(50)が一端において金属パッド(55)に接続し、他端でFEOLデバイス(1)の一部でない材料(56)に接続する半導体チップ。 - 少なくとも第2コンタクトプラグ(50)の他端がシリサイド化された領域(56)に接続され、
半導体チップは、更に、シリサイド化された領域(56)の位置にダイオード(58)を含む請求項9に記載の半導体チップ。 - 更に、少なくとも1つの第2コンタクトプラグ(50)と電気的に接続された基板貫通バイア(75)を含む請求項9に記載の半導体チップ。
- 半導体チップ(11)が、更にFEOL(1)とBEOL(3)との間にプレメタル誘電体層(13)を有し、
基板貫通バイア(75)は、プレメタル誘電体層(13)を貫通しない請求項11に記載の半導体チップ。 - 基板貫通バイア(75)は、BEOL(3)の一部のみを通る請求項11または12に記載の半導体チップ。
- 更に、少なくとも1つの第2コンタクトプラグ(50)の下方のシリサイド化された領域(56)を含み、シリサイド化された領域(56)は、少なくとも1つの第2コンタクトプラグ(50)と基板貫通バイア(75)とに電気的に接続する請求項11〜13のいずれかに記載の半導体チップ。
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US3799208P | 2008-03-19 | 2008-03-19 | |
US61/037,992 | 2008-03-19 | ||
PCT/EP2009/052922 WO2009115449A1 (en) | 2008-03-19 | 2009-03-12 | Method for fabricating through-substrate vias |
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US9646930B2 (en) | 2017-05-09 |
US20110089572A1 (en) | 2011-04-21 |
US20150035168A1 (en) | 2015-02-05 |
EP2255386A1 (en) | 2010-12-01 |
EP3032578B1 (en) | 2021-01-13 |
EP2255386B1 (en) | 2016-05-04 |
US8809188B2 (en) | 2014-08-19 |
EP3032578A1 (en) | 2016-06-15 |
WO2009115449A1 (en) | 2009-09-24 |
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