CN113284841A - 形成三维半导体结构的方法 - Google Patents

形成三维半导体结构的方法 Download PDF

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CN113284841A
CN113284841A CN202010341593.3A CN202010341593A CN113284841A CN 113284841 A CN113284841 A CN 113284841A CN 202010341593 A CN202010341593 A CN 202010341593A CN 113284841 A CN113284841 A CN 113284841A
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dielectric layer
interlayer dielectric
circuit
substrate
forming
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CN113284841B (zh
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施信益
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种形成三维半导体结构的方法，包括：形成介电穿孔，从第一元件的第一层间介电层的第一表面延伸至第一层间介电层内；通过第一层间介电层的第一表面和第二元件的第二表面粘合第一元件和第二元件，使得第二表面上的通硅接触垫覆盖介电穿孔；执行蚀刻工艺在第一元件的背面上以同时形成第一通孔和第二通孔，并通过第二通孔露出通硅接触垫，前述背面背向第一层间介电层；以及形成第一通孔插塞以填充第一通孔，以及第二通孔插塞以填充第二通孔和介电穿孔。本发明的方法可在三维半导体结构的一个表面上同时形成电性连接至第一元件和第二元件。

Description

形成三维半导体结构的方法
技术领域
本发明内容是关于一种形成三维半导体结构的方法。
背景技术
此处的陈述仅提供与本发明有关的背景信息，而不必然地构成现有技术。
随着电子元件密度的增加，三维电路布线方案的开发已启动。近年来，连接上部电子元件和下部电子元件的硅穿孔(through silicon via，TSV)技术蓬勃发展。形成TSV的过程可从上部电子元件的表面开始。TSV结构的完成能够电性连接至上部电子元件的电路互连部和下部电子元件的电路互连部，并且能够接收外部信号。然而，在一般情况下，须完成多步蚀刻工艺才能完成TSV结构。最近来亦有一种替代方法，在上部电子元件中的特定部分嵌入蚀刻延迟结构，从而可在同一蚀刻工艺中产生不同深度的TSV。接着形成可从上部电子元件的表面与上部电子元件和下部电子元件直接电性连接的三维电路结构。
发明内容
本发明的目的在于提供一种三维半导体结构的方法，该方法可在三维半导体结构的一个表面上同时形成电性连接至第一元件和第二元件。
本发明的一些实施方式公开了一种三维半导体结构的方法，包括：制备第一元件，第一元件具有第一电路和第一层间介电层设置在第一基板上，其中第一层间介电层围绕第一电路并接触第一基板；形成介电穿孔，从第一层间介电层的第一表面延伸至第一层间介电层内，其中第一表面背向第一基板；通过第一层间介电层的第一表面和第二元件的第二表面粘合第一元件和第二元件，使得从第二元件的第二表面露出的通硅接触垫覆盖介电穿孔；以及执行蚀刻工艺在第一元件的背面上以同时形成第一通孔和第二通孔，并通过第二通孔露出通硅接触垫，前述背面背向第一层间介电层。
在本发明的一或多个实施方式中，第二元件还由下述方法制备：形成第二电路和第二层间介电层于第二基板上，其中第二层间介电层围绕第二电路，通硅接触垫是在第二层间介电层的第二表面上，且第二表面背向第二基版。
在本发明的一或多个实施方式中，粘合包括混成粘合第一元件和第二元件，使得第一电路的第一导电垫粘合至第二电路的第二导电垫，第一层间介电层粘合至第二层间介电层，其中第一导电垫从第一表面露出并与第一电路的多个第一互连部的一部分接触，且第二导电垫从第二表面露出并与第二电路的多个第二互连部的一部分接触。
在本发明的一或多个实施方式中，还包括在执行蚀刻工艺之前从第一基板的背面部分移除第一基板。
在本发明的一或多个实施方式中，部分移除是通过硅研磨进行。
在本发明的一或多个实施方式中，还包括在执行蚀刻工艺之前形成钝化层于第一基板的背面上。
在本发明的一或多个实施方式中，执行蚀刻工艺包括：蚀刻第一基板的背面以形成第一盲孔和第二盲孔，使得第一盲孔的第一暂时端紧邻第一电路的多个第一互连部当中的一个，且第二盲孔的第二暂时端紧邻介电穿孔；共形地形成隔离层于第一盲孔和第二盲孔中；以及蚀刻第一基板的背面以从第一盲孔形成第一通孔，以及从第二盲孔形成第二通孔。
在本发明的一或多个实施方式中，蚀刻隔离层是通过干蚀刻进行。
在本发明的一或多个实施方式中，蚀刻第一基板的背面以从第一盲孔形成第一通孔，以及从第二盲孔形成第二通孔包括：蚀刻隔离层和第一层间介电层直到第一电路的多个第一互连部当中的一个从第一通孔露出，且通硅接触垫从第二通孔露出。
在本发明的一或多个实施方式中，第二通孔的直径大于介电穿孔的直径。
在本发明的一或多个实施方式中，第一通孔和第二通孔的形成使得第一电路的多个第一互连部当中的一个从第一通孔露出，且通硅接触垫从第二通孔露出。
在本发明的一或多个实施方式中，还包括形成第一通孔插塞以填充第一通孔，以及第二通孔插塞以填充第二通孔和介电穿孔，其中第一通孔插塞接触第一电路的多个第一互连部当中的一个，且第二通孔插塞接触通硅接触垫。
本发明的上述实施方式能够通过实质上一个蚀刻和一个沉积工艺，在三维半导体结构的一个表面上同时形成电性连接至第一元件和第二元件。其省去了用于在执行蚀刻工艺时降低形成某些通孔的蚀刻速率的额外蚀刻延迟结构。
为了让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1绘示本发明一些实施例中形成三维半导体结构的方法的流程图。
图2A绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图2B绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图3绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图4绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图5绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图6绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图7绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图8绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
图9绘示本发明一些实施例中图1所描述的方法的中间阶段的剖面示意图。
主要附图标记说明：
1000-三维半导体结构，110-第一元件，1102-第一表面，1104-背面，112-第一基板，114-第一电路，1142-第一互连部，1144-第一导电垫，116-第一层间介电层，118-介电穿孔，120-第二元件，1202-第二表面，122-第二基板，124-第二电路，1242-第二互连部，1244-第二导电垫，126-第二层间介电层，128-通硅接触垫，130-钝化层，140-隔离层，B1-第一盲孔，B2-第二盲孔，D1,D2-直径，I1-第一内壁，I2-第二内壁，P1-第一通孔插塞，P2-第二通孔插塞，S-方法，S1,S2,S3,S4,S5-操作，T1-第一暂时端，T2-第二暂时端，V1-第一通孔，V2-第二通孔。
具体实施方式
为使本发明的叙述更加详尽与完备，下文针对了本发明的实施态样与具体实施例提出了说明性的描述；但这并非实施或运用本发明具体实施例的唯一形式。以下所公开的各实施例，在有益的情形下可相互组合或取代，也可在一实施例中附加其他的实施例，而无须进一步的记载或说明。
在以下的描述中，将详细叙述许多特定细节以使读者能够充分理解以下的实施例。然而，可在无此等特定细节的情况下实践本发明的实施例。在其他情况下，为简化附图，熟知的结构与装置仅示意性地绘示于图中。
参考图1至图9。图1绘示本发明一些实施例中形成三维半导体结构的方法S的流程图。图2A至图9绘示本发明一些实施例中图1所描述的方法S的中间阶段的剖面示意图。方法S从操作S1开始，制备第一元件110。第一元件110具有第一电路114和第一层间介电层116，其皆设置在第一基板112上。其中，第一层间介电层116围绕第一电路114并接触第一基板112(参考图2A)。在一些实施例中，第一电路114嵌入第一层间介电层116。详细而言，第一层间介电层116包围并接触第一电路114的第一互连部1142。第一电路114的第一导电垫1144电性连接第一互连部1142并接触第一层间介电层116。此外，第一导电垫1144从第一层间介电层116的第一表面1102露出，其中第一表面1102背向第一基板112。在一些实施例中，第一元件110是以在第一基板112上形成(例如，以沉积方式形成)第一电路114和第一层间介电层116的方式制备。
方法S接着进行操作S2，形成介电穿孔118，从第一层间介电层116的第一表面1102延伸至第一层间介电层116内(亦参考图2A)。介电穿孔118可用例如湿蚀刻或干蚀刻的方式形成，但不以此为限。方法S接着进行操作S3，通过第一层间介电层116的第一表面1102和第二元件120的第二表面1202粘合第一元件110和第二元件120，使得从第二元件120的第二表面1202露出的通硅接触垫128覆盖介电穿孔118(参考图2B和图3)。在一些实施例中，混成粘合(hybrid bonding)第一元件110和第二元件120，使得第一电路114的一些第一导电垫1144粘合并接触第二电路124的一些第二导电垫1244，且第一层间介电层116粘合并接触第二元件120的第二层间介电层126。在一些实施例中，第一导电垫1144从第一表面1102露出并与第一互连部1142的一部分接触，且第二导电垫1244从第二表面1202露出并与第二互连部1242的一部分接触。第一互连部1142和第二互连部1242可分别是分布并嵌入于第一层间介电层116和第二层间介电层126中以形成多层电路的电路。第一互连部1142和第二互连部1242亦可包括导电垫，其连接不同电路层。
第一互连部1142、第二互连部1242、第一导电垫1144和第二导电垫1244可包括金属，例如钨(tungsten，W)、铝(aluminum，Al)、铜(copper，Cu)，或是金属硅化物(metalsilicides)，例如二硅化钨(tungsten silicide，WSi2)、二硅化钛(titanium silicide，TiSi2)，或是金属化合物，例如氮化钨(tungsten nitride，W3N2)、氮化钛(titaniumnitride，TiN)，或多晶硅(polycrystalline silicon，poly-Si)或其组合，但不以此为限。
第一层间介电层116和第二层间介电层126可包括绝缘材料，例如二氧化硅(silicon dioxide，SiO2)，但不以此为限。
在一些实施例中，第二元件120是以在第二基板122上形成(例如，以沉积方式形成)第二电路124和第二层间介电层126的方式制备。第二层间介电层126围绕第二电路124。通硅接触垫128从第二层间介电层126的第二表面1202露出，第二表面1202背向第二基板122。
第一基板112和第二基板122可包括块材单晶硅晶圆、绝缘层上硅晶(silicon-on-insulator，SOI)、化合物半导体，例如硅锗(silicon-germanium，SiGe)，或硅磊晶层长于其上的晶圆，但不以此为限。
方法S接着进行操作S4，执行蚀刻工艺于第一基板112背向第一层间介电层116的背面1104上以同时形成第一通孔V1和第二通孔V2，并通过第二通孔V2露出通硅接触垫128(参考图3和图8)。在一些实施例中，第一通孔V1预对准其中一个上述的第一互连部1142。在第一通孔V1和第二通孔V2形成前，第二通孔V2的位置预对准通硅接触垫128。在一些实施例中，于操作S3后，在执行蚀刻工艺前从第一基板112的背面1104部分去除第一基板112(参考图4)。在一些实施例中，部分去除是通过硅研磨方式，但不以此为限。通过硅研磨，更容易让接下来的蚀刻工艺能蚀刻穿过第一基板112。在一些实施例中，在执行蚀刻工艺前，钝化层130形成于第一基板112的背面1104上(参考图5)。在那的后，可在背面1104上执行干蚀刻工艺以移除一部分的钝化层130，接着可执行湿蚀刻工艺以形成第一盲孔B1和第二盲孔B2(参考图6)。应注意，去除前述一部分的钝化层130以及形成第一盲孔B1和第二盲孔B2的操作不限于上述的工艺。在一些其它实施例中，去除前述一部分的钝化层130以及形成第一盲孔B1和第二盲孔B2可于单一干蚀刻工艺中执行。在前面提到的实施例中，第一盲孔B1的第一暂时端T1紧邻(例如，延伸进层间介电层116)其中一个第一互连部1142，且第二盲孔B2的第二暂时端T2紧邻(例如，延伸进层间介电层116)介电穿孔118。钝化层130可包括二氧化硅(silicon dioxide，SiO2)、氮化硅(silicon nitride，SiNx)或有机材料，例如苯环丁烯(benzocyclobutene，BCB)，但不以此为限。
在一些实施例中，隔离层140共形地形成于第一盲孔B1和第二盲孔B2内(参考图7)。隔离层140可包括绝缘材料，例如和用于钝化层130的材料相同的材料，但不以此为限。隔离层140可形成于第一基板112的第一盲孔B1中的第一内壁I1、第一暂时端T1、第一基板112的第二盲孔B2中的第二内壁I2以及第二暂时端T2上，但不以此为限。在形成隔离层140后，接着蚀刻第一基板112的背面1104以从第一盲孔B1形成第一通孔V1，并从第二盲孔B2形成第二通孔V2(参考图8)。在一些实施例中，蚀刻隔离层140和第一层间介电层116直到其中一个上述的第一互连部1142自第一通孔V1露出，且通硅接触垫128自第二通孔V2露出。
方法S接着进行操作S5，形成第一通孔插塞P1以填充第一通孔V1，以及第二通孔插塞P2以填充第二通孔V2和介电穿孔118。第一通孔插塞P1和第二通孔插塞P2可包括金属，例如钨、铝、钴、镍和铜，和/或金属硅化物，但不以此为限。第一通孔插塞P1接触第一电路114的前述的其中一个第一互连部1142，且第二通孔插塞P2接触通硅接触垫128。在第一盲孔B1内的第一内壁I1上的隔离层140和在第二盲孔B2内的第二内壁I2上的隔离层140防止了第一通孔插塞P1和第一基板112之间，以及第二通孔插塞P2和第一基板112之间的接触和直接电性连接。通过以上工艺，形成了三维半导体结构1000(参考图9)。上述工艺可同时形成从第一元件110的背面1104(经由第一通孔插塞P1)直接电性连接第一互连部1142以及从第一元件110的背面1104(经由第二通孔插塞P2)直接电性连接通硅接触垫128，而不需使用任何额外的蚀刻延迟结构来控制第一通孔V1的蚀刻速率。在一些实施例中，第二通孔V2的直径D1大于介电穿孔118的直径D2，从而防止第二通孔插塞P2和第一基板112之间可能的漏电流。在一些实施例中，在第一通孔插塞P1、第二通孔插塞P2和钝化层130上执行化学机械研磨(chemical mechanical planarization，CMP)工艺。亦即，于形成第一通孔插塞P1和第二通孔插塞P2后在背面1104上执行化学机械研磨工艺以平坦化背面1104。
综上所述，本发明的实施例提供形成三维半导体结构的方法，通过实质上一个蚀刻和一个沉积工艺，可在三维半导体结构的一个表面上同时形成电性连接至第一元件和第二元件，其省去了用于在执行蚀刻工艺时降低形成某些通孔的蚀刻速率的额外蚀刻延迟结构。
虽然本发明已以实施例公开如上，然并非用以限定本发明，所属领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (12)

1.一种形成三维半导体结构的方法，其特征在于，包括：
制备第一元件，所述第一元件具有第一电路和第一层间介电层设置在第一基板上，其中所述第一层间介电层围绕所述第一电路并接触所述第一基板；
形成介电穿孔，从所述第一层间介电层的第一表面延伸至所述第一层间介电层内，其中所述第一表面背向所述第一基板；
通过所述第一层间介电层的所述第一表面和第二元件的第二表面粘合所述第一元件和所述第二元件，使得从所述第二元件的所述第二表面露出的通硅接触垫覆盖所述介电穿孔；以及
执行蚀刻工艺在所述第一元件的背面上以同时形成第一通孔和第二通孔，并通过所述第二通孔露出所述通硅接触垫，其中所述背面背向所述第一层间介电层。
2.如权利要求1所述的方法，其特征在于，所述第二元件还由下述方法制备：
在第二基板上形成第二电路和第二层间介电层，其中所述第二层间介电层围绕所述第二电路，所述通硅接触垫是在所述第二层间介电层的所述第二表面上，且所述第二表面背向所述第二基版。
3.如权利要求2所述的方法，其特征在于，所述粘合包括：
混成粘合所述第一元件和所述第二元件，使得所述第一电路的第一导电垫粘合至所述第二电路的第二导电垫，所述第一层间介电层粘合至所述第二层间介电层，其中所述第一导电垫从所述第一表面露出并与所述第一电路的多个第一互连部的一部分接触，且所述第二导电垫从所述第二表面露出并与所述第二电路的多个第二互连部的一部分接触。
4.如权利要求1所述的方法，其特征在于，还包括在执行所述蚀刻工艺之前从所述第一基板的所述背面部分移除所述第一基板。
5.如权利要求4所述的方法，其特征在于，所述部分移除是通过硅研磨进行。
6.如权利要求1所述的方法，其特征在于，还包括在执行所述蚀刻工艺之前形成钝化层于所述第一基板的所述背面上。
7.如权利要求1所述的方法，其特征在于，执行所述蚀刻工艺包括：
蚀刻所述第一基板的所述背面以形成第一盲孔和第二盲孔，使得所述第一盲孔的第一暂时端紧邻所述第一电路的多个第一互连部当中的一个，且所述第二盲孔的第二暂时端紧邻所述介电穿孔；
在所述第一盲孔和所述第二盲孔中共形地形成隔离层；以及
蚀刻所述第一基板的所述背面以从所述第一盲孔形成所述第一通孔，以及从所述第二盲孔形成所述第二通孔。
8.如权利要求7所述的方法，其特征在于，蚀刻所述隔离层是通过干蚀刻进行。
9.如权利要求7所述的方法，其特征在于，蚀刻所述第一基板的所述背面以从所述第一盲孔形成所述第一通孔，以及从所述第二盲孔形成所述第二通孔包括：
蚀刻所述隔离层和所述第一层间介电层直到所述第一电路的所述多个第一互连部当中的一个从所述第一通孔露出，且所述通硅接触垫从所述第二通孔露出。
10.如权利要求1所述的方法，其特征在于，所述第二通孔的直径大于所述介电穿孔的直径。
11.如权利要求1所述的方法，其特征在于，所述第一通孔和所述第二通孔的形成使得所述第一电路的多个第一互连部当中的一个从所述第一通孔露出，且所述通硅接触垫从所述第二通孔露出。
12.如权利要求1所述的方法，其特征在于，还包括：
形成第一通孔插塞以填充所述第一通孔，以及第二通孔插塞以填充所述第二通孔和所述介电穿孔，其中所述第一通孔插塞接触所述第一电路的多个第一互连部当中的一个，且所述第二通孔插塞接触所述通硅接触垫。
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