CN113284841A - Method for forming three-dimensional semiconductor structure - Google Patents

Method for forming three-dimensional semiconductor structure Download PDF

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Publication number
CN113284841A
CN113284841A CN202010341593.3A CN202010341593A CN113284841A CN 113284841 A CN113284841 A CN 113284841A CN 202010341593 A CN202010341593 A CN 202010341593A CN 113284841 A CN113284841 A CN 113284841A
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dielectric layer
interlayer dielectric
circuit
substrate
forming
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CN202010341593.3A
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CN113284841B (en
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施信益
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Nanya Technology Corp
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Nanya Technology Corp
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    • H01L2224/808—Bonding techniques
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Abstract

The invention discloses a method for forming a three-dimensional semiconductor structure, which comprises the following steps: forming a dielectric via extending from a first surface of a first interlayer dielectric layer of the first element into the first interlayer dielectric layer; bonding the first and second elements through the first surface of the first interlayer dielectric layer and the second surface of the second element such that the through-silicon contact pad on the second surface covers the dielectric via; performing an etching process on the back surface of the first element to simultaneously form a first through hole and a second through hole, and exposing the through silicon contact pad through the second through hole, wherein the back surface faces away from the first interlayer dielectric layer; and forming a first via plug to fill the first via, and a second via plug to fill the second via and the dielectric via. The method of the present invention can simultaneously form an electrical connection to a first element and a second element on one surface of a three-dimensional semiconductor structure.

Description

Method for forming three-dimensional semiconductor structure
Technical Field
The present disclosure relates to a method of forming a three-dimensional semiconductor structure.
Background
The statements herein merely provide background information related to the present disclosure and may not necessarily constitute prior art.
As the density of electronic components has increased, the development of three-dimensional circuit routing schemes has been initiated. In recent years, Through Silicon Via (TSV) technology for connecting an upper electronic component and a lower electronic component has been developed vigorously. The process of forming the TSV may begin from the surface of the upper electronic element. The completion of the TSV structure can be electrically connected to the circuit interconnection of the upper electronic element and the circuit interconnection of the lower electronic element, and can receive an external signal. However, in general, a multi-step etching process is performed to complete the TSV structure. Recently, there has been an alternative method of embedding an etch delay structure in a specific portion of the upper electronic device, so that TSVs of different depths can be generated in the same etching process. A three-dimensional circuit structure is then formed that can be electrically connected directly from the surface of the upper electronic component to the upper electronic component and the lower electronic component.
Disclosure of Invention
The present invention is directed to a method of forming a three-dimensional semiconductor structure that simultaneously forms an electrical connection to a first element and a second element on a surface of the three-dimensional semiconductor structure.
Some embodiments of the invention disclose a method of three-dimensional semiconductor structure, comprising: preparing a first element having a first circuit and a first interlayer dielectric layer disposed on a first substrate, wherein the first interlayer dielectric layer surrounds the first circuit and contacts the first substrate; forming a dielectric via extending into the first interlayer dielectric layer from a first surface of the first interlayer dielectric layer, wherein the first surface faces away from the first substrate; bonding the first and second elements through the first surface of the first interlayer dielectric layer and the second surface of the second element such that the through-silicon contact pad exposed from the second surface of the second element covers the dielectric via; and performing an etching process on the back surface of the first element to simultaneously form a first via hole and a second via hole, and exposing the through silicon contact pad through the second via hole, the back surface facing away from the first interlayer dielectric layer.
In one or more embodiments of the invention, the second component is further prepared by: and forming a second circuit and a second interlayer dielectric layer on the second substrate, wherein the second interlayer dielectric layer surrounds the second circuit, the through silicon contact pad is arranged on the second surface of the second interlayer dielectric layer, and the second surface faces away from the second substrate.
In one or more embodiments of the present invention, the bonding includes hybrid bonding the first element and the second element such that the first conductive pad of the first circuit is bonded to the second conductive pad of the second circuit, and the first interlayer dielectric layer is bonded to the second interlayer dielectric layer, wherein the first conductive pad is exposed from the first surface and is in contact with a portion of the plurality of first interconnects of the first circuit, and the second conductive pad is exposed from the second surface and is in contact with a portion of the plurality of second interconnects of the second circuit.
In one or more embodiments of the present invention, the method further includes removing the first substrate from a backside portion of the first substrate before performing the etching process.
In one or more embodiments of the present invention, the partial removal is performed by silicon polishing.
In one or more embodiments of the present invention, the method further includes forming a passivation layer on the back surface of the first substrate before performing the etching process.
In one or more embodiments of the present invention, performing an etching process includes: etching the back surface of the first substrate to form a first blind hole and a second blind hole, so that a first temporary end of the first blind hole is adjacent to one of the first interconnections of the first circuit, and a second temporary end of the second blind hole is adjacent to the dielectric through hole; forming an isolation layer in the first blind hole and the second blind hole conformally; and etching the back surface of the first substrate to form a first through hole from the first blind via and a second through hole from the second blind via.
In one or more embodiments of the present invention, etching the isolation layer is performed by dry etching.
In one or more embodiments of the present invention, etching the back surface of the first substrate to form the first via hole from the first blind hole, and forming the second via hole from the second blind hole includes: the isolation layer and the first interlayer dielectric layer are etched until one of the plurality of first interconnections of the first circuit is exposed from the first via hole and the through silicon contact pad is exposed from the second via hole.
In one or more embodiments of the present invention, the diameter of the second via is larger than the diameter of the dielectric via.
In one or more embodiments of the present invention, the first via and the second via are formed such that one of the plurality of first interconnections of the first circuit is exposed from the first via, and the through-silicon contact pad is exposed from the second via.
In one or more embodiments of the present invention, the method further includes forming a first via plug to fill the first via, and a second via plug to fill the second via and the through dielectric via, wherein the first via plug contacts one of the plurality of first interconnects of the first circuit, and the second via plug contacts the through silicon contact pad.
The above-described embodiments of the present invention enable the simultaneous formation of electrical connections to a first element and a second element on one surface of a three-dimensional semiconductor structure by essentially one etching and one deposition process. Which omits an additional etch-delay structure for reducing an etch rate for forming some of the via holes when performing the etch process.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a flow chart illustrating a method of forming a three-dimensional semiconductor structure according to some embodiments of the present invention.
FIG. 2A is a schematic cross-sectional view of an intermediate stage of the method depicted in FIG. 1 in some embodiments of the invention.
FIG. 2B is a schematic cross-sectional view of an intermediate stage of the method described in FIG. 1 according to some embodiments of the invention.
FIG. 3 is a schematic cross-sectional view of an intermediate stage of the method described in FIG. 1 according to some embodiments of the invention.
FIG. 4 is a schematic cross-sectional view of an intermediate stage of the method described in FIG. 1 according to some embodiments of the invention.
FIG. 5 is a schematic cross-sectional view of an intermediate stage of the method described in FIG. 1 according to some embodiments of the invention.
FIG. 6 is a schematic cross-sectional view of an intermediate stage of the method depicted in FIG. 1 in some embodiments of the invention.
FIG. 7 is a schematic cross-sectional view of an intermediate stage of the method described in FIG. 1 according to some embodiments of the invention.
FIG. 8 is a schematic cross-sectional view of an intermediate stage of the method described in FIG. 1 according to some embodiments of the invention.
FIG. 9 is a schematic cross-sectional view of an intermediate stage of the method described in FIG. 1 according to some embodiments of the invention.
Description of the main reference numerals:
1000-three-dimensional semiconductor structure, 110-first element, 1102-first surface, 1104-back surface, 112-first substrate, 114-first circuit, 1142-first interconnect, 1144-first conductive pad, 116-first interlayer dielectric layer, 118-dielectric via, 120-second element, 1202-second surface, 122-second substrate, 124-second circuit, 1242-second interconnect, 1244-second conductive pad, 126-second interlayer dielectric layer, 128-through silicon, 130-passivation layer, 140-isolation layer, B1-first blind via, B2-second blind via, D1, D2-diameter, I1-first inner wall, I2-second inner wall, P1-first via plug, P2-second via plug, s-method, S1, S2, S3, S4, S5-operation, T1-first temporary end, T2-second temporary end, V1-first through hole, V2-second through hole.
Detailed Description
In order to make the description of the invention more complete and complete, the following description is given for illustrative purposes with respect to embodiments and examples of the invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description.
In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in order to simplify the drawing.
Refer to fig. 1 to 9. Fig. 1 is a flow chart illustrating a method S of forming a three-dimensional semiconductor structure according to some embodiments of the invention. Fig. 2A-9 are schematic cross-sectional views illustrating intermediate stages of the method S depicted in fig. 1 according to some embodiments of the invention. Method S begins with operation S1, where a first element 110 is prepared. The first device 110 has a first circuit 114 and a first interlayer dielectric layer 116, which are disposed on a first substrate 112. The first interlayer dielectric layer 116 surrounds the first circuit 114 and contacts the first substrate 112 (see fig. 2A). In some embodiments, the first circuitry 114 is embedded in the first interlayer dielectric layer 116. In detail, the first interlayer dielectric layer 116 surrounds and contacts the first interconnection 1142 of the first circuit 114. The first conductive pad 1144 of the first circuit 114 is electrically connected to the first interconnection 1142 and contacts the first interlayer dielectric layer 116. In addition, the first conductive pad 1144 is exposed from the first surface 1102 of the first interlayer dielectric layer 116, wherein the first surface 1102 faces away from the first substrate 112. In some embodiments, the first element 110 is fabricated by forming (e.g., depositing) a first circuit 114 and a first interlayer dielectric layer 116 on a first substrate 112.
The method S then proceeds to operation S2, where a via 118 is formed extending from the first surface 1102 of the first ild layer 116 into the first ild layer 116 (see also fig. 2A). The dielectric through hole 118 may be formed by, for example, wet etching or dry etching, but not limited thereto. The method S then proceeds to operation S3, where the first element 110 and the second element 120 are bonded by the first surface 1102 of the first interlayer dielectric layer 116 and the second surface 1202 of the second element 120, so that the through-silicon contact pad 128 exposed from the second surface 1202 of the second element 120 covers the dielectric via 118 (refer to fig. 2B and 3). In some embodiments, the first element 110 and the second element 120 are hybrid bonded (hybrid bonding) such that some of the first conductive pads 1144 of the first circuit 114 are bonded and contact some of the second conductive pads 1244 of the second circuit 124, and the first interlayer dielectric layer 116 is bonded and contact the second interlayer dielectric layer 126 of the second element 120. In some embodiments, a first conductive pad 1144 is exposed from the first surface 1102 and is in contact with a portion of the first interconnect 1142, and a second conductive pad 1244 is exposed from the second surface 1202 and is in contact with a portion of the second interconnect 1242. The first interconnect 1142 and the second interconnect 1242 may be distributed and embedded in the first interlayer dielectric layer 116 and the second interlayer dielectric layer 126, respectively, to form a circuit of a multi-layered circuit. The first and second interconnects 1142, 1242 may also include conductive pads, which connect different circuit layers.
The first interconnect 1142, the second interconnect 1242, the first conductive pad 1144, and the second conductive pad 1244 may include a metal, such as tungsten (W), aluminum (Al), copper (Cu), or a metal silicide, such as tungsten silicide (WSi) or a metal silicide (Cu)2) Titanium disilicide (TiSi)2) Or a metal compound, e.g. tungsten nitride (W)3N2) Titanium nitride (TiN), or polysilicon (poly-Si), or a combination thereof, but not limited thereto.
The first interlayer dielectric layer 116 and the second interlayer dielectric layer 126 may comprise an insulating material, such as silicon dioxide (SiO)2) But not limited thereto.
In some embodiments, the second element 120 is fabricated by forming (e.g., depositing) a second circuit 124 and a second interlayer dielectric layer 126 on the second substrate 122. The second interlayer dielectric layer 126 surrounds the second circuit 124. The through silicon contact pad 128 is exposed from the second surface 1202 of the second interlayer dielectric layer 126, and the second surface 1202 faces away from the second substrate 122.
The first substrate 112 and the second substrate 122 may include a bulk silicon-on-insulator (SOI) wafer, a compound semiconductor such as silicon-germanium (SiGe), or a wafer on which a silicon epitaxial layer is grown, but not limited thereto.
The method S then proceeds to operation S4, where an etching process is performed on the back surface 1104 of the first substrate 112 facing away from the first interlayer dielectric layer 116 to simultaneously form a first via V1 and a second via V2, and expose the through-silicon contact pad 128 through the second via V2 (refer to fig. 3 and 8). In some embodiments, the first via V1 is pre-aligned with one of the first interconnects 1142 described above. The location of the second via V2 is pre-aligned to the through silicon contact pad 128 before the first via V1 and the second via V2 are formed. In some embodiments, after operation S3, the etching process is performed before the etching process is performed from the first substrate 1The back surface 1104 of the substrate 12 partially removes the first substrate 112 (see fig. 4). In some embodiments, the partial removal is by way of silicon polishing, but not limited thereto. By silicon polishing, it is easier to allow the subsequent etching process to etch through the first substrate 112. In some embodiments, the passivation layer 130 is formed on the back surface 1104 of the first substrate 112 before the etching process is performed (refer to fig. 5). After that, a dry etching process may be performed on the back surface 1104 to remove a portion of the passivation layer 130, and then a wet etching process may be performed to form the first and second blind vias B1 and B2 (refer to fig. 6). Note that the operations of removing the foregoing part of the passivation layer 130 and forming the first and second blind vias B1 and B2 are not limited to the above-described processes. In some other embodiments, the removal of the portion of the passivation layer 130 and the formation of the first and second blind vias B1 and B2 may be performed in a single dry etching process. In the aforementioned embodiment, the first temporary end T1 of the first blind via B1 is immediately adjacent to (e.g., extends into the ild layer 116) one of the first interconnects 1142, and the second temporary end T2 of the second blind via B2 is immediately adjacent to (e.g., extends into the ild layer 116) the dielectric via 118. The passivation layer 130 may include silicon dioxide (SiO)2) Silicon nitride (SiN)x) Or an organic material such as benzocyclobutene (BCB), but not limited thereto.
In some embodiments, the isolation layer 140 is conformally formed within the first blind hole B1 and the second blind hole B2 (refer to fig. 7). The isolation layer 140 may include an insulating material, such as, but not limited to, the same material as used for the passivation layer 130. The isolation layer 140 may be formed on the first inner wall I1 in the first blind hole B1 of the first substrate 112, the first temporary terminal T1, the second inner wall I2 in the second blind hole B2 of the first substrate 112, and the second temporary terminal T2, but not limited thereto. After the isolation layer 140 is formed, the rear surface 1104 of the first substrate 112 is then etched to form a first via V1 from the first blind via B1 and a second via V2 from the second blind via B2 (refer to fig. 8). In some embodiments, the isolation layer 140 and the first interlayer dielectric layer 116 are etched until one of the above-mentioned first interconnects 1142 is exposed from the first via V1, and the through silicon contact pad 128 is exposed from the second via V2.
The method S then proceeds to operation S5, where a first via plug P1 is formed to fill the first via V1, and a second via plug P2 is formed to fill the second via V2 and the dielectric via 118. The first and second via plugs P1 and P2 may include a metal, such as tungsten, aluminum, cobalt, nickel, and copper, and/or a metal silicide, but not limited thereto. The first via plug P1 contacts the aforementioned one of the first interconnections 1142 of the first circuit 114, and the second via plug P2 contacts the through silicon contact pad 128. The isolation layer 140 on the first inner wall I1 in the first blind hole B1 and the isolation layer 140 on the second inner wall I2 in the second blind hole B2 prevent contact and direct electrical connection between the first via plug P1 and the first substrate 112, and between the second via plug P2 and the first substrate 112. Through the above processes, the three-dimensional semiconductor structure 1000 (refer to fig. 9) is formed. The above process can simultaneously form the first interconnect 1142 directly electrically connected from the backside 1104 of the first device 110 (via the first via plug P1) and the silicon contact pad 128 directly electrically connected from the backside 1104 of the first device 110 (via the second via plug P2), without using any additional etch delay structure to control the etch rate of the first via V1. In some embodiments, the diameter D1 of the second via V2 is greater than the diameter D2 of the dielectric via 118, thereby preventing possible leakage current between the second via plug P2 and the first substrate 112. In some embodiments, a Chemical Mechanical Polishing (CMP) process is performed on the first and second via plugs P1 and P2 and the passivation layer 130. That is, a chemical mechanical polishing process is performed on the backside 1104 after the first and second via plugs P1 and P2 are formed to planarize the backside 1104.
In summary, embodiments of the present invention provide a method of forming a three-dimensional semiconductor structure, which can simultaneously form an electrical connection to a first element and a second element on one surface of the three-dimensional semiconductor structure by substantially one etching and one deposition process, which eliminates an additional etch delay structure for reducing an etch rate for forming some vias when performing the etching process.
While the present invention has been described with reference to the embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention, and therefore, the scope of the invention is to be determined by the appended claims.

Claims (12)

1. A method of forming a three-dimensional semiconductor structure, comprising:
preparing a first element having a first circuit and a first interlayer dielectric layer disposed on a first substrate, wherein the first interlayer dielectric layer surrounds the first circuit and contacts the first substrate;
forming a dielectric via extending into the first interlayer dielectric layer from a first surface of the first interlayer dielectric layer, wherein the first surface faces away from the first substrate;
bonding the first and second elements through the first and second surfaces of the first interlayer dielectric layer such that through-silicon contact pads exposed from the second surface of the second element cover the dielectric vias; and
performing an etching process on a back surface of the first element to simultaneously form a first via and a second via, and expose the through silicon contact pad through the second via, wherein the back surface faces away from the first interlayer dielectric layer.
2. The method of claim 1, wherein the second component is further prepared by:
forming a second circuit and a second interlayer dielectric layer on a second substrate, wherein the second interlayer dielectric layer surrounds the second circuit, the through silicon contact pad is on the second surface of the second interlayer dielectric layer, and the second surface faces away from the second substrate.
3. The method of claim 2, wherein said bonding comprises:
hybrid bonding the first and second elements such that a first conductive pad of the first circuit is bonded to a second conductive pad of the second circuit, the first interlayer dielectric layer is bonded to the second interlayer dielectric layer, wherein the first conductive pad is exposed from the first surface and is in contact with a portion of a plurality of first interconnects of the first circuit, and the second conductive pad is exposed from the second surface and is in contact with a portion of a plurality of second interconnects of the second circuit.
4. The method of claim 1, further comprising removing the first substrate from the backside portion of the first substrate prior to performing the etching process.
5. The method of claim 4, wherein the partial removal is by silicon grinding.
6. The method of claim 1, further comprising forming a passivation layer on the back side of the first substrate prior to performing the etching process.
7. The method of claim 1, wherein performing the etching process comprises:
etching the back side of the first substrate to form a first blind via and a second blind via, such that a first temporary end of the first blind via is proximate to one of the plurality of first interconnects of the first circuit and a second temporary end of the second blind via is proximate to the through dielectric via;
forming an isolation layer in common in the first and second blind holes; and
etching the back side of the first substrate to form the first via from the first blind via and to form the second via from the second blind via.
8. The method of claim 7, wherein etching the isolation layer is performed by dry etching.
9. The method of claim 7, wherein etching the back side of the first substrate to form the first via from the first blind via and the second via from the second blind via comprises:
the isolation layer and the first interlayer dielectric layer are etched until one of the plurality of first interconnects of the first circuit is exposed from the first via and the through silicon contact pad is exposed from the second via.
10. The method of claim 1, wherein a diameter of the second via is larger than a diameter of the dielectric via.
11. The method of claim 1, wherein the first via and the second via are formed such that one of a plurality of first interconnects of the first circuit is exposed from the first via and the through silicon contact pad is exposed from the second via.
12. The method of claim 1, further comprising:
forming a first via plug to fill the first via, and a second via plug to fill the second via and the through dielectric via, wherein the first via plug contacts one of the plurality of first interconnects of the first circuit, and the second via plug contacts the through silicon contact pad.
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