CN110858536A - Method for forming semiconductor device - Google Patents
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- CN110858536A CN110858536A CN201810974948.5A CN201810974948A CN110858536A CN 110858536 A CN110858536 A CN 110858536A CN 201810974948 A CN201810974948 A CN 201810974948A CN 110858536 A CN110858536 A CN 110858536A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
- H01L24/64—Manufacturing methods
Abstract
The present disclosure provides a method of forming a semiconductor device. The embodiment of the disclosure improves the method for exposing the conducting layer in the through silicon via on the back surface of the semiconductor substrate in the process of the through hole, reduces the size of the semiconductor substrate removed by the grinding and thinning process in the existing process, and increases the size of the semiconductor substrate removed by the selective etching process. Therefore, the semiconductor substrate and the conducting layer do not need to be ground at the same time, the conducting material ions in the conducting layer are prevented from diffusing into the semiconductor substrate, and the yield of products is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
A 3D Integrated Circuit (IC) is defined as a system-level Integrated structure in which a plurality of chips are stacked in a vertical plane direction, thereby saving space. Currently, Through Silicon Vias (TSVs) are mostly used in 3D integrated circuit technology to electrically connect circuits of a plurality of chips in a vertical direction. According to different stages of through silicon via manufacturing processes, the method can be divided into the following steps: three process flows of a front through hole (Via-First), a Middle through hole (Via-Middle) and a Back through hole (Via-Last), wherein The Via-Middle is formed by etching a silicon through hole on a wafer after a Complementary Metal Oxide Semiconductor (CMOS) is manufactured but before a Back end of Line (BEOL). In general, the Via-Middle process can achieve better integration with other processes, and is currently the most common method in the industry.
In the through-hole process, the silicon substrate is thinned by Grinding and Chemical Mechanical Polishing (CMP) to expose the copper pillars in the through-holes, and then the silicon substrate is etched back to make the copper pillars in the through-holes higher than the surface of the silicon substrate. Taking the process of the through silicon via with the depth of 110 μm as an example, firstly, grinding and thinning the substrate to the thickness of 105 μm, then, chemically and mechanically polishing the substrate to the thickness of 103 μm, then, etching back the silicon substrate, generally adopting the process of selective etching, removing part of the semiconductor substrate to the thickness of 98 μm, and finally, depositing an isolation layer and flattening the surface to expose the conductive layer.
However, since the copper pillars in the via structure are exposed during the process of grinding and thinning the semiconductor substrate, copper ions are out-diffused into the substrate during the chemical mechanical polishing. In the subsequent process of etching back the silicon substrate, the silicon substrate around the copper pillar cannot be completely etched due to being covered by copper ions, so that silicon residues as shown in fig. 1 are formed, and a large amount of copper ions exist on the surface of the residual silicon substrate. This causes leakage of the semiconductor device, and reduces the yield of the product.
Disclosure of Invention
In view of the above, the present disclosure provides a method for forming a semiconductor device to improve the yield of the semiconductor device.
The forming method of the semiconductor device provided by the disclosure comprises the following steps:
providing a first semiconductor substrate, wherein a through hole structure is formed on the front surface of the first semiconductor substrate, and the through hole structure comprises a dielectric layer formed at the bottom and the side wall of a through hole and a conductive layer filled on the dielectric layer;
connecting the front side of the first semiconductor substrate to a second semiconductor substrate;
thinning the back surface of the first semiconductor substrate by adopting a first planarization process;
selectively etching the back surface of the first semiconductor substrate, and removing part of substrate material of the first semiconductor substrate to expose the bottom of the through hole structure, wherein the material of the first semiconductor substrate has a higher etching selection ratio relative to the material of the dielectric layer;
depositing an isolation layer on the back of the etched first semiconductor substrate;
and thinning the isolation layer by adopting a second planarization process and removing the dielectric layer at the bottom of the through hole structure to expose the conductive layer in the through hole structure.
Further, the dielectric layer comprises an oxide layer and a barrier layer which are sequentially stacked.
Further, in the selective etching process, the substrate material is removed while the barrier layer is kept unexposed.
Further, the process conditions of the selective etching process are set such that the material of the first semiconductor substrate has a higher etching selectivity ratio with respect to the material of the barrier layer.
Further, the material of the barrier layer is tantalum nitride (TaN) and/or tantalum carbonitride (TaCN).
Further, the conductive structure is made of copper;
the first semiconductor substrate is made of silicon, and the through hole structure is a silicon through hole.
Further, the first planarization process thins the thickness of the back surface of the first semiconductor substrate so that the via structure is not exposed.
Further, the first planarization process includes grinding thinning and chemical mechanical polishing.
Further, the method for selectively etching the first semiconductor substrate comprises one or more times of deep reactive ion etching.
Further, the method for depositing the isolation layer is to alternately deposit an oxide layer and a nitride layer.
Further, the second planarization process is chemical mechanical polishing.
Further, the etching depth of the selective etching is configured to make the height of the etched first semiconductor substrate smaller than the height of the conductive layer.
The embodiment of the disclosure improves the method for exposing the conducting layer in the through silicon via on the back surface of the semiconductor substrate in the process of the through hole, reduces the size of the semiconductor substrate removed by the grinding and thinning process in the existing process, and increases the size of the semiconductor substrate removed by the selective etching process. Therefore, the semiconductor substrate and the conducting layer do not need to be ground at the same time, conducting ions in the conducting layer are prevented from diffusing into the semiconductor substrate, and the yield of products is improved.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a through silicon via formed by a prior art process;
fig. 2 is a flow chart of a method of forming a semiconductor device of an embodiment of the present disclosure;
fig. 3 to 9 are schematic cross-sectional views of structures formed at respective steps of a method of forming a semiconductor substrate according to an embodiment of the present disclosure.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, "multi-layer" means two or more layers unless otherwise specified.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Spatial relationship terms such as "below …", "below", "lower", "above …", "above", and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may assume other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.
Fig. 2 is a flowchart of a method of forming a semiconductor device of an embodiment of the present disclosure, and referring to fig. 2, the method of forming an embodiment of the present disclosure includes the steps of:
step S100, providing a first semiconductor substrate. And a through hole structure is formed on the front surface of the first semiconductor substrate, and the through hole structure comprises a dielectric layer formed at the bottom and the side wall of the through hole and a conductive layer filled on the dielectric layer.
Step S200 of connecting the front surface of the first semiconductor substrate to the second semiconductor substrate.
And step S300, thinning the back surface of the first semiconductor substrate by adopting a first planarization process.
Step S400, performing selective etching on the back surface of the first semiconductor substrate, and removing part of substrate material of the first semiconductor substrate to expose the bottom of the through hole structure, wherein the material of the first semiconductor substrate has a higher etching selectivity ratio relative to the material of the dielectric layer;
step S500, depositing an isolation layer on the back surface of the etched first semiconductor substrate.
And S600, thinning the oxidation isolation layer by adopting a second planarization process and removing the dielectric layer at the bottom of the through hole structure to expose the conductive layer in the through hole structure.
Fig. 3 to 9 are schematic cross-sectional views of structures formed at respective steps of a method of forming a semiconductor substrate according to an embodiment of the present disclosure. Fig. 3 is a schematic cross-sectional view of the first semiconductor substrate 100. Referring to fig. 3, in step S100, a first semiconductor substrate 100 is provided. The first semiconductor substrate 100 comprises a front surface 101 and a back surface 102, wherein the front surface 101 of the first semiconductor substrate 100 is formed with a via structure 300, and the via structure 300 comprises a dielectric layer 310 formed on the bottom and the sidewall of a via and a conductive layer 320 filled on the dielectric layer 310. In this embodiment, the depth of the through hole is 110 μm.
The first semiconductor substrate 100 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the first semiconductor substrate 100 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-silicon-germanium (S-SiGeOI), a silicon-on-insulator-silicon-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. Preferably, the first semiconductor substrate 100 is a silicon single crystal substrate. Structures such as a plurality of epitaxial interface layers or strain layers can also be formed on the surface of the first semiconductor substrate 100 to improve the electrical performance of the semiconductor device. Isolation regions are formed in the first semiconductor substrate 100. As an example, the isolation region is a Shallow Trench Isolation (STI) region or a local oxidation of silicon (LOCOS) isolation region. The isolation region may divide the first semiconductor substrate 100 into several active regions, etc., which are not shown in the drawing for simplicity.
The dielectric layer 310 in the via structure 300 includes an oxide layer 311 and a barrier layer 312 stacked in sequence. Wherein the oxide layer 311 is located at the bottom of the via structure, and the barrier layer 312 is formed on the oxide layer 311. The oxide layer 311 may serve to protect the conductive layer 320 from being etched in a subsequent etching process for etching the first semiconductor substrate 100. The material of the oxide layer 311 may be silicon oxide (SiO)2) Etc. insulating material. The barrier layer 312 functions to block ions in the conductive layer 320 from diffusing into the first semiconductor substrate 100. The material of the barrier layer 312 may include any one of tantalum nitride (TaN) or tantalum carbonitride (TaCN), or a combination thereof, and it is understood that other materials such as silicon oxynitride (SiON), tantalum (Ta), silicon nitride (SiN), etc., which function to block diffusion of conductive ions in the conductive layer 320, may also be used. The conductive layer 320 electrically connects the first semiconductor substrate 100 and the second semiconductor substrate 200 to each other in a subsequent process. The material of the conductive layer 320 may be a metal material, such as any one of copper (Cu), iron (Fe), aluminum (Al), tungsten (W), and sodium (Na), or a combination thereof, or may be a conductive polymer, a metal silicide, or the like.
The via structure 300 may be formed by a through silicon via process. In particular, in an alternative implementationThe method for forming the via structure 300 in the first semiconductor substrate 100 includes: first, a via hole is formed on the front surface 101 of the first semiconductor substrate 100, which via hole can be formed by a dry etching method, preferably a reactive ion etching method. As an example, the depth of the through hole is 110 μm, and the bottom of the through hole has a certain distance from the back surface 102 of the semiconductor substrate 100. Then, a dielectric layer 310 is formed on the sidewall and the bottom of the via, wherein the dielectric layer 310 includes a barrier layer 312 made of tantalum nitride (TaN) and a silicon oxide (SiO) layer2) Oxide layer 311. Finally, the surface of the dielectric layer 310 is filled with a conductive layer 320 made of copper (Cu), and the front surface 101 of the first semiconductor substrate 100 is subjected to a chemical mechanical polishing process to make the front surface 101 of the first semiconductor substrate 100 flat.
It should be understood that the figures of the present disclosure illustrate only one via structure 300 in the first semiconductor substrate 100 as an example, and in fact a plurality of via structures 300 may be formed in the first semiconductor substrate 100.
Referring to fig. 4, in step S200, the front surface 101 of the first semiconductor substrate 100 is connected to the second semiconductor substrate 200. Specifically, the method of connecting the front surface 101 of the first semiconductor substrate 100 to the second semiconductor substrate 200 includes: a second semiconductor substrate 200 is provided, and the second semiconductor substrate 200 may be formed with devices such as active devices, Micro-Electromechanical Systems (Micro-Electromechanical Systems MEMS) devices, inertial sensors, and interconnect structures, or may be formed with CMOS image sensors. In the present embodiment, the second semiconductor substrate 200 is a MEMS device. A first Bonding layer and a second Bonding layer (not shown in the figure) are formed on the front surface 101 of the first semiconductor substrate 100 and the front surface of the second semiconductor substrate, respectively, and then Thermal Compression Bonding (TCB) is selected or the first Bonding layer and the second Bonding layer are eutectic bonded into a whole by van der waals force.
Referring to fig. 5, in step S300, the back surface 102 of the first semiconductor substrate 100 is thinned using a first planarization process. In an alternative implementation, the back surface 102 of the first semiconductor substrate 100 is first thinned by Grinding (thinning) to make the thickness of the first semiconductor substrate 100 be 115 μm, and then the back surface 102 of the first semiconductor substrate 100 is thinned by Chemical Mechanical Polishing (CMP) to make the thickness of the first semiconductor substrate 100 be 113 μm.
Unlike the prior art process in which the conductive layer is exposed during the grinding thinning process, the embodiment of the present disclosure reduces the size of the back surface 102 of the semiconductor substrate removed by the grinding thinning process, thereby ensuring that the conductive layer 320 is wrapped by the dielectric layer 310 and conductive ions do not diffuse into the first semiconductor substrate 100 during the first planarization process.
Referring to fig. 6 and 7, in step S400, selective etching is performed on the back surface 102 of the first semiconductor substrate 100. Removing a portion of the substrate material of the first semiconductor substrate 100 exposes the bottom of the via structure 300, and the height of the first semiconductor substrate 100 is less than the height of the conductive layer 320. During the selective etching process, the material of the first semiconductor substrate 100 has a higher etching selectivity ratio with respect to the material of the dielectric layer.
Preferably, a Deep Reactive Ion Etch (DRIE) method is selected to remove a portion of the substrate material of the first semiconductor substrate 100 in this step, while leaving a portion of the dielectric layer 310 in the via structure 300 that is not etched or is etched only a small amount, so that the barrier layer 312 wrapped by the oxide layer 311 is not exposed. Reactive ion etching is a device which utilizes active groups generated by high-frequency glow discharge to perform chemical reaction with corroded materials to form volatile products so that atoms on the surface of a sample fall off from crystal lattices, and thus, the preparation of a fine pattern on the surface of the sample is realized. The selection of deep reactive ion etching can maintain a very high etching selectivity. In an alternative implementation, the thickness of the back surface 102 of the first semiconductor substrate 100 is removed by etching, and due to the high selectivity of the deep reactive ion etching, the first semiconductor substrate 100 made of silicon is etched, but the oxide layer 311 at the bottom of the via structure 300 is not affected by the etching, and the via structure 300 remains, so that the height of the conductive layer 320 is greater than the thickness of the first semiconductor substrate 100 after etching, thereby ensuring that the chemical mechanical polishing can expose the conductive layer 320 before the subsequent deposition of the isolation layer 400, and the back surface 102 of the first semiconductor substrate 100 is still covered by the isolation layer 400. Due to the non-uniformity and variability of the etching rate, the surface of the etched first semiconductor substrate 100 is not uniform, and the uniformity is worse when the etching depth is larger. Preferably, the etching may be divided into a plurality of times to improve the uniformity of the surface of the first semiconductor substrate 100. In consideration of etching efficiency, two times of deep reactive ion etching may be employed to remove a portion of the substrate material of the first semiconductor substrate 100, each time the etching depth is 5 μm.
In an alternative implementation, two deep reactive ion etches remove a portion of the substrate material of the first semiconductor substrate 100, each etch being 5 μm deep. The process conditions of the deep reactive ion etching are as follows: selecting gaseous silicon hexafluoride (SF)6) And applying a radio frequency power supply as a process gas to ensure that the reaction gas of the silicon hexafluoride forms high ionization, wherein the working pressure is controlled to be 20 mTorr-8 Torr, the power is 2000W, the frequency is 13.5MHz, and the direct current bias can be continuously controlled within-500V-1000V in the etching step, thereby ensuring the requirement of anisotropic etching. The deep reactive ion etching system can be selected from equipment commonly used in the field and is not limited to a certain model.
Compared with the prior art, the via structure 300 remains in the first semiconductor substrate 100 after the grinding and thinning process, and conductive ions in the conductive layer 320 are prevented from diffusing into the first semiconductor substrate 100 in the process. In the process of selectively etching the first semiconductor substrate 100, the thickness of the first semiconductor substrate 100 removed by selective etching according to the embodiment of the present disclosure is increased, and deep reactive ion etching with a high etching selectivity is selected to ensure that the via structure 300 is not etched, and the conductive layer 320 is wrapped by the dielectric layer 310, so that the phenomenon that conductive ions in the conductive layer 320 diffuse into the first semiconductor substrate 100 does not occur. Meanwhile, the first semiconductor substrate 100 is etched by a multiple deep reactive ion etching method to ensure the uniformity of etching.
Referring to fig. 8, in step S500, an isolation layer 400 is deposited on the back surface 102 of the etched first semiconductor substrate 100. The isolationThe layer 400 covers the back surface 102 of the first semiconductor substrate 100 and the upper surface and sidewalls of the portion of the via structure 300 above the first semiconductor substrate 100, and the lower surface of the isolation layer 400 is below the bottom of the conductive layer 320 in the via structure 300. The material of the isolation layer may be silicon oxide (SiO)2) Or silicon nitride (SiN), etc., preferably, the isolation layer 400 is an ONO isolation layer, i.e., a plurality of silicon oxide (SiO) layers alternately stacked2) A layer and a silicon nitride (SiN) layer. The ONO spacer may be formed by alternately depositing oxide and nitride layers multiple times. The Deposition method of the isolation layer 400 can be any conventional method known to those skilled in the art, and preferably a Chemical Vapor Deposition method (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), etc., is used.
Referring to fig. 9, in step S600, the isolation layer 400 is thinned and the dielectric layer 310 at the bottom of the via structure 300 is removed by using a second planarization process to expose the conductive layer 320 in the via structure. The second planarization process may be performed by a process known to those skilled in the art, preferably by chemical mechanical polishing to planarize the surface of the isolation layer 400 and remove the dielectric layer 310 at the bottom of the via structure 300. The isolation layer 400 is formed to cover the back surface 102 of the first semiconductor substrate 100 and expose the conductive layer 320 of the via structure 300 and the dielectric layer 310 outside the conductive layer 320.
Different from the prior art that the conductive layer 320 is exposed during the process of chemically and mechanically polishing the first semiconductor substrate 100, the embodiment of the disclosure exposes the conductive layer 320 during the process of chemically and mechanically polishing the isolation layer 400 after the isolation layer 400 is formed, and because the isolation layer 400 can prevent the conductive ions in the conductive layer 320 from diffusing compared with the first semiconductor substrate 100, the condition that the conductive ions in the conductive layer 320 diffuse into the first semiconductor substrate 100 during the process of chemically and mechanically polishing the first semiconductor substrate 100 to cause the electric leakage of the semiconductor device is avoided, and the yield of the product is improved.
In subsequent processes, a dielectric material layer is deposited on the isolation layer 400, the dielectric material layer is patterned, and a conductive material is deposited in the patterned dielectric material layer to form an interconnection structure, so that the first semiconductor substrate 100 and the second semiconductor substrate 200 are electrically connected.
The embodiment of the disclosure improves the method for exposing the conducting layer in the through silicon via on the back surface of the semiconductor substrate in the process of the through hole, reduces the size of the semiconductor substrate removed by the grinding and thinning process in the existing process, and increases the size of the semiconductor substrate removed by the selective etching process. Therefore, the semiconductor substrate and the conducting layer do not need to be ground at the same time, conducting ions in the conducting layer are prevented from diffusing into the semiconductor substrate, and the yield of products is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. A method of forming a semiconductor device, comprising:
providing a first semiconductor substrate, wherein a through hole structure is formed on the front surface of the first semiconductor substrate, and the through hole structure comprises a dielectric layer formed at the bottom and the side wall of a through hole and a conductive layer filled on the dielectric layer;
connecting the front side of the first semiconductor substrate to a second semiconductor substrate;
thinning the back surface of the first semiconductor substrate by adopting a first planarization process;
selectively etching the back surface of the first semiconductor substrate, and removing part of substrate material of the first semiconductor substrate to expose the bottom of the through hole structure, wherein the material of the first semiconductor substrate has a higher etching selection ratio relative to the material of the dielectric layer;
depositing an isolation layer on the back of the etched first semiconductor substrate;
and thinning the isolation layer by adopting a second planarization process and removing the dielectric layer at the bottom of the through hole structure to expose the conductive layer in the through hole structure.
2. The method of claim 1, wherein the dielectric layer comprises an oxide layer and a barrier layer stacked in sequence.
3. The method of claim 2, wherein the substrate material is removed while leaving the barrier layer unexposed during the selective etching process.
4. The method according to claim 2, characterized in that the process conditions of the selective etching process are set such that the material of the first semiconductor substrate has a higher etch selectivity ratio with respect to the barrier material.
5. The method according to claim 2, wherein the material of the barrier layer is tantalum nitride (TaN) and/or tantalum carbonitride (TaCN).
6. The method of claim 1, wherein the conductive structure is copper;
the material of the first semiconductor substrate is silicon; the through hole structure is a through silicon via.
7. The method of claim 1, wherein the first planarization process thins the thickness of the backside of the first semiconductor substrate is controlled such that the via structure is not exposed.
8. The method of claim 1, wherein the first planarization process comprises abrasive thinning and chemical mechanical polishing.
9. The method of claim 1, wherein the method of selectively etching the first semiconductor substrate comprises one or more deep reactive ion etches.
10. The method of claim 1, wherein the spacer layer is deposited by alternately depositing an oxide layer and a nitride layer.
11. The method of claim 1, wherein the second planarization process is chemical mechanical polishing.
12. The method of claim 1, wherein an etch depth of the selective etch is configured such that a height of the etched first semiconductor substrate is less than a height of the conductive layer.
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| CN111681949B (en) * | 2020-06-22 | 2021-05-18 | 长江存储科技有限责任公司 | Method for processing back of wafer |
| CN113035829A (en) * | 2021-03-04 | 2021-06-25 | 复旦大学 | TSV passive adapter plate and manufacturing method thereof |
| CN116314016A (en) * | 2023-04-26 | 2023-06-23 | 北京大学 | Submicron-sized through silicon via structure, preparation method thereof and electronic equipment |
| CN116314016B (en) * | 2023-04-26 | 2023-10-03 | 北京大学 | Submicron-sized through silicon via structure, preparation method thereof and electronic equipment |
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