CN104143526A - Method for manufacturing through-silicon-via structure - Google Patents
Method for manufacturing through-silicon-via structure Download PDFInfo
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- CN104143526A CN104143526A CN201310169431.6A CN201310169431A CN104143526A CN 104143526 A CN104143526 A CN 104143526A CN 201310169431 A CN201310169431 A CN 201310169431A CN 104143526 A CN104143526 A CN 104143526A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
The invention discloses a method for manufacturing a through-silicon-via structure. The method comprises the steps of providing a silicon substrate, wherein the silicon substrate is provided with a front surface and a back surface opposite to the front surface, the front surface of the silicon substrate is provided with a through hole, the through hole extends to the back surface of the silicon substrate, a dielectric layer and a barrier layer are sequentially deposited on the inner wall of the through hole, and then the through hole is filled with metal; thinning the back surface of the silicon substrate initially; carrying out wet etching on the back surface of the silicon substrate and stopping wet etching before the portion, on the bottom of the through hole, of the dielectric layer is exposed; carrying out dry gas-phase etching on the back surface of the silicon substrate till a part of metal, barrier layer and dielectric layer deposited on the bottom of the through hole protrude out of the back surface of the silicon substrate, wherein the portion, on the bottom of the through hole, of the dielectric layer is exposed; depositing a passivation layer on the back surface of the silicon substrate except the bottom of the through hole; removing the portion, on the bottom of the through hole, of the dielectric layer; removing the portion, on the bottom of the through hole, of the barrier layer through the dry gas-phase etching method, wherein the portion, on the bottom of the through hole, of the metal is exposed out of the back surface of the silicon substrate. According to the method, the back surface of the silicon substrate is thinned and the portion, on the bottom of the through hole, of the barrier layer is removed through the dry gas-phase etching method, and therefore the manufacturing yield of the through-silicon-via structure is increased.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, relate in particular to a kind of through-silicon-via construction manufacturing method.
Background technology
Along with complete electronic set system is constantly to light, thin, little future development, to the integrated level of integrated circuit, require also more and more higher.At present, the integrated level that improves integrated circuit is mainly to take to reduce characteristic size, and making in given area can integrated more element, belongs to two dimension integrated.Yet when the structure of integrated circuit is day by day complicated, when the function that requires to possess is become stronger day by day, the limitation of two-dimentional integrated technology highlights gradually.Therefore, need seek new integrated technology to improve the integrated level of integrated circuit.
Three-dimensional integration technology based on through-silicon-via technology has become the most noticeable a kind of new technology of integrated level that instantly improves integrated circuit.Three-dimensional integration technology utilizes through-silicon-via (TSV) to realize the interconnection of stacked chips in integrated circuit.TSV can make that chip is maximum in the stacking density of three-dimensional, the interconnection line between chip is the shortest, overall dimension is minimum, and can greatly improve the performance of chip speed and low-power consumption.
TSV structure fabrication technique mainly comprises formation, silicon substrate attenuate and the TSV bonding of through hole.Specifically comprise: in the front of silicon substrate, make through hole, through hole extends to the back side of silicon substrate, metal is then filled on metallization medium layer and barrier layer successively in through hole in through hole; By the thinning back side of silicon substrate to the dielectric layer that exposes via bottoms place; Last dielectric layer and barrier layer of removing successively via bottoms place, the metal at via bottoms place exposes from the back side of silicon substrate, to obtain and be electrically connected to another layer of chip, thereby realizes the interconnection of chip chamber.
In above-mentioned TSV structure fabrication process, the mode that silicon substrate attenuate adopts mechanical lapping and wet etching to combine conventionally.Particularly, first adopt mechanical lapping to carry out preliminary attenuate, because mechanical lapping meeting produces scratch to surface of silicon, after mechanical lapping, surface of silicon situation is not fine, thereby, need to adopt again wet etching to process surface of silicon, when improving surface of silicon situation, silicon substrate is carried out to the dielectric layer that exposes via bottoms place that is thinned to a certain degree.The etching liquid of wet etching is generally selected the mixed liquor of KOH, HF and nitric acid and TMAH solvent etc.Although this etching liquid can be removed silicon substrate, lower to the selection of dielectric layer material, the dielectric layer material of conventionally choosing is silica.Thereby this etching liquid easily produces etching to dielectric layer, even penetrates dielectric layer, cause the making yield of TSV structure to reduce.
In addition, what the dielectric layer at via bottoms place and the removal on barrier layer adopted is cmp (CMP) method, the method is when removing barrier layer, if it is accurate not that terminal is controlled grasp, metal in through hole also can be worn away and corrode, thereby the metal mixed being worn away can cause metal ion to be diffused in silicon substrate in lapping liquid, and then causes the inefficacy of TSV structure.
Summary of the invention
The defect that the object of the invention is to exist for above-mentioned background technology provides a kind of TSV construction manufacturing method that can improve TSV structure fabrication yield.
For achieving the above object, a kind of through-silicon-via construction manufacturing method provided by the invention, comprise the steps: to provide a silicon substrate, silicon substrate have front and with the back side of vis-a-vis, the front of silicon substrate is formed with through hole, through hole extends to the back side of silicon substrate, at the inwall of through hole successively metallization medium layer and barrier layer, then in through hole, fills metal; Preliminary attenuate is carried out in the back side of silicon substrate; Wet etching is carried out in the back side of silicon substrate, and stopped wet etching before the dielectric layer at via bottoms place is exposed; Dry method gas phase etching is carried out in the back side of silicon substrate, until metal, barrier layer and the dielectric layer of a part for via bottoms place deposition are protruding from the back side of silicon substrate, wherein the dielectric layer at via bottoms place is exposed; Part deposit passivation layer at the back side of silicon substrate except via bottoms; Remove the dielectric layer at via bottoms place; And adopting dry method gas phase etching method to remove the barrier layer at via bottoms place, the metal at via bottoms place exposes from the back side of silicon substrate.
In one embodiment, behind the inwall of through hole successively metallization medium layer and barrier layer, on barrier layer, deposit stress absorbing layer, and then fill metal in through hole.When adopting dry method gas phase etching method to remove the barrier layer at via bottoms place, and then the stress absorbing layer at via bottoms place is removed.The material of stress absorbing layer is tungsten, tungsten nitride, tantalum or titanium.
In such scheme, the step that adopts dry method gas phase etching method to remove the barrier layer at via bottoms place further comprises: adopt xenon difluoride gas to remove the barrier layer at via bottoms place.
In such scheme, the step of removing the dielectric layer at via bottoms place further comprises: adopt HF gas to remove the dielectric layer at via bottoms place.
In such scheme, the material of passivation layer is SiC, SiN, SiCN or their mixture.
In such scheme, dry method gas phase etching is carried out to until metal, barrier layer and the dielectric layer of a part for via bottoms place deposition further comprise from the step of the back side projection of silicon substrate in the back side of silicon substrate: adopt the mist of xenon difluoride gas or the same nitrogen of xenon difluoride gas, hydrogen fluoride gas or steam to carry out gas phase etching to the back side of silicon substrate.
In such scheme, metal, barrier layer and the dielectric layer of a part for via bottoms place deposition adopts the method for terminal control to control from the height of the back side projection of silicon substrate, wherein when dielectric layer being detected, be the terminal of gas phase etching, and then continue one time period of etching, by controlling the described time period, control through hole from the height of the back side projection of silicon substrate.
In sum; the present invention is by adopting the back side of dry method gas phase etching attenuate silicon substrate and the barrier layer at removal via bottoms place; can be good at protecting the metal in the injury-free and through hole of dielectric layer in through hole be not worn away or corrode, thereby improved TSV structure fabrication yield.
Accompanying drawing explanation
Fig. 1 is the flow chart of an embodiment of through-silicon-via construction manufacturing method of the present invention.
Fig. 2 to Fig. 8 is the cross-sectional view of each processing step of an embodiment of through-silicon-via construction manufacturing method of the present invention.
Fig. 9 is the cross-sectional view of processing step of the another embodiment of through-silicon-via construction manufacturing method of the present invention.
Embodiment
By describing technology contents of the present invention in detail, being reached object and effect, below in conjunction with embodiment and coordinate graphic detailed description in detail.
Refer to Fig. 1 and Fig. 2 to Fig. 8, disclosed an embodiment of TSV construction manufacturing method of the present invention, according to this embodiment, TSV construction manufacturing method of the present invention comprises the steps:
S001: as shown in Figure 2, first one silicon substrate 100 is provided, silicon substrate 100 have front and with the back side of vis-a-vis, the front of silicon substrate 100 is formed with through hole and integrated circuit (IC)-components, through hole extends to the back side of silicon substrate 100, at the inwall of through hole successively metallization medium layer 101 and barrier layer 102, then in through hole, fill metal 103.Wherein, preferred, the material of dielectric layer 101 is silica, and the material on barrier layer 102 is tantalum, tantalum nitride, titanium, titanium nitride or their mixture, and the material of metal 103 is copper.In order further to guarantee conventionally also to need to provide a silicon chip or sheet glass as carrying tablet 200 by the making yield of TSV structure, carrying tablet 200 is bonded together with the front of silicon substrate 100, in the process of making TSV structure, carries silicon substrate 100.Before using TSV electrical connection upper strata chip and lower floor's chip, carrying tablet 200 is peeled off from silicon substrate 100.
S002: as shown in Figure 3, preliminary attenuate is carried out in the back side of silicon substrate 100, conventionally adopt the method for mechanical lapping or cmp that silicon substrate 100 is thinned to 50-250 micron, after attenuate the thickness of silicon substrate 100 according to the degree of depth of through hole requirements different from other parameters determine.
S003: as shown in Figure 4, after preliminary attenuate, wet etching is carried out in the back side of silicon substrate 100, when improving silicon substrate 100 surface uniformities and roughness, further attenuate is carried out in the back side of silicon substrate 100, now, apart from the dielectric layer 101 at via bottoms place, still have certain distance.The etching liquid of wet etching can be selected, for example, and KOH, the mixed liquor of HF and nitric acid, TMAH solvent.Before the dielectric layer 101 at via bottoms place is exposed, stop wet etching.
S004: as shown in Figure 5, after wet etching, dry method gas phase etching is carried out in the back side of silicon substrate 100, until metal 103, barrier layer 102 and the dielectric layer 101 of a part for via bottoms place deposition are from the back side projection of silicon substrate 100, the height H of projection is 1-10 micron, and then the dielectric layer 101 at via bottoms place is exposed.Particularly, due to xenon difluoride and silicon spontaneous generation chemical reaction at normal temperatures, therefore, preferably, adopt the mist of xenon difluoride gas or the same nitrogen of xenon difluoride gas, hydrogen fluoride gas or steam to carry out gas phase etching to the back side of silicon substrate 100.Metal 103, barrier layer 102 and the dielectric layer 101 of a part for via bottoms place deposition can adopt the method for terminal control to control from the height H of the back side projection of silicon substrate 100, when dielectric layer 101 being detected, the back side of silicon substrate 100 flushes with the dielectric layer 101 at via bottoms place, now, metal 103, barrier layer 102 and the dielectric layer 101 of a part for via bottoms place deposition have just exposed.In gas phase etching process, can using the reference point of this time point as etching technics terminal, according to the height of metal 103, barrier layer 102 and the dielectric layer 101 actual needs projections of a part for via bottoms place deposition, determine further to continue the time period of etching, in continuing the process of etching, gas flow and other technological parameters remain unchanged, and control metal 103, barrier layer 102 and the dielectric layer 101 of a part of via bottoms place deposition from the height H of the back side projection of silicon substrate 100 by control time section.Dry method gas phase etching only can be removed silicon substrate 100, and does not react with dielectric layer 101, thereby it is injury-free to can be good at protective dielectric layer 101.
S005: as shown in Figure 6; part to the back side of silicon substrate 100 except via bottoms is carried out Passivation Treatment; the i.e. part deposit passivation layer 104 except via bottoms at the back side of silicon substrate 100, to protect the back side of silicon substrate 100 not to be further etched in subsequent technique.For example, can be first at backside deposition one deck passivation layer 104 of silicon substrate 100, then, apply again one deck photoresist, then the back side of silicon substrate 100 is anti-carved to erosion, to remove the passivation layer 104 at via bottoms place, and passivation layer 104 on the region of the back side that guarantees silicon substrate 100 except via bottoms is not destroyed.Finally again photoresist is removed.The material of passivation layer 104 can be SiC, SiN, SiCN or their mixture.
S006: as shown in Figure 7, then, remove the dielectric layer 101 at via bottoms place, the method for employing can be dry method gas phase etching or wet etching.Particularly, can adopt HF gas to remove the dielectric layer 101 at via bottoms place.
S007: as shown in Figure 8, last, remove the barrier layer 102 at via bottoms place, the metal 103 at via bottoms place exposes from the back side of silicon substrate 100, to obtain and be electrically connected to chip, thereby realizes the interconnection of chip chamber.The method of removing the barrier layer 102 at via bottoms place is dry method gas phase etching, particularly, can adopt xenon difluoride gas to remove the barrier layer 102 at via bottoms place.According to different process requirements, passivation layer 104 can retain or remove.Compare with existing chemical mechanical milling method, the barrier layer 102 that adopts dry method gas phase etching method to remove via bottoms place can avoid the metal 103 in through hole be worn away or corrode.
Refer to Fig. 9, in order to eliminate through hole stress around, behind the inwall of through hole successively metallization medium layer 101 and barrier layer 102, preferably, on barrier layer 102, deposit stress absorbing layer 105, and then fill metal 103 in through hole.While in the end removing the barrier layer 102 at via bottoms place, and then the stress absorbing layer at via bottoms place 105 is removed.The material of stress absorbing layer 105 can be tungsten, tungsten nitride, tantalum, titanium etc.
From the above, TSV construction manufacturing method of the present invention, by adopting the back side of dry method gas phase etching attenuate silicon substrate 100 and the barrier layer 102 at removal via bottoms place, has improved TSV structure fabrication yield.
In sum, TSV construction manufacturing method of the present invention illustrates by above-mentioned execution mode and correlative type, the exposure that oneself is concrete, full and accurate correlation technique, those skilled in the art can be implemented according to this.And the above embodiment is just used for illustrating the present invention, rather than be used for limiting of the present invention, interest field of the present invention, should be defined by claim of the present invention.
Claims (9)
1. a through-silicon-via construction manufacturing method, is characterized in that, comprises the steps:
One silicon substrate is provided, silicon substrate have front and with the back side of vis-a-vis, the front of silicon substrate is formed with through hole, through hole extends to the back side of silicon substrate, at the inwall of through hole successively metallization medium layer and barrier layer, then in through hole, fills metal;
Preliminary attenuate is carried out in the back side of silicon substrate;
Wet etching is carried out in the back side of silicon substrate, and stopped wet etching before the dielectric layer at via bottoms place is exposed;
Dry method gas phase etching is carried out in the back side of silicon substrate, until metal, barrier layer and the dielectric layer of a part for via bottoms place deposition are protruding from the back side of silicon substrate, wherein the dielectric layer at via bottoms place is exposed;
Part deposit passivation layer at the back side of silicon substrate except via bottoms;
Remove the dielectric layer at via bottoms place; And
Adopt dry method gas phase etching method to remove the barrier layer at via bottoms place, the metal at via bottoms place exposes from the back side of silicon substrate.
2. through-silicon-via construction manufacturing method according to claim 1, is characterized in that, further comprises: behind the inwall of through hole successively metallization medium layer and barrier layer, deposit stress absorbing layer, and then fill metal on barrier layer in through hole.
3. through-silicon-via construction manufacturing method according to claim 2, is characterized in that, when adopting dry method gas phase etching method to remove the barrier layer at via bottoms place, and then the stress absorbing layer at via bottoms place is removed.
4. through-silicon-via construction manufacturing method according to claim 2, is characterized in that, the material of described stress absorbing layer is tungsten, tungsten nitride, tantalum or titanium.
5. according to the through-silicon-via construction manufacturing method described in claim 1 or 3, it is characterized in that, the step that described employing dry method gas phase etching method is removed the barrier layer at via bottoms place further comprises: adopt xenon difluoride gas to remove the barrier layer at via bottoms place.
6. through-silicon-via construction manufacturing method according to claim 1, is characterized in that, the step of the dielectric layer at described removal via bottoms place further comprises: adopt HF gas to remove the dielectric layer at via bottoms place.
7. through-silicon-via construction manufacturing method according to claim 1, is characterized in that, the material of described passivation layer is SiC, SiN, SiCN or their mixture.
8. through-silicon-via construction manufacturing method according to claim 1, it is characterized in that, described dry method gas phase etching is carried out to until metal, barrier layer and the dielectric layer of a part for via bottoms place deposition further comprise from the step of the back side projection of silicon substrate in the back side of silicon substrate: adopt the mist of xenon difluoride gas or the same nitrogen of xenon difluoride gas, hydrogen fluoride gas or steam to carry out gas phase etching to the back side of silicon substrate.
9. through-silicon-via construction manufacturing method according to claim 1, it is characterized in that, metal, barrier layer and the dielectric layer of a part for described via bottoms place deposition adopts the method for terminal control to control from the height of the back side projection of silicon substrate, wherein when dielectric layer being detected, be the terminal of gas phase etching, and then continue one time period of etching, by controlling the described time period, control through hole from the height of the back side projection of silicon substrate.
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| CN106455391A (en) * | 2016-09-28 | 2017-02-22 | 东莞劲胜精密组件股份有限公司 | 3C electronic product housing and preparation method thereof |
| CN110473826A (en) * | 2018-05-09 | 2019-11-19 | 联华电子股份有限公司 | The manufacturing method of semiconductor structure |
| CN110858536A (en) * | 2018-08-24 | 2020-03-03 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN111799177A (en) * | 2020-07-14 | 2020-10-20 | 通富微电子股份有限公司技术研发分公司 | Method for manufacturing semiconductor device |
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| CN111799177A (en) * | 2020-07-14 | 2020-10-20 | 通富微电子股份有限公司技术研发分公司 | Method for manufacturing semiconductor device |
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Address after: 201203 building 4, No. 1690, Cailun Road, free trade zone, Pudong New Area, Shanghai Patentee after: Shengmei semiconductor equipment (Shanghai) Co., Ltd Address before: 201203 Shanghai Zhangjiang High Tech Park of Pudong New Area Cailun Road No. 4 1690 Patentee before: ACM (SHANGHAI) Inc. |