CN105428309A - Manufacturing technological method for TSV through hole, and manufacturing technological method for blind hole or TSV through hole of multiple hole depths - Google Patents
Manufacturing technological method for TSV through hole, and manufacturing technological method for blind hole or TSV through hole of multiple hole depths Download PDFInfo
- Publication number
- CN105428309A CN105428309A CN201510940285.1A CN201510940285A CN105428309A CN 105428309 A CN105428309 A CN 105428309A CN 201510940285 A CN201510940285 A CN 201510940285A CN 105428309 A CN105428309 A CN 105428309A
- Authority
- CN
- China
- Prior art keywords
- wafer
- tsv
- hole
- barrier layer
- blind hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing technological method for a TSV through hole. The manufacturing technological method comprises the following steps: providing a wafer and depositing a barrier layer on the surface of the wafer; performing photoetching and etching processes on the surface of the wafer, removing a part of the barrier layer, wherein the removed part is not used as the TSV region, and forming barrier layer protruding points in the TSV region; forming a shape with an RDL wire casing in the surface of the wafer through the photoetching and etching processes; depositing an insulating layer on the surface of the wafer; making a metal layer on the insulating layer on the surface of the wafer, and forming metal RDL in the RDL wire casing; depositing a protection layer on the metal layer on the surface of the wafer; performing CMP grinding on the surface of the wafer to remove the protection layer, the metal layer and the insulating layer above the barrier layer protruding points; removing the residual barrier layer protruding point materials in the TSV region on the surface of the wafer to expose the wafer material; performing a dry etching process on the surface of the wafer to form a blind hole in the TSV region where the wafer material is exposed; and thinning the back surface of the wafer to enable the bottom of the blind hole to be opened so as to form the TSV through hole.
Description
Technical field
The present invention relates to technical field of semiconductors, especially a kind of process for making of TSV through hole.
Background technology
Along with the development of semiconductor technology, the characteristic size of integrated circuit constantly reduces, and device interconnection density improves constantly.Traditional two dimension encapsulation can not meet the demand of industry, and the keyset packaged type therefore based on TSV perpendicular interconnection interconnects with its short distance, and the key technology advantage of High Density Integration and low cost, has led the trend that encapsulation technology develops gradually.
TSV keyset technology main technique opens TSV in the front of keyset, then connect up and plant ball.Some technology then directly utilize TSV to do passage, can as the mass transfer passage of MEMS or micro-fluidic device.And at optical communication field, the TSV passage of this macropore then can realize inserting optical fiber from wafer rear, thus light signal is incorporated into the function of wafer frontside.The diameter of keyset through hole is very large, and hole sidewall is almost vertical, and follow-up photoetching gluing sidewall photoresist can occur and comes off, and hole depth can not be in order to be effective to exposure imaging bottom hole etc., and hole depth is also comparatively unfavorable to the last techniques such as cleaning of removing photoresist.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of process for making of TSV through hole is provided, and a kind of relevant blind hole of multiple hole depth or the process for making of TSV through hole, first at wafer silicon face deposited barrier layer, the method of lead to the hole site step is first reserved with barrier layer, preferentially produce RDL wire casing and weld pad groove, then by CMP, crystal column surface is ground, expose step, and metal RDL and metal pad surface matcoveredn cover, follow-uply directly remove step material by etching technics, expose wafer material, blind hole or TSV through hole is made by dry etch process, when making blind hole and TSV through hole without gluing and photoetching process, ensure that the stability of technique.The technical solution used in the present invention is:
A process for making for TSV through hole, comprises the steps:
Step S1, provides a wafer, at crystal column surface deposited barrier layer;
Step S2, carries out photoetching and etching technics at crystal column surface, removes the region that part is not TSV, make TSV region place formation barrier layer salient point to barrier layer;
Step S3, by photoetching and etching technics, makes crystal column surface be formed with the pattern of RDL wire casing;
Step S4, then at crystal column surface depositing insulating layer;
Step S5, crystal column surface insulating barrier makes metal level, forms metal RDL in RDL wire casing;
Step S6, at crystal column surface metal layer Deposition of protective layer;
Step S7, carries out CMP grinding to crystal column surface, removes protective layer, metal level and insulating barrier above the salient point of barrier layer;
Step S8, removes remaining barrier layer, crystal column surface TSV region convex point material, exposes wafer material;
Step S9, carries out dry etch process to crystal column surface, and the TSV region of exposing wafer material is etched formation blind hole;
Step S10, carries out reduction process to wafer rear, and blind via bottom is opened, and forms TSV through hole.
Further, the material of barrier layer salient point is silica, silicon nitride, photoresistance, macromolecule membrane, or metal material.
Further, in step S3, also form weld pad groove at crystal column surface simultaneously.
Further, in step S4, insulating layer material is silica, silicon nitride, photoresistance, or macromolecule membrane.
Further, in step S6, protective layer material is silica, silicon nitride, photoresistance, or macromolecule membrane.
Further, in step S8, by dry etching or wet-etching technology, the barrier layer convex point material in crystal column surface TSV region after previous step CMP grinding is removed.
The present invention also proposes the blind hole of one kind of multiple hole depths or the process for making of TSV through hole, comprises the steps:
Step S1 ', provides a wafer, at crystal column surface deposited barrier layer;
Step S2 ', carries out photoetching and etching technics at crystal column surface, removes the region that part is not TSV, make TSV region place form the different barrier layer salient point of multiple height to barrier layer;
Step S3 ', by photoetching and etching technics, makes crystal column surface be formed with the pattern of RDL wire casing;
Step S4 ', then at crystal column surface depositing insulating layer;
Step S5 ', crystal column surface insulating barrier makes metal level, forms metal RDL in RDL wire casing;
Step S6 ', at crystal column surface metal layer Deposition of protective layer;
Step S7 ', first carries out CMP grinding to the highest barrier layer salient point, removes the layer protective layer at its top, and the metal level above the barrier layer salient point then using the removal of the method for dry method or wet etching the highest and insulating barrier, expose the highest barrier layer salient point;
Step S8 ', by dry etching or wet-etching technology, removes the highest barrier layer convex point material exposed, exposes wafer material;
Step S9 ', carries out dry etch process to crystal column surface, and the TSV region of exposing wafer material is etched formation blind hole; After previous blind hole is formed, with insulating layer material, this blind hole is protected, then carry out the process of next barrier layer salient point by CMP;
Then according to the identical method of above-mentioned steps S7 ' ~ step S9 ', highly to process one by one to minimum barrier layer salient point secondary, then by repeatedly dry etching, the blind hole of the multiple degree of depth is formed to the TSV region of successively exposing wafer material;
Step S901 ', carries out CMP to crystal column surface and is ground to smooth, removes protective layer and metal level, retains insulating barrier;
Step S10 ', carries out reduction process to wafer rear.
Further, in step S10 ', thinning back side of silicon wafer makes a darkest blind hole open becomes TSV through hole, and the blind hole of all the other hole depths continues to keep blind hole shape.
Or:
In step S10 ', thinning back side of silicon wafer, makes all blind holes all continue to keep blind hole shape.
The invention has the advantages that:
1) first etch RDL wire casing, then carry out the etching of blind hole, avoid and first etch blind hole when being RDL again, the problem that blind via bottom photoresist exposure difficulty and photoresist are lost control of one's feelings at hole sidewall.
2) CMP before open-blind hole being all, avoids the residue problem to resist material inside bottom hole and the pollution problem of sidewall and hole of the material such as photoresist in photoetching process.
Accompanying drawing explanation
Fig. 1 is wafer schematic diagram in technique of the present invention.
Fig. 2 is deposited barrier layer schematic diagram in technique of the present invention.
Fig. 3 makes barrier layer salient point schematic diagram in technique of the present invention.
Fig. 4 makes RDL wire casing and weld pad groove and depositing insulating layer schematic diagram in technique of the present invention.
Fig. 5, in technique of the present invention, insulating barrier makes metal level schematic diagram.
Fig. 6 is Deposition of protective layer schematic diagram in technique of the present invention.
Fig. 7 is that in technique of the present invention, crystal column surface CMP grinds schematic diagram.
Fig. 8 removes barrier layer salient point surplus material schematic diagram in technique of the present invention.
Fig. 9 etches blind hole schematic diagram in technique of the present invention.
Figure 10 is that in technique of the present invention, thinning back side of silicon wafer forms TSV through hole schematic diagram.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
The process for making of the TSV through hole that the present invention proposes, comprises the steps:
Step S1, provides a wafer 1, as shown in Figure 1, on wafer 1 surface deposition barrier layer 2, as shown in Figure 2;
Barrier layer 2 can be the inorganic material such as silica, silicon nitride, also can be the organic materials such as photoresistance, macromolecule membrane, also can be the metal materials such as copper tin titanium, or first cvd silicon oxide does the resilient coating metal material such as deposited copper tin titanium again; This barrier layer 2 can be one deck, also can be multilayer; The deposition materials of this barrier layer 2 multilayer can be different types of;
Step S2, carries out photoetching and etching technics on wafer 1 surface, removes the region that part is not TSV, make TSV region place formation barrier layer salient point 201 to barrier layer 2; As shown in Figure 3; TSV region on the corresponding wafer 1 of barrier layer salient point 201;
In this step, first photoetching process is carried out to wafer 1 surface, make the region will being TSV have photoresist to protect, then by dry method or wet etching crystal column surface, not protected region, surface, barrier layer 2 entirety is removed; Remove photoresist, then TSV region only remaining barrier layer salient point 201; Barrier layer salient point 201 height is at 100nm ~ 100um herein;
If made blind hole has the demand of multiple hole depth, then in this step, form the barrier layer salient point 201 that multiple height is different;
Step S3, by photoetching and etching technics, makes wafer 1 surface be formed with the pattern of RDL wire casing 3 and weld pad groove 4; As shown in Figure 4;
Weld pad groove 4 be in this step alternatively, weld pad groove 4 can various shape above, and can be connected with RDL wire casing 3, also can separate, the degree of depth of weld pad groove 4 is at 100nm ~ 300um;
Step S4, then at wafer 1 surface deposition insulating barrier 5; As shown in Figure 4; This insulating barrier 5 material can be the inorganic material such as silica, silicon nitride, also can be the organic materials such as photoresistance, macromolecule membrane;
Step S5, wafer 1 surface insulation layer 5 makes metal level 6, forms metal RDL in RDL wire casing 3, and plates metal in optional weld pad groove 4; As shown in Figure 5;
This step is plated metal Seed Layer, then plated metal on wafer insulating barrier 5 first, and insulating barrier 5 is formed metal level 6, is coated with metal RDL simultaneously, also plates metal in optional weld pad groove 4 in RDL wire casing 3; RDL is the meaning of layer of rerouting;
Step S6, Deposition of protective layer 7 on wafer 1 surface metal-layer 6; As shown in Figure 6;
Protective layer 7 is used for protecting metal, and this protective layer can be the inorganic material such as silica, silicon nitride, also can be the organic materials such as photoresistance, macromolecule membrane;
Step S7, carries out CMP grinding to wafer 1 surface, removes protective layer 7, metal level 6 and insulating barrier 5 above barrier layer salient point 201; Retain the insulating barrier 5 of part beyond the surperficial TSV region of wafer 1;
In this step, can as shown in Figure 7, when carrying out CMP grinding on wafer 1 surface, polished by barrier layer salient point 201, after whole wafer 1 surface is polished, the protective layer 7 above barrier layer salient point 201, metal level 6 and insulating barrier 5 are naturally worn; And the insulating barrier 5 of part needs to retain beyond the surperficial TSV region of wafer 1, can not grind;
If made blind hole has the demand of multiple hole depth, so, need first to carry out CMP grinding to the highest barrier layer salient point, remove the layer protective layer 7 at its top, the metal level 6 above the barrier layer salient point then using the removal of the method for dry method or wet etching the highest and insulating barrier 5; Now, the crystal column surface beyond the TSV region that the highest barrier layer salient point is corresponding, also maintains insulating barrier 5, metal level 6 and protective layer 7;
Step S8, removes remaining barrier layer, wafer 1 surperficial TSV region salient point 201 material, exposes wafer material;
This step as described in Figure 8, by dry etching or wet-etching technology, removes barrier layer salient point 201 material in crystal column surface TSV region after previous step CMP grinding, exposes wafer material;
Step S9, carries out dry etch process to wafer 1 surface, the TSV region of exposing wafer material is etched and forms blind hole 101; As shown in Figure 9;
Step S10, carries out reduction process to wafer 1 back side, makes to open bottom blind hole 101, forms TSV through hole 102;
Wafer is follow-up can be proceeded to plant the technique such as ball or welding and complete requirement of engineering.
Below to have the blind hole of multiple hole depth demand or or TSV through hole manufacture craft be described further.
Step S1 ', provides a wafer 1, on wafer 1 surface deposition barrier layer 2;
Step S2 ', carries out photoetching and etching technics on wafer 1 surface, removes the region that part is not TSV, make TSV region place form the different barrier layer salient point 201 of multiple height to barrier layer 2;
Step S3 ', by photoetching and etching technics, makes wafer 1 surface be formed with the pattern of RDL wire casing 3;
Step S4 ', then at wafer 1 surface deposition insulating barrier 5;
Step S5 ', wafer 1 surface insulation layer 5 makes metal level 6, forms metal RDL in RDL wire casing 3;
Step S6 ', Deposition of protective layer 7 on wafer 1 surface metal-layer 6;
Step S7 ', first carries out CMP grinding to the highest barrier layer salient point, removes the layer protective layer 7 at its top, and the metal level 6 above the barrier layer salient point then using the removal of the method for dry method or wet etching the highest and insulating barrier 5, expose the highest barrier layer salient point;
Now, the crystal column surface beyond the TSV region that the highest barrier layer salient point is corresponding, also maintains insulating barrier 5, metal level 6 and protective layer 7;
Step S8 ', by dry etching or wet-etching technology, removes the highest barrier layer convex point material exposed, exposes wafer material;
Step S9 ', carries out dry etch process to wafer 1 surface, the TSV region of exposing wafer material is etched and forms blind hole 101; After previous blind hole is formed, with insulating layer material, this blind hole is protected, then carry out the process of next barrier layer salient point by CMP;
Then according to the identical method of above-mentioned steps S7 ' ~ step S9 ', highly to process one by one to minimum barrier layer salient point secondary, then by repeatedly dry etching, the blind hole of the multiple degree of depth is formed to the TSV region of successively exposing wafer material;
Step S901 ', carries out CMP to wafer 1 surface and is ground to smooth, removes protective layer 7 and metal level 6, retains insulating barrier 5;
Step S10 ', carries out reduction process to wafer 1 back side.Reduction process can make a darkest blind hole open becomes TSV through hole, and the blind hole of all the other hole depths continues to keep blind hole shape; Also can be that all blind holes all continue to keep blind hole shape.
Claims (9)
1. a process for making for TSV through hole, is characterized in that, comprises the steps:
Step S1, provides a wafer (1), on wafer (1) surface deposition barrier layer (2);
Step S2, carries out photoetching and etching technics on wafer (1) surface, removes the region that part is not TSV, make formation barrier layer salient point, TSV region place (201) to barrier layer (2);
Step S3, by photoetching and etching technics, makes wafer (1) surface be formed with the pattern of RDL wire casing (3);
Step S4, then at wafer (1) surface deposition insulating barrier (5);
Step S5, wafer (1) surface insulation layer (5) makes metal level (6), in RDL wire casing (3), form metal RDL;
Step S6, Deposition of protective layer (7) on wafer (1) surface metal-layer (6);
Step S7, carries out CMP grinding to wafer (1) surface, removes the protective layer (7) of top, barrier layer salient point (201), metal level (6) and insulating barrier (5); Retain the insulating barrier (5) of part beyond wafer (1) surperficial TSV region;
Step S8, removes remaining barrier layer, wafer (1) surperficial TSV region salient point (201) material, exposes wafer material;
Step S9, carries out dry etch process to wafer (1) surface, the TSV region of exposing wafer material is etched and forms blind hole (101);
Step S10, carries out reduction process to wafer (1) back side, blind hole (101) bottom is opened, forms TSV through hole (102).
2. the process for making of TSV through hole as claimed in claim 1, is characterized in that:
The material of barrier layer salient point (201) is silica, silicon nitride, photoresistance, macromolecule membrane, or metal material.
3. the process for making of TSV through hole as claimed in claim 1, is characterized in that:
In step S3, also form weld pad groove (4) on wafer (1) surface simultaneously.
4. the process for making of TSV through hole as claimed in claim 1, is characterized in that:
In step S4, insulating barrier (5) material is silica, silicon nitride, photoresistance, or macromolecule membrane.
5. the process for making of TSV through hole as claimed in claim 1, is characterized in that:
In step S6, protective layer (7) material is silica, silicon nitride, photoresistance, or macromolecule membrane.
6. the process for making of TSV through hole as claimed in claim 1, is characterized in that:
In step S8, by dry etching or wet-etching technology, barrier layer salient point (201) material in crystal column surface TSV region after previous step CMP grinding is removed.
7. the blind hole of one kind of multiple hole depths or the process for making of TSV through hole, is characterized in that, comprise the steps:
Step S1 ', provides a wafer (1), on wafer (1) surface deposition barrier layer (2);
Step S2 ', carries out photoetching and etching technics on wafer (1) surface, removes the region that part is not TSV, make TSV region place form the different barrier layer salient point (201) of multiple height to barrier layer (2);
Step S3 ', by photoetching and etching technics, makes wafer (1) surface be formed with the pattern of RDL wire casing (3);
Step S4 ', then at wafer (1) surface deposition insulating barrier (5);
Step S5 ', wafer (1) surface insulation layer (5) makes metal level (6), in RDL wire casing (3), form metal RDL;
Step S6 ', Deposition of protective layer (7) on wafer (1) surface metal-layer (6);
Step S7 ', first CMP grinding is carried out to the highest barrier layer salient point, remove the layer protective layer (7) at its top, then the metal level (6) above the barrier layer salient point using the removal of the method for dry method or wet etching the highest and insulating barrier (5), expose the highest barrier layer salient point;
Step S8 ', by dry etching or wet-etching technology, removes the highest barrier layer convex point material exposed, exposes wafer material;
Step S9 ', carries out dry etch process to wafer (1) surface, the TSV region of exposing wafer material is etched and forms blind hole (101); After previous blind hole is formed, with insulating layer material, this blind hole is protected, then carry out the process of next barrier layer salient point by CMP;
Then according to the identical method of above-mentioned steps S7 ' ~ step S9 ', highly to process one by one to minimum barrier layer salient point secondary, then by repeatedly dry etching, the blind hole of the multiple degree of depth is formed to the TSV region of successively exposing wafer material;
Step S901 ', carries out CMP to wafer (1) surface and is ground to smooth, removes protective layer (7) and metal level 6, retains insulating barrier (5);
Step S10 ', carries out reduction process to wafer (1) back side.
8. the blind hole of multiple hole depth as claimed in claim 7 or the process for making of TSV through hole, is characterized in that:
In step S10 ', thinning back side of silicon wafer makes a darkest blind hole open becomes TSV through hole, and the blind hole of all the other hole depths continues to keep blind hole shape.
9. the blind hole of multiple hole depth as claimed in claim 7 or the process for making of TSV through hole, is characterized in that:
In step S10 ', thinning back side of silicon wafer, makes all blind holes all continue to keep blind hole shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510940285.1A CN105428309B (en) | 2015-12-16 | 2015-12-16 | The process for making of the blind hole or TSV through hole of the process for making of TSV through hole and a variety of hole depths |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510940285.1A CN105428309B (en) | 2015-12-16 | 2015-12-16 | The process for making of the blind hole or TSV through hole of the process for making of TSV through hole and a variety of hole depths |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105428309A true CN105428309A (en) | 2016-03-23 |
| CN105428309B CN105428309B (en) | 2018-07-06 |
Family
ID=55506411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510940285.1A Active CN105428309B (en) | 2015-12-16 | 2015-12-16 | The process for making of the blind hole or TSV through hole of the process for making of TSV through hole and a variety of hole depths |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105428309B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109314061A (en) * | 2018-09-11 | 2019-02-05 | 深圳市汇顶科技股份有限公司 | Production method, living things feature recognition mould group and the terminal device of via devices |
| CN111180388A (en) * | 2020-03-16 | 2020-05-19 | 西安微电子技术研究所 | Manufacturing method of silicon through hole on wafer without blank area |
| WO2020140231A1 (en) * | 2019-01-03 | 2020-07-09 | 京东方科技集团股份有限公司 | Patterning method for film layer, and microfluidic device and manufacturing method therefor |
| GB2587374A (en) * | 2019-09-25 | 2021-03-31 | X Fab Semiconductor Foundries | Through silicon via and redistribution layer |
| CN113410175A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Preparation method of TSV (through silicon Via) conductive through hole structure |
| CN113580557A (en) * | 2021-07-28 | 2021-11-02 | 沛顿科技（深圳）有限公司 | 3D printing method for replacing NCF in TSV process |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377984A (en) * | 2012-04-16 | 2013-10-30 | 上海华虹Nec电子有限公司 | Manufacturing process method for TSV backside conduction |
| CN103426864A (en) * | 2013-08-26 | 2013-12-04 | 华进半导体封装先导技术研发中心有限公司 | TSV structure applicable to adapter board and preparation method of TSV structure |
| CN103560108A (en) * | 2013-10-08 | 2014-02-05 | 华进半导体封装先导技术研发中心有限公司 | Method for filling deep holes with photoresist |
| US20150076694A1 (en) * | 2013-09-13 | 2015-03-19 | United Microelectronics Corporation | Interposer structure and manufacturing method thereof |
| US20150179516A1 (en) * | 2013-12-25 | 2015-06-25 | United Microelectronics Corp. | Integrated structure and method for fabricating the same |
-
2015
- 2015-12-16 CN CN201510940285.1A patent/CN105428309B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377984A (en) * | 2012-04-16 | 2013-10-30 | 上海华虹Nec电子有限公司 | Manufacturing process method for TSV backside conduction |
| CN103426864A (en) * | 2013-08-26 | 2013-12-04 | 华进半导体封装先导技术研发中心有限公司 | TSV structure applicable to adapter board and preparation method of TSV structure |
| US20150076694A1 (en) * | 2013-09-13 | 2015-03-19 | United Microelectronics Corporation | Interposer structure and manufacturing method thereof |
| CN103560108A (en) * | 2013-10-08 | 2014-02-05 | 华进半导体封装先导技术研发中心有限公司 | Method for filling deep holes with photoresist |
| US20150179516A1 (en) * | 2013-12-25 | 2015-06-25 | United Microelectronics Corp. | Integrated structure and method for fabricating the same |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109314061A (en) * | 2018-09-11 | 2019-02-05 | 深圳市汇顶科技股份有限公司 | Production method, living things feature recognition mould group and the terminal device of via devices |
| WO2020051765A1 (en) * | 2018-09-11 | 2020-03-19 | 深圳市汇顶科技股份有限公司 | Method for manufacturing via component, biological feature recognition module, and terminal device |
| US11731125B2 (en) | 2019-01-03 | 2023-08-22 | Beijing Boe Sensor Technology Co., Ltd. | Patterning method of film, microfluidic device and manufacturing method thereof |
| WO2020140231A1 (en) * | 2019-01-03 | 2020-07-09 | 京东方科技集团股份有限公司 | Patterning method for film layer, and microfluidic device and manufacturing method therefor |
| CN111886197A (en) * | 2019-01-03 | 2020-11-03 | 京东方科技集团股份有限公司 | Film composition method, microfluidic device and manufacturing method thereof |
| CN111886197B (en) * | 2019-01-03 | 2023-04-04 | 京东方科技集团股份有限公司 | Film composition method, microfluidic device and manufacturing method thereof |
| GB2587374B (en) * | 2019-09-25 | 2022-08-17 | X Fab Semiconductor Foundries Gmbh | Through silicon via and redistribution layer |
| GB2587374A (en) * | 2019-09-25 | 2021-03-31 | X Fab Semiconductor Foundries | Through silicon via and redistribution layer |
| US11795051B2 (en) | 2019-09-25 | 2023-10-24 | X-Fab Semiconductor Foundries Gmbh | Through silicon via and redistribution layer |
| CN111180388B (en) * | 2020-03-16 | 2021-11-30 | 西安微电子技术研究所 | Manufacturing method of silicon through hole on wafer without blank area |
| CN111180388A (en) * | 2020-03-16 | 2020-05-19 | 西安微电子技术研究所 | Manufacturing method of silicon through hole on wafer without blank area |
| CN113410175A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Preparation method of TSV (through silicon Via) conductive through hole structure |
| CN113410175B (en) * | 2021-06-15 | 2023-06-02 | 西安微电子技术研究所 | TSV conductive through hole structure preparation method |
| CN113580557A (en) * | 2021-07-28 | 2021-11-02 | 沛顿科技（深圳）有限公司 | 3D printing method for replacing NCF in TSV process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105428309B (en) | 2018-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105428309A (en) | Manufacturing technological method for TSV through hole, and manufacturing technological method for blind hole or TSV through hole of multiple hole depths | |
| US10840287B2 (en) | 3DIC interconnect apparatus and method | |
| US11678133B2 (en) | Structure for integrated microphone | |
| CN105321874B (en) | The method for forming semiconductor devices | |
| CN101842886B (en) | Methods for fabricating sub-resolution alignment marks on semiconductor structures and semiconductor structures including same | |
| TWI466258B (en) | Conductive through connection and forming method thereof | |
| CN102280391B (en) | Wafer level package structure and formation method thereof | |
| EP3799112B1 (en) | Method for dicing a semiconductor substrate into a plurality of dies | |
| CN103377984A (en) | Manufacturing process method for TSV backside conduction | |
| CN103219281A (en) | Through silicon via (TSV) back surface exposure process | |
| CN105023909A (en) | Structure and method of providing a re-distribution layer (RDL) and a through-silicon via (TSV) | |
| CN105405781A (en) | Method for manufacturing wafer level encapsulation back lead using CMP process | |
| CN104167353A (en) | Method for processing surface of bonding substrate | |
| CN105374747B (en) | The process in different depth TSV holes is etched on wafer | |
| CN105470146B (en) | The method that large through-hole wafer pinboard is made using CMP process | |
| CN104143526A (en) | Method for manufacturing through-silicon-via structure | |
| US8822141B1 (en) | Front side wafer ID processing | |
| CN110444469B (en) | Method for relieving damage to lower layer part caused by etching of top layer of chip | |
| CN102130036B (en) | Method for producing shallow trench isolating structure | |
| CN104952720A (en) | Method for forming height-controllable exposure of electric-conducting poles from back | |
| US11315904B2 (en) | Semiconductor assembly and method of manufacturing the same | |
| CN105900247A (en) | Semiconductor device for optical applications and method of producing such a semiconductor device | |
| CN105810637B (en) | A kind of integrated approach of 3D NAND peripheral components | |
| CN105470147A (en) | Method for making adapter plate with CMP process | |
| EP3358612A1 (en) | Method for selective etching using dry film photoresist |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |