CN105470147A - Method for making adapter plate with CMP process - Google Patents
Method for making adapter plate with CMP process Download PDFInfo
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- CN105470147A CN105470147A CN201510942997.7A CN201510942997A CN105470147A CN 105470147 A CN105470147 A CN 105470147A CN 201510942997 A CN201510942997 A CN 201510942997A CN 105470147 A CN105470147 A CN 105470147A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
Abstract
The invention relates to a method for making an adapter plate with a CMP process. The method comprises the following steps of: (1) depositing an insulation layer on the back surface of a wafer, and making an RDL region on the first insulation layer with a photolithographic process; then making a TSV opening graph with the photolithographic process, and etching a TSV in the TSV opening graph; (2) depositing a second insulation layer on the surface of the first insulation layer on the back surface of the wafer, wherein the second insulation layer covers the surface of the first insulation layer, the side wall and bottom of the RDL region and the side wall and the bottom of the TSV; then making a metal film on the second insulation layer on the back surface of the wafer; (3) grinding the back surface of the wafer with the CMP process until the second insulation layer is exposed, and enabling the metal film in the RDL region to be flush with the second insulation layer on the back surface of the wafer so as to form an RDL route in the RDL region; and finally enabling a bottom opening of the TSV to be exposed with a TSV back exposure process. According to the method, firstly the insulation layer is deposited, secondly wire arrangement is performed on the surface of the insulation layer, and finally a TSV groove is formed, so that a TSV adapter plate process is more reliable and the cost is reduced.
Description
Technical field
The present invention relates to a kind of method adopting CMP to make keyset, belong to technical field of semiconductors.
Background technology
Along with the development of semiconductor technology, the characteristic size of integrated circuit constantly reduces, and device interconnection density improves constantly.Traditional two dimension encapsulation can not meet the demand of industry, and the keyset packaged type therefore based on TSV perpendicular interconnection interconnects with its short distance, and the key technology advantage of High Density Integration and low cost, has led the trend that encapsulation technology develops gradually.
TSV keyset technology main technique opens TSV hole in the front of keyset, then connect up and plant ball.Some technology then directly utilize TSV to do passage, can as the mass transfer passage of MEMS or micro-fluidic device.And at optical communication field, the TSV passage of this macropore then can realize inserting optical fiber from wafer rear, thus light signal is incorporated into the function of wafer frontside.The diameter of keyset through hole is very large, and hole sidewall is almost vertical, and follow-up photoetching gluing sidewall photoresist can occur and comes off, and bottom hole, exposure imaging etc. can not be in order to be effective, also comparatively unfavorable to the last techniques such as cleaning of removing photoresist.
Summary of the invention
The object of this part is some aspects of general introduction embodiments of the invention and briefly introduces some preferred embodiments.May do in the specification digest and denomination of invention of this part and the application a little simplify or omit with avoid making this part, specification digest and denomination of invention object fuzzy, and this simplification or omit and can not be used for limiting the scope of the invention.
In view of the TSV passage TSV keyset existed in above-mentioned and/or existing semiconductor packages being opened large through-hole, the problem that follow-up photoetching gluing generation sidewall photoresist comes off, exposure imaging can not be in order to be effective bottom hole, proposes the present invention.
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of method adopting CMP to make keyset, first depositing insulating layer, in surface of insulating layer wiring, finally open TSV groove, make TSV keyset technique more reliable, reduce costs.
According to technical scheme provided by the invention, described employing CMP makes the method for keyset, comprises the following steps:
(1) at wafer rear depositing first insulator layer, the first insulating barrier produces RDL region by photoetching process; Produce TSV hole opening figure through photoetching process again, in TSV hole, opening figure etches TSV hole;
(2) the first surface of insulating layer of wafer rear deposits the second insulating barrier, and the second insulating barrier covers the surface of the first insulating barrier, the sidewall in the sidewall in RDL region and bottom and TSV hole and bottom; Then on the second insulating barrier of wafer rear, metallic film is made;
(3) adopt the CMP grinding crystal wafer back side until expose the second insulating barrier, make the metallic film in RDL region concordant with the second insulating barrier of wafer rear, thus form RDL circuit in RDL region; Finally adopt TSV back technique of appearing that the bottom opening in TSV hole is exposed.
Further, described step (1) specifically adopts following technique:
Step 1-1, at wafer rear depositing first insulator layer;
Step 1-2, surperficial resist coating at the first insulating barrier, the opening figure in RDL region is exposed through exposure imaging, at the opening figure place in RDL region, etching is carried out to the first insulating barrier by dry etching or wet corrosion technique and form RDL region, etching depth is less than the thickness of the first insulating barrier, retains certain thickness first insulating barrier after etching in the bottom in RDL region;
Step 1-3, making the first surface of insulating layer resist coating in RDL region, expose TSV hole opening figure through exposure imaging;
Step 1-4, at TSV opening figure place, dry etching is carried out to the first insulating barrier, form TSV hole;
Step 1-5, remove the photoresist of the first surface of insulating layer.
Further, described step (2) specifically adopts following technique:
Step 2-1, on the first insulating barrier of wafer rear, deposit the second insulating barrier, the second insulating barrier covers the surface of the first insulating barrier, the sidewall in the sidewall in RDL region and bottom and TSV hole and bottom; Second thickness of insulating layer of wafer rear is 50nm ~ 5 μm, and bottom TSV hole, the second thickness of insulating layer is 100nm ~ 2 μm;
Step 2-2, at wafer rear depositing metal films, metallic film covers the second insulating barrier of wafer rear.
Further, described step (3) specifically adopts following technique:
Step 3-1, CMP is carried out to wafer rear, grind off the metallic film of protrusion, expose the second insulating barrier;
Step 3-2, finish wafer back process after, carry out thinning to the front of wafer, by etching technics, the bottom in TSV hole is exposed, thinning rear wafer thickness is 100nm ~ 500 μm; Then etch bottom the TSV hole of exposing or directly grind, or grind again after covering insulating barrier, finally open the bottom in TSV hole, make bottom TSV hole unimpeded, form bottom opening.
Further, the thickness of described first insulating barrier is 10nm ~ 50 μm.
Further, the etching depth in described RDL region is 10nm ~ 50 μm.
Further, the A/F in described TSV hole is 10nm ~ 5mm, and the degree of depth is 100nm ~ 500 μm; The sidewall in described TSV hole is vertical or domatic.
Further, also comprise and make multilayer RDL circuit: the wafer rear depositing insulating layer obtained in step (3), make the etching of carrying out TSV hole behind RDL region again through photoetching process; Then adopt CMP to grind after making metallic film and expose insulating barrier.
Described employing CMP makes the method for keyset, comprises the following steps:
(1) at wafer rear depositing first insulator layer, the first insulating barrier produces RDL region by photoetching process; Produce TSV hole opening figure through photoetching process again, in TSV hole, opening figure etches TSV hole;
(2) described wafer adopts High Resistivity Si, and the first insulating barrier of wafer rear makes metallic film;
(3) adopt the CMP grinding crystal wafer back side until expose the first insulating barrier, make the metallic film in RDL region concordant with the first insulating barrier of wafer rear, thus form RDL circuit in RDL region; Finally adopt TSV back technique of appearing that the bottom opening in TSV hole is exposed.
Employing CMP of the present invention makes the method for keyset, utilizes CMP(cmp) technology, first depositing insulating layer, in surface of insulating layer wiring, finally opens TSV groove, and make TSV keyset technique become reliable, cost reduces.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein: Fig. 1 ~ Figure 12 is the schematic diagram of manufacturing process of the present invention, wherein:
Fig. 1 is the schematic diagram at wafer rear depositing first insulator layer.
Fig. 2-1 is the schematic diagram making RDL region at the first surface of insulating layer.
Fig. 2-2 is the vertical view of Fig. 2-1.
Fig. 3-1 is the schematic diagram making TSV opening figure.
Fig. 3-2 is the vertical view of Fig. 3-1 after removal photoresist.
Fig. 4 is the schematic diagram making TSV hole.
Fig. 5 is the schematic diagram of removal first surface of insulating layer photoresist.
Fig. 6 is the schematic diagram that wafer rear deposits the second insulating barrier.
Fig. 7 is the schematic diagram making metallic film at wafer rear.
Fig. 8 is schematic diagram wafer rear being carried out to CMP.
Fig. 9 carries out the thinning schematic diagram opening TSV hole bottom opening to the front of wafer.
Figure 10 is the schematic diagram of two-layer RDL circuit.
Figure 11 is TSV hole and the disjunct structural representation of RDL circuit.
Figure 12 is the schematic diagram of the disjunct two-layer RDL line construction of TSV hole and RDL circuit.
Sequence number in figure: wafer 1, RDL region 2, TSV hole opening figure 3, TSV hole 4, first insulating barrier 5-1, the second insulating barrier 5-2, metal level 6.
Embodiment
In order to enable above-mentioned purpose of the present invention, feature and advantage become apparent more, are further described the specific embodiment of the present invention below in conjunction with concrete accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here carrys out embodiment, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space that should comprise length, width and the degree of depth in making is being implemented.
Separately, the term " back side " proposed in the present invention, " front ", " sidewall " or the indicating position such as " " and " surface " or position relationship are based on orientation shown in the drawings or position relationship at the end, understand based on this kind, if for the thinning of particular elements or assembly " face " or " side " or thicken, the extension based on this particular elements or assembly " face " or " side " can also be referred to, instead of require that the present invention with specific azimuth configuration and operation, therefore must be not understood to limitation of the present invention.
Embodiment one: a kind of method adopting CMP to make keyset, comprises the following steps:
(1) the first depositing first insulator layer 5-1 at wafer 1 back side, the first insulating barrier 5-1 produces RDL region 2 by photoetching process, i.e. RDL cabling figure; Produce TSV hole opening figure 3 through photoetching process again, etch TSV hole 4 in TSV hole opening figure 3; Concrete employing following steps:
Step 1-1, as shown in Figure 1, at wafer 1 backside deposition first insulating barrier 5-1, the material of the first insulating barrier 5-1 can be the inorganic matter such as silicon dioxide, silicon nitride, also can be the organic substance such as photoresistance, resin, insulating material is done in the effect of the first insulating barrier 5-1, avoids follow-up metal material and wafer conducting; The thickness of described first insulating barrier 5-1 is 10nm ~ 50 μm;
Step 1-2, making RDL region 2: as shown in Fig. 2-1, Fig. 2-2, at the surperficial resist coating of the first insulating barrier 5-1, expose the opening figure in RDL region 2 through exposure imaging, RDL region 2 comprises pad, cabling and connects the region in TSV hole; At the opening figure place in RDL region 2, etching is carried out to the first insulating barrier 5-1 by the technique such as dry etching or wet etching again and form RDL region 2, etching depth is 10nm ~ 50 μm, and etching depth is less than the thickness of the first insulating barrier 5-1, after making etching form RDL region 2, retain certain thickness first insulating barrier 5-1 in the bottom in RDL region; Described RDL region 2 can comprise TSV bore region, also can only include the routing region that RDL lead areas is connected with follow-up TSV bore region, or not be connected with TSV bore region;
Step 1-3, making TSV hole opening figure: as shown in figure 3-1, making the first insulating barrier 5-1 surface resist coating in RDL region 2, TSV hole opening figure 3 is exposed through exposure imaging, the position of TSV hole opening figure 3 can not be connected with RDL region 2 as shown in figure 3-2, or be positioned at edge, RDL region 2, connect TSV hole by cabling, or TSV bore region is directly in the inside in RDL region 2;
Step 1-4, as shown in Figure 4, carry out dry etching at TSV opening figure 3 place to the first insulating barrier 5-1, the A/F forming hole, TSV hole 4, TSV 4 is 10nm ~ 5mm, and the degree of depth is 100nm ~ 500 μm; Described TSV hole 4 cross section can be square, trapezoidal, triangle or other polygon, and the sidewall in TSV hole 4 can be vertical, also can be domatic;
Step 1-5, as shown in Figure 5, remove the photoresist on the first insulating barrier 5-1 surface, and the back side of the first insulating barrier 5-1 and TSV hole 4 are cleaned, make these regions there is no organic substance residues.
(2) the first insulating barrier 5-1 surface deposition second insulating barrier 5-2 at wafer 1 back side, the second insulating barrier 5-2 cover the surface of the first insulating barrier 5-1, the sidewall in the sidewall in RDL region 2 and bottom and TSV hole 4 and bottom; Then on the second insulating barrier 5-2 at wafer 1 back side, metallic film 6 is made; Concrete employing following steps:
Step 2-1, as shown in Figure 6, the first insulating barrier 5-1 at wafer 1 back side deposits the second insulating barrier 5-2, make the second insulating barrier 5-2 cover the surface of the first insulating barrier 5-1, the sidewall in the sidewall in RDL region 2 and bottom and TSV hole 4 and bottom; The second described insulating barrier 5-2 can be the inorganic oxide such as silica, silicon nitride of vapor phase method deposition, and also can be organic substance such as plating photoresistance, spray-bonding craft photoresistance etc., their Main Function be isolation wafer back part, plays the effect of insulation; The second insulating barrier 5-2 herein, due to the more difficult deposition in bottom in TSV hole 4, therefore there will be thickness of insulating layer at the bottom of hole less, the trend that surface is larger; The second insulating barrier 5-2 thickness at final wafer 1 back side is 50nm ~ 5 μm, and bottom TSV hole 4, the second insulating barrier 5-2 thickness is 100nm ~ 2 μm; High Resistivity Si can without depositing insulating layer;
Step 2-2, as shown in Figure 7, at wafer 1 backside deposition metallic film 6, metallic film 6 covers the second insulating barrier 5-2 at wafer 1 back side; The technique of described depositing metal films 6 comprises PVD Seed Layer and follow-up plating or changes depositing process etc.; Seed Layer can be titanium copper metal, also can aluminium; Plating or change plating can be copper, also can be tin, nickel, palladium, gold etc.; If depositing metal films 6 step needs after finishing to protect metallic circuit, a layer insulating can also be deposited again, as silicon dioxide etc. in face on the line.
(3) adopt CMP grinding crystal wafer 1 back side until expose the second insulating barrier 5-2, make the metallic film 6 in RDL region 2 concordant with the second insulating barrier 5-2 at wafer 1 back side, thus form RDL circuit in RDL region 2, the cleaning wafer back side; Finally adopt TSV back technique of appearing that the bottom opening in TSV hole 4 is exposed; Concrete employing following steps:
Step 3-1, as shown in Figure 8, CMP is carried out to wafer 1 back side, grind off the second insulating barrier 5-2 and the metallic film 6 of all protrusions, expose the second insulating barrier 5-2; Now RDL region 2 and TSV hole 4 are because of the surface lower than wafer 1 back side, therefore can not be removed by CMP, define the RDL circuit of conducting; Cleaning wafer 1 back side, the pad that wafer 1 back side is exposed directly can do pad, does pad again after also can changing plating nickel gold; Also directly follow-up doing can plant ball technique, or first change plating nickel gold etc. and protect RDL circuit and pad, then carry out planting ball technique;
Step 3-2, as shown in Figure 9, after finishing the back process of wafer 1, carry out thinning to the front of wafer 1, by etching technics, the bottom in TSV hole 4 is exposed, thinning rear wafer 1 thickness is 100nm ~ 500 μm; Then etch bottom the TSV hole 4 of exposing or directly grind, or grind again after covering insulating barrier, finally open the bottom in TSV hole 4, make bottom TSV hole 4 unimpeded, form bottom opening.
RDL circuit of the present invention can be one deck, also can be multilayer, but is all the etching of carrying out TSV hole after first etching formation RDL region again; Be the schematic diagram of two-layer RDL circuit as shown in Figure 10.
As shown in figure 11, TSV hole 4 of the present invention can RDL cabling or pad not connect completely; As shown in Figure 9, be schematic diagram that TSV hole 4 is connected with RDL circuit.As the schematic diagram that Figure 12 is two-layer RDL circuit, in Figure 12, RDL circuit is not connected with TSV hole 4.As shown in Figure 10, be the schematic diagram of two-layer RDL circuit, in Figure 10, RDL circuit is connected with TSV hole 4.
The label had about step mentioned in the embodiments of the present invention, is only used to the convenience described, and does not have the contact of sequencing in fact.As long as can realize goal of the invention of the present invention, the different step in each embodiment, can carry out the combination of different sequencing.
It should be noted that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (9)
1. adopt CMP to make a method for keyset, it is characterized in that, comprise the following steps:
(1) at wafer (1) backside deposition first insulating barrier (5-1), the first insulating barrier (5-1) produces RDL region (2) by photoetching process; Produce TSV hole opening figure (3) through photoetching process again, etch TSV hole (4) in TSV hole opening figure (3);
(2) the first insulating barrier (5-1) surface deposition second insulating barrier (5-2) at wafer (1) back side, the second insulating barrier (5-2) covers the surface of the first insulating barrier (5-1), the sidewall of the sidewall of RDL region (2) and bottom and TSV hole (4) and bottom; Then on second insulating barrier (5-2) at wafer (1) back side, metallic film (6) is made;
(3) adopt CMP grinding crystal wafer (1) back side until expose the second insulating barrier (5-2), make the metallic film of RDL region (2) (6) concordant with second insulating barrier (5-2) at wafer (1) back side, thus form RDL circuit in RDL region (2); Finally adopt TSV back technique of appearing that the bottom opening in TSV hole (4) is exposed.
2. the method adopting CMP to make keyset as claimed in claim 1, is characterized in that: described step (1) specifically adopts following technique:
Step 1-1, at wafer (1) backside deposition first insulating barrier (5-1);
Step 1-2, surperficial resist coating at the first insulating barrier (5-1), the opening figure of RDL region (2) is exposed through exposure imaging, at the opening figure place of RDL region (2), etching is carried out to the first insulating barrier (5-1) by dry etching or wet corrosion technique and form RDL region (2), etching depth is less than the thickness of the first insulating barrier (5-1), retains certain thickness first insulating barrier (5-1) after etching in the bottom of RDL region (2);
Step 1-3, making the first insulating barrier (5-1) the surperficial resist coating in RDL region (2), expose TSV hole opening figure (3) through exposure imaging;
Step 1-4, at TSV opening figure (3) place, dry etching is carried out to the first insulating barrier (5-1), form TSV hole (4);
Step 1-5, remove the first insulating barrier (5-1) surface photoresist.
3. the method adopting CMP to make keyset as claimed in claim 1, is characterized in that: described step (2) specifically adopts following technique:
Upper deposition second insulating barrier (5-2) of step 2-1, the first insulating barrier (5-1) at wafer (1) back side, the second insulating barrier (5-2) covers the surface of the first insulating barrier (5-1), the sidewall of the sidewall of RDL region (2) and bottom and TSV hole (4) and bottom; Second insulating barrier (5-2) thickness at wafer (1) back side is 50nm ~ 5 μm, and TSV hole (4) bottom the second insulating barrier (5-2) thickness is 100nm ~ 2 μm;
Step 2-2, at wafer (1) backside deposition metallic film (6), metallic film (6) covers second insulating barrier (5-2) at wafer (1) back side.
4. the method adopting CMP to make keyset as claimed in claim 1, is characterized in that: described step (3) specifically adopts following technique:
Step 3-1, CMP is carried out to wafer (1) back side, grind off the metallic film (6) of protrusion, expose the second insulating barrier (5-2);
Step 3-2, finish wafer (1) back process after, carry out thinning to the front of wafer (1), by etching technics, the bottom in TSV hole (4) is exposed, thinning rear wafer (1) thickness is 100nm ~ 500 μm; Then the bottom, TSV hole (4) of exposing is etched or directly ground, or grind again after covering insulating barrier, finally open the bottom of TSV hole (4), make bottom, TSV hole (4) unimpeded, form bottom opening.
5. the method adopting CMP to make keyset as claimed in claim 1, is characterized in that: the thickness of described first insulating barrier (5-1) is 10nm ~ 50 μm.
6. the method adopting CMP to make keyset as claimed in claim 1, is characterized in that: the etching depth of described RDL region (2) is 10nm ~ 50 μm.
7. the method adopting CMP to make keyset as claimed in claim 1, is characterized in that: the A/F of described TSV hole (4) is 10nm ~ 5mm, and the degree of depth is 100nm ~ 500 μm; The sidewall of described TSV hole (4) is vertical or domatic.
8. the method adopting CMP to make keyset as claimed in claim 1, is characterized in that: also comprise and make multilayer RDL circuit: the wafer rear depositing insulating layer obtained in step (3), makes the etching of carrying out TSV hole behind RDL region again through photoetching process; Then adopt CMP to grind after making metallic film and expose insulating barrier.
9. adopt CMP to make a method for keyset, it is characterized in that, comprise the following steps:
(1) at wafer (1) backside deposition first insulating barrier (5-1), the first insulating barrier (5-1) produces RDL region (2) by photoetching process; Produce TSV hole opening figure (3) through photoetching process again, etch TSV hole (4) in TSV hole opening figure (3);
(2) described wafer (1) adopts High Resistivity Si, and first insulating barrier (5-1) at wafer (1) back side makes metallic film (6);
(3) adopt CMP grinding crystal wafer (1) back side until expose the first insulating barrier (5-1), make the metallic film of RDL region (2) (6) concordant with first insulating barrier (5-1) at wafer (1) back side, thus form RDL circuit in RDL region (2); Finally adopt TSV back technique of appearing that the bottom opening in TSV hole (4) is exposed.
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| CN111180388A (en) * | 2020-03-16 | 2020-05-19 | 西安微电子技术研究所 | Manufacturing method of silicon through hole on wafer without blank area |
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| CN103700617A (en) * | 2013-11-04 | 2014-04-02 | 中国航天科技集团公司第九研究院第七七一研究所 | High-reliability TSV (Through Silicon Via) technique based on SOI (Silicon-On-Insulator) substrate |
| CN104600026A (en) * | 2015-01-30 | 2015-05-06 | 华进半导体封装先导技术研发中心有限公司 | Method for etching surface insulation layer of PAD at bottom of TSV hole of CIS product |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109166822A (en) * | 2018-08-28 | 2019-01-08 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semiconductor device and semiconductor devices |
| US11043448B2 (en) | 2018-08-28 | 2021-06-22 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Semiconductor device with vertically separated openings and manufacturing method thereof |
| CN111180388A (en) * | 2020-03-16 | 2020-05-19 | 西安微电子技术研究所 | Manufacturing method of silicon through hole on wafer without blank area |
| CN111180388B (en) * | 2020-03-16 | 2021-11-30 | 西安微电子技术研究所 | Manufacturing method of silicon through hole on wafer without blank area |
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