US20150076694A1 - Interposer structure and manufacturing method thereof - Google Patents

Interposer structure and manufacturing method thereof Download PDF

Info

Publication number
US20150076694A1
US20150076694A1 US14/025,843 US201314025843A US2015076694A1 US 20150076694 A1 US20150076694 A1 US 20150076694A1 US 201314025843 A US201314025843 A US 201314025843A US 2015076694 A1 US2015076694 A1 US 2015076694A1
Authority
US
United States
Prior art keywords
trenches
layer
area
shallow trenches
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/025,843
Other versions
US9117804B2 (en
Inventor
Chien-Li Kuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to US14/025,843 priority Critical patent/US9117804B2/en
Assigned to UNITED MICROELECTRONICS CORPORATION reassignment UNITED MICROELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUO, CHIEN-LI
Publication of US20150076694A1 publication Critical patent/US20150076694A1/en
Application granted granted Critical
Publication of US9117804B2 publication Critical patent/US9117804B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a manufacturing method for an interposer structure, and more particularly to a manufacturing method for an interposer structure by using fewer masks.
  • the present invention also relates to an interposer structure manufactured by the method.
  • TSV Through-Silicon Via “(hereinafter referred to as TSV) is a 3D packaging technology capable of stacking a plurality of chips vertically in a manner like a sandwich.
  • silicon interposer is accordingly developed.
  • FIG. 1 is a schematic cross-sectional view of a common silicon interposer structure known in prior art. As shown, a plurality of TSV structures 100 (herein in FIG. 1 is exemplified by two TSV structures 100 only) are formed in a silicon substrate 10 , and a dielectric layer 102 and a re-distribution layer (hereinafter referred to as RDL) 101 with specific patterns are formed on one side of the silicon substrate 10 .
  • RDL re-distribution layer
  • the TSV structure 100 is used to provide a via so that the components and/or chips (not shown) disposed on top and bottom of the silicon substrate 10 can have an electrical connection to each other; and the RDL 101 is used to redistribute I/O pads and thereby enabling the related chips to apply in various component modules.
  • the formation of the TSV structures 100 in the silicon interposer is realized by using three masks. Specifically, a first mask is used for the formation of a plurality of shallow trenches on a surface of the silicon substrate 10 , wherein these shallow trenches will be used as alignment marks for the follow-up manufacturing process. Next, a second mask, aligned with the aforementioned alignment marks, is used to define a plurality of deep trenches of the TSV structures 100 . After the deep trenches are formed by performing one or more etching processes, the TSV structures 100 for electrically connecting the components and/or chips disposed on top and bottom of the silicon substrate 10 are formed by performing a metal filling and at least one planarization process to the deep trenches.
  • a dielectric layer is formed on the substrate 10 and a third mask is used to form trenches for the RDL 101 .
  • a metal filling and at least one planarization process are performed to finish fabricating of the RDL 101 . Therefore, at least three masks and multiple metal filling/planarization processes are required for the formation of the TSV structures 100 and the RDL 101 as taught in prior art or conventional related art, and consequentially the conventional interposer structure has a relatively high manufacturing cost.
  • one object of the present invention is to provide an interposer structure, which has a less complicated manufacturing process and a lower manufacturing cost.
  • Another object of the present invention is to provide a manufacturing method for the aforementioned interposer structure.
  • the present invention provides an interposer structure, which includes a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures.
  • the semiconductor substrate has a first surface and a second surface.
  • the shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface, wherein each two adjacent shallow trenches are separated by a portion of the semiconductor substrate.
  • the deep trenches are formed and extending from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface.
  • the metal damascene structures are filled in the shallow trenches and the deep trenches, respectively.
  • the present invention also provides a manufacturing method for an interposer structure.
  • the manufacturing method includes steps of: providing a semiconductor substrate having a first surface and a second surface opposite to each other; performing, with using a first mask, a first patterning process on the first surface to form a plurality of shallow trenches in both of a first area and a second area of the semiconductor substrate; performing, with using a second mask and using the shallow trenches in the first area as alignment marks, a second patterning process through at least one of the shallow trenches in the second area to form a plurality of deep trenches extending from the at least one shallow trench toward the second surface; and performing a metal filling process and at least one planarization process to form a plurality of metal damascene structures in the shallow trenches and the deep trenches.
  • the manufacturing method for an interposer structure of the present invention has a less complicated manufacturing process; and correspondingly the interposer structure manufactured by the aforementioned method has lower cost.
  • FIG. 1 is a schematic cross-sectional view of a silicon interposer structure in prior art.
  • FIGS. 2A-2D are schematic views illustrating a manufacturing process of a silicon interposer structure in accordance with an embodiment of the present invention.
  • FIGS. 2A-2D are schematic views illustrating a manufacturing process for a silicon interposer structure in accordance with an embodiment of the present invention.
  • a substrate 2 having a first surface 28 and a second surface 29 opposite to each other is provided.
  • a first resist pattern (not shown) through performing a first lithography process on the silicon substrate 2 with using a first mask 30 and then performing an etching process with the first defined resist pattern as etching mask, a plurality of shallow trenches (herein the shallow trenches 201 , 202 , 203 and 211 are exemplified in FIG. 2 A) are formed.
  • the first mask 30 is used with a positive photoresist layer (not shown), but it is not intended to limit the present invention.
  • the first mask 30 includes shaded regions and unshaded regions, and only the latter allow light to pass through. After being exposed to an intense light, exposed portions of the positive photoresist layer corresponding to the unshaded regions are soluble to the developer and removed, while unexposed portions of the positive photoresist layer corresponding to the shaded regions are insoluble to the developer and remained intact to protect portions of the first surface 28 in the follow-up etching process. Therefore, the other portions of the first surface 28 which are not protected by the remaining photoresist layer will be etched through.
  • the shallow trenches 201 , 202 , 203 and 211 are formed on the silicon substrate 2 and correspondingly the silicon substrate 2 has a respective number of openings formed on the first surface 28 thereof; wherein it is to be noted that each two adjacent shallow trenches 201 , 202 , 203 , 211 in this embodiment are configured be separate portions of the silicon substrate 2 .
  • the shallow trench 211 located in a scribe-line area 21 is used as a mask alignment mark for the follow-up manufacturing process.
  • the rest of the shallow trenches 201 , 202 and 203 are located in a component area 20 , and are being used for the RDL in the follow-up manufacturing process.
  • the aforementioned lithography process and etching process together may be referred as a patterning process.
  • a second resist pattern (not shown) through performing a second lithography process on the silicon substrate 2 with using a second mask 32 and then performing an etching process with the defined second resist pattern and using the shallow trench 211 in the scribe-line area 21 as a mask alignment mark
  • a plurality of deep trenches (herein the deep trenches 208 , 209 are exemplified in FIG. 2B ) are formed under some or all of the shallow trenches 201 , 202 as illustrated in FIG. 2B .
  • the deep trenches 208 , 209 extend from the shallow trenches 201 , 202 toward the second surface 29 of the semiconductor substrate 2 .
  • the function of the second mask 32 and the related manufacturing processes are similar to that of the first mask 30 , and no redundant detail is to be given herein.
  • the metal filling process may include the following steps: forming a liner oxide layer 22 in each one of the shallow trenches 201 , 202 , 203 and the deep trenches 208 , 209 ; forming a barrier layer 23 on a surface of the liner oxide layer 22 ; forming a seed layer 24 on a surface of the barrier layer 23 ; and forming a metal layer on a surface of the seed layer 24 .
  • a TSV structure 25 and a respective RDL 26 are formed as illustrated in FIG. 2C .
  • the liner oxide layer 22 , the barrier layer 23 , the seed layer 24 and the metal layer are also formed in the shallow trench 211 in the scribe-line area 21 along with other trenches.
  • the present invention is not limited to this structural configuration, and the stack layers may or may not be formed in the shallow trench 211 , which is previously used as a mask alignment mark, according to different applications.
  • the substrate 2 may be other known type of semiconductor substrate; the liner oxide layer 22 may be made of any insulating material such as SiN, SiON, SiC, SiCN, SiO 2 or a combination thereof; the material of the barrier layer 23 may be Ti, TiN, Ta, TaN or a combination thereof; the seed layer 24 may be a copper seed layer; and the metal layer for both the TSV structure 25 and the RDL 26 may be made of copper.
  • the liner oxide layer 22 may be manufactured by thermal oxidation/nitridation method or chemical vapor deposition (CVD) and is used as an isolation layer for both of the TSV structure 25 and the RDL 26 .
  • the planarization process may comprise a chemical-mechanical polishing (CMP) process mainly for polishing the metal (Cu) layer and another CMP process for polishing the barrier layer 23 .
  • the planarization process may only comprise a CMP process mainly for polishing the metal (Cu) layer.
  • the liner oxide layer 22 on the first surface 28 of the silicon substrate 2 may be polished to be completely removed; or, there may be still a portion of the liner oxide layer 22 remaining on the first surface 28 of the silicon substrate 2 for a specific purpose.
  • the metal layer filled in the deep trenches 208 , 209 forms the TSV structure 25 ; wherein each one of the TSV structures 25 has a corresponding opening on the second surface 29 .
  • the present invention has less patterning processes.
  • the formation of the shallow trenches and the deep trenches may have a reverse order.
  • the deep trenches instead of the shallow trenches may be formed in the scribe-line area and used as the mask alignment marks for the formation of the shallow trenches in the component area.
  • the deep trench has a relatively large depth, it is to be noted that using the shallow trenches as mask alignment marks is a preferred option since more effort is required in the wafer cutting process if the deep trenches are formed in the scribe-line area.
  • re-distribution layers may be stacked sequentially on a surface of the re-distribution layer 26 if necessary, and no redundant detail is to be given herein.
  • the manufacturing method for an interposer structure of the present invention has a less complicated manufacturing process; and correspondingly the interposer structure manufactured by the aforementioned method has lower cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a manufacturing method for an interposer structure, and more particularly to a manufacturing method for an interposer structure by using fewer masks. The present invention also relates to an interposer structure manufactured by the method.
    • BACKGROUND OF THE INVENTION
  • Through-Silicon Via “(hereinafter referred to as TSV) is a 3D packaging technology capable of stacking a plurality of chips vertically in a manner like a sandwich. In order to have a higher finesse of chip stack, silicon interposer is accordingly developed.
  • FIG. 1 is a schematic cross-sectional view of a common silicon interposer structure known in prior art. As shown, a plurality of TSV structures 100 (herein in FIG. 1 is exemplified by two TSV structures 100 only) are formed in a silicon substrate 10, and a dielectric layer 102 and a re-distribution layer (hereinafter referred to as RDL) 101 with specific patterns are formed on one side of the silicon substrate 10. Specifically, the TSV structure 100 is used to provide a via so that the components and/or chips (not shown) disposed on top and bottom of the silicon substrate 10 can have an electrical connection to each other; and the RDL 101 is used to redistribute I/O pads and thereby enabling the related chips to apply in various component modules.
  • In the related art, however, the formation of the TSV structures 100 in the silicon interposer is realized by using three masks. Specifically, a first mask is used for the formation of a plurality of shallow trenches on a surface of the silicon substrate 10, wherein these shallow trenches will be used as alignment marks for the follow-up manufacturing process. Next, a second mask, aligned with the aforementioned alignment marks, is used to define a plurality of deep trenches of the TSV structures 100. After the deep trenches are formed by performing one or more etching processes, the TSV structures 100 for electrically connecting the components and/or chips disposed on top and bottom of the silicon substrate 10 are formed by performing a metal filling and at least one planarization process to the deep trenches. Then, a dielectric layer is formed on the substrate 10 and a third mask is used to form trenches for the RDL 101. After the trenches for the RDL are formed, a metal filling and at least one planarization process are performed to finish fabricating of the RDL 101. Therefore, at least three masks and multiple metal filling/planarization processes are required for the formation of the TSV structures 100 and the RDL 101 as taught in prior art or conventional related art, and consequentially the conventional interposer structure has a relatively high manufacturing cost.
    • SUMMARY OF THE INVENTION
  • Therefore, one object of the present invention is to provide an interposer structure, which has a less complicated manufacturing process and a lower manufacturing cost.
  • In addition, another object of the present invention is to provide a manufacturing method for the aforementioned interposer structure.
  • The present invention provides an interposer structure, which includes a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures. The semiconductor substrate has a first surface and a second surface. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface, wherein each two adjacent shallow trenches are separated by a portion of the semiconductor substrate. The deep trenches are formed and extending from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in the shallow trenches and the deep trenches, respectively.
  • The present invention also provides a manufacturing method for an interposer structure. The manufacturing method includes steps of: providing a semiconductor substrate having a first surface and a second surface opposite to each other; performing, with using a first mask, a first patterning process on the first surface to form a plurality of shallow trenches in both of a first area and a second area of the semiconductor substrate; performing, with using a second mask and using the shallow trenches in the first area as alignment marks, a second patterning process through at least one of the shallow trenches in the second area to form a plurality of deep trenches extending from the at least one shallow trench toward the second surface; and performing a metal filling process and at least one planarization process to form a plurality of metal damascene structures in the shallow trenches and the deep trenches.
  • In summary, by using fewer masks, the manufacturing method for an interposer structure of the present invention has a less complicated manufacturing process; and correspondingly the interposer structure manufactured by the aforementioned method has lower cost.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
  • FIG. 1 is a schematic cross-sectional view of a silicon interposer structure in prior art; and
  • FIGS. 2A-2D are schematic views illustrating a manufacturing process of a silicon interposer structure in accordance with an embodiment of the present invention.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
  • FIGS. 2A-2D are schematic views illustrating a manufacturing process for a silicon interposer structure in accordance with an embodiment of the present invention. First, as shown in FIG. 2A, a substrate 2 having a first surface 28 and a second surface 29 opposite to each other is provided. By defining a first resist pattern (not shown) through performing a first lithography process on the silicon substrate 2 with using a first mask 30 and then performing an etching process with the first defined resist pattern as etching mask, a plurality of shallow trenches (herein the shallow trenches 201, 202, 203 and 211 are exemplified in FIG. 2A) are formed. For illustrative purposes only, the first mask 30 is used with a positive photoresist layer (not shown), but it is not intended to limit the present invention. The first mask 30 includes shaded regions and unshaded regions, and only the latter allow light to pass through. After being exposed to an intense light, exposed portions of the positive photoresist layer corresponding to the unshaded regions are soluble to the developer and removed, while unexposed portions of the positive photoresist layer corresponding to the shaded regions are insoluble to the developer and remained intact to protect portions of the first surface 28 in the follow-up etching process. Therefore, the other portions of the first surface 28 which are not protected by the remaining photoresist layer will be etched through. Accordingly, the shallow trenches 201, 202, 203 and 211 are formed on the silicon substrate 2 and correspondingly the silicon substrate 2 has a respective number of openings formed on the first surface 28 thereof; wherein it is to be noted that each two adjacent shallow trenches 201, 202, 203, 211 in this embodiment are configured be separate portions of the silicon substrate 2. Specifically, the shallow trench 211 located in a scribe-line area 21 is used as a mask alignment mark for the follow-up manufacturing process. The rest of the shallow trenches 201, 202 and 203 are located in a component area 20, and are being used for the RDL in the follow-up manufacturing process. In addition, it is understood that the aforementioned lithography process and etching process together may be referred as a patterning process.
  • Next, by defining a second resist pattern (not shown) through performing a second lithography process on the silicon substrate 2 with using a second mask 32 and then performing an etching process with the defined second resist pattern and using the shallow trench 211 in the scribe-line area 21 as a mask alignment mark, a plurality of deep trenches (herein the deep trenches 208, 209 are exemplified in FIG. 2B) are formed under some or all of the shallow trenches 201, 202 as illustrated in FIG. 2B. The deep trenches 208, 209 extend from the shallow trenches 201, 202 toward the second surface 29 of the semiconductor substrate 2. The function of the second mask 32 and the related manufacturing processes are similar to that of the first mask 30, and no redundant detail is to be given herein.
  • Next, by performing a metal filling process and at least one planarization process for both of the shallow trenches and the deep trenches, a plurality of metal damascene structures for all the aforementioned trenches are formed, respectively. The metal filling process may include the following steps: forming a liner oxide layer 22 in each one of the shallow trenches 201, 202, 203 and the deep trenches 208, 209; forming a barrier layer 23 on a surface of the liner oxide layer 22; forming a seed layer 24 on a surface of the barrier layer 23; and forming a metal layer on a surface of the seed layer 24. Thus, a TSV structure 25 and a respective RDL 26 are formed as illustrated in FIG. 2C. Sometimes, the liner oxide layer 22, the barrier layer 23, the seed layer 24 and the metal layer are also formed in the shallow trench 211 in the scribe-line area 21 along with other trenches. However, the present invention is not limited to this structural configuration, and the stack layers may or may not be formed in the shallow trench 211, which is previously used as a mask alignment mark, according to different applications. In this embodiment, it is understood that the substrate 2 may be other known type of semiconductor substrate; the liner oxide layer 22 may be made of any insulating material such as SiN, SiON, SiC, SiCN, SiO2 or a combination thereof; the material of the barrier layer 23 may be Ti, TiN, Ta, TaN or a combination thereof; the seed layer 24 may be a copper seed layer; and the metal layer for both the TSV structure 25 and the RDL 26 may be made of copper. In addition, the liner oxide layer 22 may be manufactured by thermal oxidation/nitridation method or chemical vapor deposition (CVD) and is used as an isolation layer for both of the TSV structure 25 and the RDL 26.
  • Then, by performing at least one planarization process on the silicon substrate 2 together with the metal layer for both the TSV structure 25 and the respective RDL 26, a silicon interposer structure as illustrated in FIG. 2D is formed. In one embodiment, the planarization process may comprise a chemical-mechanical polishing (CMP) process mainly for polishing the metal (Cu) layer and another CMP process for polishing the barrier layer 23. In another embodiment, the planarization process may only comprise a CMP process mainly for polishing the metal (Cu) layer. Specifically, by performing a planarization on the first surface 28 of the silicon substrate 2, the metal layer filled in the shallow trenches 201, 202 and 203 forms the RDL 26. It is to be noted that the liner oxide layer 22 on the first surface 28 of the silicon substrate 2 may be polished to be completely removed; or, there may be still a portion of the liner oxide layer 22 remaining on the first surface 28 of the silicon substrate 2 for a specific purpose. In addition, by performing at least one thinning or grinding or planarization process on the second surface 29 of the silicon substrate 2, the metal layer filled in the deep trenches 208, 209 forms the TSV structure 25; wherein each one of the TSV structures 25 has a corresponding opening on the second surface 29. Thus, compared with the prior art, the present invention has less patterning processes.
  • Based on the concept of the present invention, it is understood that the formation of the shallow trenches and the deep trenches may have a reverse order. The deep trenches instead of the shallow trenches may be formed in the scribe-line area and used as the mask alignment marks for the formation of the shallow trenches in the component area. However, because the deep trench has a relatively large depth, it is to be noted that using the shallow trenches as mask alignment marks is a preferred option since more effort is required in the wafer cutting process if the deep trenches are formed in the scribe-line area.
  • Furthermore, it is understood that another one or more re-distribution layers may be stacked sequentially on a surface of the re-distribution layer 26 if necessary, and no redundant detail is to be given herein.
  • In summary, by using fewer masks, the manufacturing method for an interposer structure of the present invention has a less complicated manufacturing process; and correspondingly the interposer structure manufactured by the aforementioned method has lower cost.
  • While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (15)

What is claimed is:
1. An interposer structure, comprising:
a semiconductor substrate comprising a first surface and a second surface opposite to each other;
a plurality of shallow trenches formed on the first surface in a first area and a second area of the semiconductor substrate, respectively, and a plurality of respective openings are correspondingly being formed on the first surface, wherein each two adjacent shallow trenches are separated by a portion of the semiconductor substrate;
a plurality of deep trenches formed and extending from at least one of the shallow trenches toward the second surface in the second area and a plurality of respective openings being correspondingly formed on the second surface; and
a plurality of metal damascene structures filled in the shallow trenches and the deep trenches.
2. The interposer structure according to claim 1, wherein the semiconductor substrate is a silicon substrate.
3. The interposer structure according to claim 1, wherein the shallow trenches formed in the first area are used as a mask alignment mark for the formation of the deep trenches.
4. The interposer structure according to claim 1, wherein the metal damascene structures filled in the shallow trenches and the deep trenches comprises:
a liner oxide layer formed on a surface of the shallow trenches and the deep trenches;
a barrier layer formed on a surface of the liner oxide layer;
a seed layer formed on a surface of the barrier layer; and
a metal layer formed on a surface of the seed layer.
5. The interposer structure according to claim 4, wherein the liner oxide layer is made of an insulating material of SiN, SiON, SiC, SiCN, SiO2 or a combination thereof; the barrier layer is made of Ti, TiN, Ta, TaN or a combination thereof; the seed layer is a copper seed layer; and the metal layer is a copper layer.
6. The interposer structure according to claim 4, wherein the metal damascene structures filled in the shallow trenches in the second area form a re-distribution layer (RDL).
7. The interposer structure according to claim 4, wherein the metal damascene structures filled in the deep trenches form a through-silicon via (TSV) structure.
8. A manufacturing method for an interposer structure, comprising steps of:
providing a semiconductor substrate having a first surface and a second surface opposite to each other;
performing, with using a first mask, a first patterning process on the first surface to form a plurality of shallow trenches in a first area and a second area of the semiconductor substrate, respectively;
performing, with using a second mask and using the shallow trenches in the first area as alignment marks, a second patterning process through at least one of the shallow trenches in the second area to form a plurality of deep trenches extending from the at least one shallow trench toward the second surface; and
performing a metal filling process and at least one planarization process to form a plurality of metal damascene structures in the shallow trenches and the deep trenches.
9. The manufacturing method according to claim 8, wherein the step of performing the first patterning process or the second patterning process comprises steps of:
performing a lithography process for defining a resist pattern; and
performing an etching process with using the defined resist pattern as an etching mask.
10. The manufacturing method according to claim 8, wherein the metal filling process comprises steps of:
forming a liner oxide layer on a surface of the shallow trenches and the deep trenches;
forming a barrier layer on a surface of the liner oxide layer;
forming a seed layer on a surface of the barrier layer; and
forming a metal layer on a surface of the seed layer.
11. The manufacturing method according to claim 10, wherein the liner oxide layer is made of an insulating material of SiN, SiON, SiC, SiCN, SiO2 or a combination thereof; the barrier layer is made of Ti, TiN, Ta, TaN or a combination thereof; the seed layer is a copper seed layer; and the metal layer is a copper layer.
12. The manufacturing method according to claim 10, wherein the planarization process is performed on the first surface of the semiconductor substrate to form a re-distribution layer including the metal damascene structures filled in the shallow trenches in the second area.
13. The manufacturing method according to claim 10, wherein the planarization process is performed on the second surface of the semiconductor substrate to form a TSV structure including the metal damascene structures filled in the deep trenches.
14. The manufacturing method according to claim 8, wherein each two adjacent shallow trenches are separated by a portion of the semiconductor substrate.
15. The manufacturing method according to claim 8, wherein the first area is a scribe-line area and the second area is a component area.
US14/025,843 2013-09-13 2013-09-13 Interposer structure and manufacturing method thereof Active 2033-10-18 US9117804B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/025,843 US9117804B2 (en) 2013-09-13 2013-09-13 Interposer structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/025,843 US9117804B2 (en) 2013-09-13 2013-09-13 Interposer structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
US20150076694A1 true US20150076694A1 (en) 2015-03-19
US9117804B2 US9117804B2 (en) 2015-08-25

Family

ID=52667261

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/025,843 Active 2033-10-18 US9117804B2 (en) 2013-09-13 2013-09-13 Interposer structure and manufacturing method thereof

Country Status (1)

Country Link
US (1) US9117804B2 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150170994A1 (en) * 2013-12-16 2015-06-18 Globalfoundries Singapore Pte. Ltd. Tsv without zero alignment marks
US20150262866A1 (en) * 2014-03-11 2015-09-17 Thorsten Meyer Integrated circuit package
CN105428309A (en) * 2015-12-16 2016-03-23 华进半导体封装先导技术研发中心有限公司 Manufacturing technological method for TSV through hole, and manufacturing technological method for blind hole or TSV through hole of multiple hole depths
US20170025384A1 (en) * 2015-07-22 2017-01-26 Samsung Electronics Co., Ltd. Semiconductor chip and semiconductor package having the same
US9786605B1 (en) * 2016-05-27 2017-10-10 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US20180108540A1 (en) * 2016-10-13 2018-04-19 Samsung Electronics Co., Ltd. Method of forming an interposer and a method of manufacturing a semiconductor package including the same
US10312181B2 (en) 2016-05-27 2019-06-04 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US10396012B2 (en) 2016-05-27 2019-08-27 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
CN112185934A (en) * 2019-07-05 2021-01-05 力晶积成电子制造股份有限公司 Method for producing mark
GB2587374A (en) * 2019-09-25 2021-03-31 X Fab Semiconductor Foundries Through silicon via and redistribution layer
US20220223558A1 (en) * 2019-08-27 2022-07-14 Mitsubishi Electric Corporation Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110828372A (en) * 2019-11-11 2020-02-21 武汉新芯集成电路制造有限公司 Metal lead, semiconductor device and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
US20020000583A1 (en) * 1995-11-09 2002-01-03 Goro Kitsukawa System with meshed power and signal buses on cell array
US7381646B2 (en) * 2005-08-15 2008-06-03 Chartered Semiconductor Manufacturing, Ltd. Method for using a Cu BEOL process to fabricate an integrated circuit (IC) originally having an al design
US7633165B2 (en) * 2007-12-21 2009-12-15 Taiwan Semiconductor Manfacturing Company, Ltd. Introducing a metal layer between SiN and TiN to improve CBD contact resistance for P-TSV

Family Cites Families (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514818A1 (en) 1951-01-28 1969-05-08 Telefunken Patent Solid-state circuit, consisting of a semiconductor body with inserted active components and an insulating layer with applied passive components and conductor tracks
US3150299A (en) 1959-09-11 1964-09-22 Fairchild Camera Instr Co Semiconductor circuit complex having isolation means
US3256465A (en) 1962-06-08 1966-06-14 Signetics Corp Semiconductor device assembly with true metallurgical bonds
US3343256A (en) 1964-12-28 1967-09-26 Ibm Methods of making thru-connections in semiconductor wafers
US3323198A (en) 1965-01-27 1967-06-06 Texas Instruments Inc Electrical interconnections
US3372070A (en) 1965-07-30 1968-03-05 Bell Telephone Labor Inc Fabrication of semiconductor integrated devices with a pn junction running through the wafer
US3648131A (en) 1969-11-07 1972-03-07 Ibm Hourglass-shaped conductive connection through semiconductor structures
US4394712A (en) 1981-03-18 1983-07-19 General Electric Company Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US4395302A (en) 1981-12-10 1983-07-26 Enthone Incorporated Metal dissolution process using H2 O2 --H2 SO4 etchant
US4616247A (en) 1983-11-10 1986-10-07 At&T Bell Laboratories P-I-N and avalanche photodiodes
KR900008647B1 (en) 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 A method for manufacturing three demensional i.c.
US4773972A (en) 1986-10-30 1988-09-27 Ford Motor Company Method of making silicon capacitive pressure sensor with glass layer between silicon wafers
US5463246A (en) 1988-12-29 1995-10-31 Sharp Kabushiki Kaisha Large scale high density semiconductor apparatus
US5399898A (en) 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
JP3004071B2 (en) 1991-04-16 2000-01-31 日本特殊陶業株式会社 Package for integrated circuit
US5214000A (en) 1991-12-19 1993-05-25 Raychem Corporation Thermal transfer posts for high density multichip substrates and formation method
US5372969A (en) 1991-12-31 1994-12-13 Texas Instruments Incorporated Low-RC multi-level interconnect technology for high-performance integrated circuits
WO1995009438A1 (en) 1993-09-30 1995-04-06 Kopin Corporation Three-dimensional processor using transferred thin film circuits
US5484073A (en) 1994-03-28 1996-01-16 I/O Sensors, Inc. Method for fabricating suspension members for micromachined sensors
US5502333A (en) 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5627106A (en) 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
JP2001525120A (en) 1996-11-08 2001-12-04 ダブリュ．エル．ゴア アンド アソシエイツ，インコーポレイティド Using light-absorbing coatings to improve the quality of both blind and through micro-via entrances
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US6143616A (en) 1997-08-22 2000-11-07 Micron Technology, Inc. Methods of forming coaxial integrated circuitry interconnect lines
US6309956B1 (en) 1997-09-30 2001-10-30 Intel Corporation Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US20010038972A1 (en) 1998-11-20 2001-11-08 Christopher F. Lyons Ultra-thin resist shallow trench process using metal hard mask
US6162587A (en) 1998-12-01 2000-12-19 Advanced Micro Devices Thin resist with transition metal hard mask for via etch application
US6274937B1 (en) 1999-02-01 2001-08-14 Micron Technology, Inc. Silicon multi-chip module packaging with integrated passive components and method of making
US6573565B2 (en) 1999-07-28 2003-06-03 International Business Machines Corporation Method and structure for providing improved thermal conduction for silicon semiconductor devices
US6483147B1 (en) 1999-10-25 2002-11-19 Advanced Micro Devices, Inc. Through wafer backside contact to improve SOI heat dissipation
US6633083B2 (en) 2000-02-28 2003-10-14 Advanced Micro Devices Inc. Barrier layer integrity test
JP4979154B2 (en) * 2000-06-07 2012-07-18 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4023076B2 (en) 2000-07-27 2007-12-19 富士通株式会社 Front and back conductive substrate and manufacturing method thereof
US6407002B1 (en) 2000-08-10 2002-06-18 Taiwan Semiconductor Manufacturing Company Partial resist free approach in contact etch to improve W-filling
JP2002134658A (en) 2000-10-24 2002-05-10 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
US6805614B2 (en) 2000-11-30 2004-10-19 Texas Instruments Incorporated Multilayered CMP stop for flat planarization
US6391777B1 (en) 2001-05-02 2002-05-21 Taiwan Semiconductor Manufacturing Company Two-stage Cu anneal to improve Cu damascene process
US6812193B2 (en) 2001-08-31 2004-11-02 International Business Machines Corporation Slurry for mechanical polishing (CMP) of metals and use thereof
US6831013B2 (en) 2001-11-13 2004-12-14 United Microelectronics Corp. Method of forming a dual damascene via by using a metal hard mask layer
US7126214B2 (en) 2001-12-05 2006-10-24 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
US6627985B2 (en) 2001-12-05 2003-09-30 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
US6525419B1 (en) 2002-02-14 2003-02-25 Intel Corporation Thermally coupling electrically decoupling cooling device for integrated circuits
US6778275B2 (en) 2002-02-20 2004-08-17 Micron Technology, Inc. Aberration mark and method for estimating overlay error and optical aberrations
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6930048B1 (en) 2002-09-18 2005-08-16 Lam Research Corporation Etching a metal hard mask for an integrated circuit structure
JP2004140286A (en) 2002-10-21 2004-05-13 Nec Semiconductors Kyushu Ltd Semiconductor device and its manufacturing method
KR100480897B1 (en) 2002-12-09 2005-04-07 매그나칩 반도체 유한회사 Method for manufacturing STI of semiconductor device
CN1751405B (en) 2003-02-20 2010-12-08 三菱化学株式会社 Negative-electrode for lithium secondary battery and lithium secondary battery
US7449780B2 (en) 2003-03-31 2008-11-11 Intel Corporation Apparatus to minimize thermal impedance using copper on die backside
US6897148B2 (en) 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US7083495B2 (en) 2003-11-26 2006-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced process control approach for Cu interconnect wiring sheet resistance control
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7420277B2 (en) 2004-03-16 2008-09-02 Taiwan Semiconductor Manufacturing Company, Ltd System for heat dissipation in semiconductor devices
JP4439976B2 (en) 2004-03-31 2010-03-24 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7075133B1 (en) 2004-05-03 2006-07-11 National Semiconductor Corporation Semiconductor die with heat and electrical pipes
TWI237316B (en) 2004-08-24 2005-08-01 Chipmos Technologies Inc Electronic device having pin electrode with slight warpage
US7098070B2 (en) 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
US7396732B2 (en) 2004-12-17 2008-07-08 Interuniversitair Microelektronica Centrum Vzw (Imec) Formation of deep trench airgaps and related applications
JP4577687B2 (en) 2005-03-17 2010-11-10 エルピーダメモリ株式会社 Semiconductor device
US7166913B2 (en) 2005-04-19 2007-01-23 International Business Machines Corporation Heat dissipation for heat generating element of semiconductor device and related method
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US20070126085A1 (en) 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
JP2007165461A (en) 2005-12-12 2007-06-28 Elpida Memory Inc Semiconductor device and manufacturing method thereof
US7563714B2 (en) 2006-01-13 2009-07-21 International Business Machines Corporation Low resistance and inductance backside through vias and methods of fabricating same
US7427803B2 (en) 2006-09-22 2008-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Electromagnetic shielding using through-silicon vias
US8026169B2 (en) 2006-11-06 2011-09-27 Advanced Micro Devices, Inc. Cu annealing for improved data retention in flash memory devices
US7795735B2 (en) 2007-03-21 2010-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming single dies with multi-layer interconnect structures and structures formed therefrom
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
KR101336569B1 (en) 2007-05-22 2013-12-03 삼성전자주식회사 Semiconductor Packages With Enhanced Joint Reliability And Methods Of Fabricating The Same
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7825517B2 (en) 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
KR101341586B1 (en) 2007-08-30 2013-12-16 삼성전자주식회사 Semiconductor integrated circuit device and fabricating method of the same
JP2009129953A (en) 2007-11-20 2009-06-11 Hitachi Ltd Semiconductor device
US20090127667A1 (en) 2007-11-21 2009-05-21 Powertech Technology Inc. Semiconductor chip device having through-silicon-via (TSV) and its fabrication method
KR101420817B1 (en) 2008-01-15 2014-07-21 삼성전자주식회사 Semiconductor Integrated Circuit Device Electrically Connecting Integrated Circuit Modules Stacked Sequentially With 3-Dimensional Serial And Parallel Circuits And Method Of Forming The Same
US8486823B2 (en) 2008-03-07 2013-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming through via
US7812426B2 (en) 2008-05-30 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV-enabled twisted pair
KR20100003911A (en) 2008-07-02 2010-01-12 삼성전자주식회사 Multi-chip package having three dimension mesh-based power distribution network and power distribution method thereof
US7851346B2 (en) 2008-07-21 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding metallurgy for three-dimensional interconnect
KR20100021856A (en) 2008-08-18 2010-02-26 삼성전자주식회사 Method of forming semiconductor device having tsv and related device
US7956442B2 (en) 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US7846837B2 (en) 2008-10-09 2010-12-07 United Microelectronics Corp. Through substrate via process
US8053900B2 (en) 2008-10-21 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect
US7955895B2 (en) 2008-11-07 2011-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for stacked wafer fabrication
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8053902B2 (en) 2008-12-02 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure for protecting dielectric layers from degradation
US8227889B2 (en) 2008-12-08 2012-07-24 United Microelectronics Corp. Semiconductor device
US8168470B2 (en) 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
US8049327B2 (en) 2009-01-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with scalloped sidewalls
US7932608B2 (en) 2009-02-24 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via formed with a post passivation interconnect structure
US8329578B2 (en) 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
US8202766B2 (en) 2009-06-19 2012-06-19 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8344512B2 (en) 2009-08-20 2013-01-01 International Business Machines Corporation Three-dimensional silicon interposer for low voltage low power systems
US8053898B2 (en) 2009-10-05 2011-11-08 Samsung Electronics Co., Ltd. Connection for off-chip electrostatic discharge protection
US7969013B2 (en) 2009-10-22 2011-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via with dummy structure and method for forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US20020000583A1 (en) * 1995-11-09 2002-01-03 Goro Kitsukawa System with meshed power and signal buses on cell array
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
US7381646B2 (en) * 2005-08-15 2008-06-03 Chartered Semiconductor Manufacturing, Ltd. Method for using a Cu BEOL process to fabricate an integrated circuit (IC) originally having an al design
US7633165B2 (en) * 2007-12-21 2009-12-15 Taiwan Semiconductor Manfacturing Company, Ltd. Introducing a metal layer between SiN and TiN to improve CBD contact resistance for P-TSV

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9437550B2 (en) * 2013-12-16 2016-09-06 Globalfoundries Singapore Pte. Ltd. TSV without zero alignment marks
US20150170994A1 (en) * 2013-12-16 2015-06-18 Globalfoundries Singapore Pte. Ltd. Tsv without zero alignment marks
US10157869B2 (en) 2014-03-11 2018-12-18 Intel Corporation Integrated circuit package
US20150262866A1 (en) * 2014-03-11 2015-09-17 Thorsten Meyer Integrated circuit package
US9472515B2 (en) * 2014-03-11 2016-10-18 Intel Corporation Integrated circuit package
US20170025384A1 (en) * 2015-07-22 2017-01-26 Samsung Electronics Co., Ltd. Semiconductor chip and semiconductor package having the same
CN105428309A (en) * 2015-12-16 2016-03-23 华进半导体封装先导技术研发中心有限公司 Manufacturing technological method for TSV through hole, and manufacturing technological method for blind hole or TSV through hole of multiple hole depths
US10312181B2 (en) 2016-05-27 2019-06-04 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US9786605B1 (en) * 2016-05-27 2017-10-10 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US10396012B2 (en) 2016-05-27 2019-08-27 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US10396013B2 (en) 2016-05-27 2019-08-27 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US20180108540A1 (en) * 2016-10-13 2018-04-19 Samsung Electronics Co., Ltd. Method of forming an interposer and a method of manufacturing a semiconductor package including the same
CN112185934A (en) * 2019-07-05 2021-01-05 力晶积成电子制造股份有限公司 Method for producing mark
US20220223558A1 (en) * 2019-08-27 2022-07-14 Mitsubishi Electric Corporation Semiconductor device
US12113040B2 (en) * 2019-08-27 2024-10-08 Mitsubishi Electric Corporation Semiconductor device
GB2587374A (en) * 2019-09-25 2021-03-31 X Fab Semiconductor Foundries Through silicon via and redistribution layer
GB2587374B (en) * 2019-09-25 2022-08-17 X Fab Semiconductor Foundries Gmbh Through silicon via and redistribution layer
US11795051B2 (en) * 2019-09-25 2023-10-24 X-Fab Semiconductor Foundries Gmbh Through silicon via and redistribution layer

Also Published As

Publication number Publication date
US9117804B2 (en) 2015-08-25

Similar Documents

Publication Publication Date Title
US9117804B2 (en) Interposer structure and manufacturing method thereof
US10964692B2 (en) Through silicon via design for stacking integrated circuits
US10777539B2 (en) Seal-ring structure for stacking integrated circuits
US10157891B2 (en) 3DIC interconnect apparatus and method
US20230378139A1 (en) 3DIC Interconnect Apparatus and Method
US10840287B2 (en) 3DIC interconnect apparatus and method
US20220359433A1 (en) Forming Large Chips Through Stitching
US9691840B2 (en) Cylindrical embedded capacitors
US8421238B2 (en) Stacked semiconductor device with through via
CN109856931A (en) Semiconductor device and its manufacturing method
US20130341799A1 (en) Through silicon via structure and method of fabricating the same
US9293343B2 (en) Method of forming patterns of semiconductor device
US20230020810A1 (en) Method of fabricating integrated circuit device
CN103811415A (en) Through-substrate via formation with improved topography control
JP2014011309A (en) Semiconductor device and manufacturing method of the same
US11094662B1 (en) Semiconductor assembly and method of manufacturing the same
TWI768380B (en) Semiconductor structure and method for forming the same
US20140147984A1 (en) Semiconductor device and method of fabricating through silicon via structure
US11315904B2 (en) Semiconductor assembly and method of manufacturing the same
TW201742104A (en) Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices
TW202410378A (en) Semiconductor device having inductor and method of manufacturing thereof
CN118053770A (en) Semiconductor structure, forming method thereof and packaging structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KUO, CHIEN-LI;REEL/FRAME:031198/0085

Effective date: 20130901

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8