CN104347481A - Metal coating processing method - Google Patents
Metal coating processing method Download PDFInfo
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- CN104347481A CN104347481A CN201310330145.3A CN201310330145A CN104347481A CN 104347481 A CN104347481 A CN 104347481A CN 201310330145 A CN201310330145 A CN 201310330145A CN 104347481 A CN104347481 A CN 104347481A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Abstract
The invention discloses a metal coating processing method comprising following steps of: providing a substrate equipped with through holes; filling the through holes on the substrate with metal and forming a metallic layer on the surface of the substrate; polishing the metallic layer to near the surface of the substrate in a stress-free electrochemical polishing manner; carrying out an annealing process on the metallic layer on the surface of the substrate and forming metallic protrusions on the metallic layer over the through holes; and removing the metallic layer on the surface of the substrate and the metallic protrusions over the through holes and just leaving the metal in through holes. Usually, the metallic layer on the surface of the substrate and the metallic protrusions over the through holes are removed in a chemical mechanical polishing manner. The metal coating processing method integrates stress-free electrochemical polishing, chemical mechanical polishing, and the annealing process, breaks through a technical bottleneck that the internal stress of the metallic layer causes the warping of the substrate and the metallic protrusions over the through holes, and improves the quality of integrated circuit devices.
Description
Technical field
The present invention relates to method for manufacturing integrated circuit, particularly relate to a kind of coat of metal processing method.
Background technology
In recent years, silicon through hole (TSV) technology has become the focus that microelectronic industry is paid close attention to, TSV technology is by making vertical conducting between chip and chip, between wafer and wafer, realize the state-of-the-art technology interconnected to each other, encapsulate bonding from IC in the past and use the superimposing technique of salient point different, TSV can make chip maximum in the density that three-dimensional is stacking, and overall dimension is minimum, and greatly improves the performance of chip speed and low-power consumption.The key technology of TSV is Z axis interconnection and electric isolution technology, comprising: the formation of through hole, stacking form, bonding pattern, insulating barrier, barrier layer and the deposit of Seed Layer, the filling (plating) of copper and removal, distribute that lead-in wire (RDL) is electroplated, wafer is thinning again, measurement and detection etc.
Because the through hole in TSV technology has larger depth-to-width ratio, generally from 5:1 to 10:1, even 20:1, large depth-to-width ratio can cause fills in the technique of copper in plating, and through hole cannot fill up.In order to fill up through hole, do not produce space in through hole, the excessive plating of meeting usually, causes substrate (wafer or chip) surface metal layers of copper blocked up thus, is generally 3 to 5 microns.And the stress in metal copper layer increases along with the increase of metal copper layer thickness, the stress in metal copper layer crosses conference makes substrate form warpage.The conventional method removing substrate surface metal copper layer is cmp (CMP), simultaneously in conjunction with annealing process.Although annealing process can obtain lower film resiativity and good electromigration resisting property, eliminate metal grain defect, but after annealing process, metal copper layer internal stress increases, and substrate warpage is even more serious, and the metal copper layer above through hole especially can be caused to form projection.When removing the metal copper layer of substrate surface in the mode of cmp, the stronger downforce that cmp produces can make the substrate of warpage break, if the metal bump above through hole is comparatively large, cmp effectively can not remove the metal bump above through hole.
Summary of the invention
The object of this invention is to provide a kind of coat of metal processing method, the method can not only break through because metal level internal stress causes the warpage of substrate and the technical bottleneck of through hole upper metal projection, and can improve the quality of integrated circuit (IC)-components.
For achieving the above object, the coat of metal processing method that the present invention proposes, comprise the following steps: provide substrate, substrate is formed with through hole; Metal is filled and at the forming metal layer on surface of substrate in the through hole of substrate; Metal level is polished to the surface close to substrate in the mode of unstressed electrochemical polish; Carry out annealing process to the metal level of substrate surface, the metal level above through hole forms metal bump; Remove the metal bump above the metal level of substrate surface and through hole, only retain the metal in through hole.
In one embodiment, the metal bump removed above the metal level of substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of cmp.
In one embodiment, the metal bump removed above the metal level of substrate surface and through hole comprises: the metal level first removing substrate surface in the mode of cmp, and then removes the metal bump above through hole in the mode of unstressed electrochemical polish.
In one embodiment, substrate is dielectric layer, and through hole is formed in dielectric layer, and through hole just extending towards the back side of dielectric layer from dielectric layer, the front of the diapire of through hole and sidewall and dielectric layer is formed with barrier layer, and metal level is formed on barrier layer.
For achieving the above object, the another coat of metal processing method that the present invention proposes, comprise the following steps: provide substrate, substrate is formed with through hole; Metal is filled and at the forming metal layer on surface of substrate in the through hole of substrate; Carry out annealing process to the metal level of substrate surface, the metal level above through hole forms metal bump; Metal level is polished to the surface close to substrate in the mode of unstressed electrochemical polish; Remove the metal bump above the metal level of substrate surface and through hole, only retain the metal in through hole.
In one embodiment, the metal bump removed above the metal level of substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of cmp.
In one embodiment, before removing the metal bump above the metal level of substrate surface and through hole, second time annealing process is carried out to the metal level of substrate surface.The metal bump removed above the metal level of substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of cmp.
In one embodiment, before removing the metal bump above the metal level of substrate surface and through hole, second time annealing process is carried out to the metal level of substrate surface.The metal bump removed above the metal level of substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of unstressed electrochemical polish.
In one embodiment, substrate is dielectric layer, and through hole is formed in dielectric layer, and through hole just extending towards the back side of dielectric layer from dielectric layer, the front of the diapire of through hole and sidewall and dielectric layer is formed with barrier layer, and metal level is formed on barrier layer.
In sum, coat of metal processing method of the present invention is by integrating unstressed electrochemical polish, cmp and annealing process, breach because metal level internal stress causes the warpage of substrate and the technical bottleneck of through hole upper metal projection, improve the quality of integrated circuit (IC)-components.
Accompanying drawing explanation
Fig. 1 (a) to Fig. 1 (d) discloses the schematic flow sheet of coat of metal processing method according to a first embodiment of the present invention.
Fig. 2 (a) to Fig. 2 (e) discloses the schematic flow sheet of coat of metal processing method according to a second embodiment of the present invention.
Fig. 3 (a) to Fig. 3 (d) discloses the schematic flow sheet of coat of metal processing method according to a third embodiment of the present invention.
Fig. 4 (a) to Fig. 4 (e) discloses the schematic flow sheet of coat of metal processing method according to a fourth embodiment of the present invention.
Fig. 5 (a) to Fig. 5 (e) discloses the schematic flow sheet of coat of metal processing method according to a fifth embodiment of the present invention.
Embodiment
By describing technology contents of the present invention in detail, reached object and effect, coordinate graphic being described in detail below in conjunction with embodiment.
Consult Fig. 1 (a) to Fig. 1 (d), disclose the schematic flow sheet of coat of metal processing method according to a first embodiment of the present invention.As shown in Fig. 1 (a), the through hole of TSV is formed in substrate, and in the present invention, substrate is dielectric layer 110, through hole just extending towards the back side of dielectric layer 110 from dielectric layer 110.In order to prevent metal, usual preferable alloy copper, spread to dielectric layer 110, barrier layer 112 is formed at the diapire of through hole and the front of sidewall and dielectric layer 110, the material on barrier layer 112 can be tantalum, tantalum nitride, titanium, titanium nitride or their combination, barrier layer 112 is except preventing metal to except dielectric layer 110 diffusion, and barrier layer 112 can also be the tack coat between metal and dielectric layer 110.Then, on barrier layer 112, metal seed layer is formed in the mode of physical vapour deposition (PVD).Then, carry out metal plating in the mode of electrochemistry plating (ECP), metal 114 fills up through hole and formed on the surface on barrier layer 112 has certain thickness metal level, and Fig. 1 (a) is the generalized section after electrochemical plating processes.
Next, need to carry out planarization to the metal level on barrier layer 112, to remove metal level, only retain the metal 114 in through hole.First, in the mode of unstressed electrochemical polish, metal level is polished to close to barrier layer 112.The U.S. Patent Application No. US10/590 that the applicant of the applicant proposed on February 23rd, 2005, electrochemical polishing method disclosed in 460 and device are all applicable to the present invention, therefore only briefly introduce to unstressed electrochemical polishing method at this.In one embodiment, unstressed electrochemical polishing method can comprise the following steps: first, makes nozzle be positioned at the center of close substrate; Then, rotate substrate, when substrate rotates, nozzle to the metal level supply electrolyte on substrate, thus starts electrochemical polish; Then, moving substrate, by the center of substrate to the metal level on edge electric chemical polishing substrate.The object adopting the mode of unstressed electrochemical polish to be polished to by metal level close to barrier layer 112 is to discharge metal level internal stress by thinning for continuous print metal level.After electrochemical plating processes, although metal level internal stress causes dielectric layer 110 warpage, but due to can not mechanical force be produced during unstressed electrochemical polish, therefore unstressed electrochemical polish can not damage dielectric layer 110, as shown in Fig. 1 (b), Fig. 1 (b) is the generalized section after unstressed electrochemical polishing process.
Then, annealing process is carried out to metal level, because metal level is thinning, after annealing process, it is less that metal level internal stress increases, and the metal bump thus formed above through hole is less, as shown in Fig. 1 (c), Fig. 1 (c) is the generalized section after annealing process.Finally, all removed by the metal 114 beyond through hole in the mode of CMP, only retain the metal 114 in through hole, as shown in Figure 1 (d) shows, Fig. 1 (d) is the generalized section after CMP.
Consult Fig. 2 (a) to Fig. 2 (e), disclose the schematic flow sheet of coat of metal processing method according to a second embodiment of the present invention.As shown in Figure 2 (a) shows, the through hole of TSV is formed in dielectric layer 210, through hole just extending towards the back side of dielectric layer 210 from dielectric layer 210.In order to prevent metal, usual preferable alloy copper, spread to dielectric layer 210, barrier layer 212 is formed at the diapire of through hole and the front of sidewall and dielectric layer 210, the material on barrier layer 212 can be tantalum, tantalum nitride, titanium, titanium nitride or their combination, barrier layer 212 is except preventing metal to except dielectric layer 210 diffusion, and barrier layer 212 can also be the tack coat between metal and dielectric layer 210.Then, on barrier layer 212, metal seed layer is formed in the mode of physical vapour deposition (PVD).Then, carry out metal plating in the mode of electrochemistry plating (ECP), metal 214 fills up through hole and formed on the surface on barrier layer 212 has certain thickness metal level, and Fig. 2 (a) is the generalized section after electrochemical plating processes.
Next, need to carry out planarization to the metal level on barrier layer 212, to remove metal level, only retain the metal 214 in through hole.First, in the mode of unstressed electrochemical polish, metal level is polished to close to barrier layer 212, object is by thinning for continuous print metal level to discharge metal level internal stress, and as shown in Fig. 2 (b), Fig. 2 (b) is the generalized section after unstressed electrochemical polishing process.The method of unstressed electrochemical polish described here is identical with the unstressed electrochemical polishing method described in the first embodiment, therefore does not repeat them here.Then, annealing process is carried out to metal level, because metal level is thinning, after annealing process, it is less that metal level internal stress increases, and the metal bump thus formed above through hole is less, as shown in Figure 2 (c), Fig. 2 (c) is the generalized section after annealing process.Then, with the metal level of the mode planarization remainder of CMP, owing to being formed with metal bump above through hole, cmp may metal bump completely above planarization through hole, and make the metal projection that the metal bump above through hole becomes isolated, if adopt the mode of CMP to continue abrasive metal projection, the mechanical shear stress that cmp produces can cause the damage of through-hole side wall dielectric layer 210, and then the integrated circuit (IC)-components made was lost efficacy, as shown in Figure 2 (d) shows, Fig. 2 (d) is the generalized section after CMP.In order to overcome the defect that cmp exists, finally, in the mode of unstressed electrochemical polish, the metal bump above through hole is removed, only retain the metal 214 in through hole, as shown in Fig. 2 (e), Fig. 2 (e) is the generalized section after unstressed electrochemical polishing process.
Consult Fig. 3 (a) to Fig. 3 (d), disclose the schematic flow sheet of coat of metal processing method according to a third embodiment of the present invention.As shown in Fig. 3 (a), the through hole of TSV is formed in dielectric layer 310, through hole just extending towards the back side of dielectric layer 310 from dielectric layer 310.In order to prevent metal, usual preferable alloy copper, spread to dielectric layer 310, barrier layer 312 is formed at the diapire of through hole and the front of sidewall and dielectric layer 310, the material on barrier layer 312 can be tantalum, tantalum nitride, titanium, titanium nitride or their combination, barrier layer 312 is except preventing metal to except dielectric layer 310 diffusion, and barrier layer 312 can also be the tack coat between metal and dielectric layer 310.Then, on barrier layer 312, metal seed layer is formed in the mode of physical vapour deposition (PVD).Then, carry out metal plating in the mode of electrochemistry plating (ECP), metal 314 fills up through hole and formed on the surface on barrier layer 312 has certain thickness metal level, and Fig. 3 (a) is the generalized section after electrochemical plating processes.
Next, need to carry out planarization to the metal level on barrier layer 312, to remove metal level, only retain the metal 314 in through hole.First, annealing process is carried out to metal level, object obtains lower film resiativity and good electromigration resisting property, eliminate metal grain defect, but metal level internal stress increases after annealing process, thus cause the metal level above through hole to form projection, as shown in Figure 3 (b), Fig. 3 (b) is the generalized section after annealing process.Then, in the mode of unstressed electrochemical polish, metal level is polished to close to barrier layer 312, object is to discharge metal level internal stress by thinning for continuous print metal level, simultaneously to the removal that the metal bump above through hole is carried out to a certain degree, as shown in Figure 3 (c), Fig. 3 (c) is the generalized section after unstressed electrochemical polishing process.The method of unstressed electrochemical polish described here is identical with the unstressed electrochemical polishing method described in the first embodiment, therefore does not repeat them here.Finally, with the metal bump above the metal level of the mode planarization remainder of CMP and through hole, only retain the metal 314 in through hole, as shown in Fig. 3 (d), Fig. 3 (d) is the generalized section after CMP.Because metal level internal stress major part discharges, during metal bump above the metal level of cmp remainder and through hole, damage can not be caused to dielectric layer 310.
Consult Fig. 4 (a) to Fig. 4 (e), disclose the schematic flow sheet of coat of metal processing method according to a fourth embodiment of the present invention.As shown in Figure 4 (a), the through hole of TSV is formed in dielectric layer 410, through hole just extending towards the back side of dielectric layer 410 from dielectric layer 410.In order to prevent metal, usual preferable alloy copper, spread to dielectric layer 410, barrier layer 412 is formed at the diapire of through hole and the front of sidewall and dielectric layer 410, the material on barrier layer 412 can be tantalum, tantalum nitride, titanium, titanium nitride or their combination, barrier layer 412 is except preventing metal to except dielectric layer 410 diffusion, and barrier layer 412 can also be the tack coat between metal and dielectric layer 410.Then, on barrier layer 412, metal seed layer is formed in the mode of physical vapour deposition (PVD).Then, carry out metal plating in the mode of electrochemistry plating (ECP), metal 414 fills up through hole and formed on the surface on barrier layer 412 has certain thickness metal level, and Fig. 4 (a) is the generalized section after electrochemical plating processes.
Next, need to carry out planarization to the metal level on barrier layer 412, to remove metal level, only retain the metal 414 in through hole.First, first time annealing process is carried out to metal level, object obtains lower film resiativity and good electromigration resisting property, eliminate metal grain defect, but metal level internal stress increases after annealing process, thus cause the metal level above through hole to form projection, as shown in Figure 4 (b), Fig. 4 (b) is the generalized section after first time annealing process.Then, in the mode of unstressed electrochemical polish, metal level is polished to close to barrier layer 412, object is to discharge metal level internal stress by thinning for continuous print metal level, simultaneously to the removal that the metal bump above through hole is carried out to a certain degree, as shown in Figure 4 (c), Fig. 4 (c) is the generalized section after unstressed electrochemical polishing process.The method of unstressed electrochemical polish described here is identical with the unstressed electrochemical polishing method described in the first embodiment, therefore does not repeat them here.Then, carry out second time annealing process to the metal level of remainder, as shown in Fig. 4 (d), Fig. 4 (d) is the generalized section after second time annealing process.Adopt twice annealing technique in the present embodiment, its benefit is: after electrochemical plating processes, and the time of metal level being carried out to first time annealing process is shorter, and temperature is lower, thus the metal level internal stress increase that annealing process is caused reduces as far as possible; After unstressed electrochemical polish, metal level is thinning, metal level internal stresses release, and then to metal level carry out second time annealing process time can be shorter, temperature can be lower, after annealing process, the increase of metal level internal stress is less, therefore, the metal bump above through hole is less, and, at twice to metal level annealing, the angularity of dielectric layer 410 can be reduced.Finally, with the metal bump above the metal level of the mode planarization remainder of CMP and through hole, only retain the metal 414 in through hole, as shown in Fig. 4 (e), Fig. 4 (e) is the generalized section after CMP.
Consult Fig. 5 (a) to Fig. 5 (e), disclose the schematic flow sheet of coat of metal processing method according to a fifth embodiment of the present invention.As shown in Fig. 5 (a), the through hole of TSV is formed in dielectric layer 510, through hole just extending towards the back side of dielectric layer 510 from dielectric layer 510.In order to prevent metal, usual preferable alloy copper, spread to dielectric layer 510, barrier layer 512 is formed at the diapire of through hole and the front of sidewall and dielectric layer 510, the material on barrier layer 512 can be tantalum, tantalum nitride, titanium, titanium nitride or their combination, barrier layer 512 is except preventing metal to except dielectric layer 510 diffusion, and barrier layer 512 can also be the tack coat between metal and dielectric layer 510.Then, on barrier layer 512, metal seed layer is formed in the mode of physical vapour deposition (PVD).Then, carry out metal plating in the mode of electrochemistry plating (ECP), metal 514 fills up through hole and formed on the surface on barrier layer 512 has certain thickness metal level, and Fig. 5 (a) is the generalized section after electrochemical plating processes.
Next, need to carry out planarization to the metal level on barrier layer 512, to remove metal level, only retain the metal 514 in through hole.First, first time annealing process is carried out to metal level, object obtains lower film resiativity and good electromigration resisting property, eliminate metal grain defect, but metal level internal stress increases after annealing process, thus cause the metal level above through hole to form projection, as shown in Fig. 5 (b), Fig. 5 (b) is the generalized section after first time annealing process.Then, in the mode of unstressed electrochemical polish, metal level is polished to close to barrier layer 512, object is to discharge metal level internal stress by thinning for continuous print metal level, simultaneously to the removal that the metal bump above through hole is carried out to a certain degree, as shown in Fig. 5 (c), Fig. 5 (c) is the generalized section after unstressed electrochemical polishing process.Then, carry out second time annealing process to the metal level of remainder, as shown in Fig. 5 (d), Fig. 5 (d) is the generalized section after second time annealing process.Adopt twice annealing technique in the present embodiment, its benefit is: after electrochemical plating processes, and the time of metal level being carried out to first time annealing process is shorter, and temperature is lower, thus the metal level internal stress increase that annealing process is caused reduces as far as possible; After unstressed electrochemical polish, metal level is thinning, metal level internal stresses release, and then to metal level carry out second time annealing process time can be shorter, temperature can be lower, after annealing process, the increase of metal level internal stress is less, therefore, the metal bump above through hole is less, and, at twice to metal level annealing, the angularity of dielectric layer 510 can be reduced.Finally, then with the metal bump above the metal level of the mode planarization remainder of unstressed electrochemical polish and through hole, only retain the metal 514 in through hole, as shown in Figure 5 (e) shows, Fig. 5 (e) is the generalized section after unstressed electrochemical polishing process.Compared to cmp, in unstressed electrochemical polishing process, owing to not having mechanical stress to produce, thus can ensure can not cause damage to dielectric layer 510.The method of the unstressed electrochemical polish described in the present embodiment is identical with the unstressed electrochemical polishing method described in the first embodiment, therefore does not repeat them here.
Coat of metal processing method of the present invention, by integrating unstressed electrochemical polish, cmp and annealing process, breaches the technical bottleneck of warpage because metal level internal stress causes and metal bump, improves the quality of integrated circuit (IC)-components.
In sum, the present invention is illustrated by above-mentioned execution mode and correlative type, and what oneself was concrete, full and accurate discloses correlation technique, and those skilled in the art can be implemented according to this.And the above embodiment be only used to illustrate the present invention, instead of be used for restriction of the present invention, interest field of the present invention, should be defined by claim of the present invention.
Claims (10)
1. a coat of metal processing method, is characterized in that, comprises the following steps:
There is provided substrate, described substrate is formed with through hole;
Metal is filled and at the forming metal layer on surface of substrate in the through hole of substrate;
Metal level is polished to the surface close to substrate in the mode of unstressed electrochemical polish;
Carry out annealing process to the metal level of substrate surface, the metal level above through hole forms metal bump;
Remove the metal bump above the metal level of substrate surface and through hole, only retain the metal in through hole.
2. coat of metal processing method according to claim 1, it is characterized in that, the metal bump above the metal level of described removal substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of cmp.
3. coat of metal processing method according to claim 1, it is characterized in that, metal bump above the metal level of described removal substrate surface and through hole comprises: the metal level first removing substrate surface in the mode of cmp, and then removes the metal bump above through hole in the mode of unstressed electrochemical polish.
4. coat of metal processing method according to claim 1, it is characterized in that, described substrate is dielectric layer, through hole is formed in dielectric layer, through hole just extending towards the back side of dielectric layer from dielectric layer, the front of the diapire of through hole and sidewall and dielectric layer is formed with barrier layer, and metal level is formed on barrier layer.
5. a coat of metal processing method, is characterized in that, comprises the following steps:
There is provided substrate, described substrate is formed with through hole;
Metal is filled and at the forming metal layer on surface of substrate in the through hole of substrate;
Carry out annealing process to the metal level of substrate surface, the metal level above through hole forms metal bump;
Metal level is polished to the surface close to substrate in the mode of unstressed electrochemical polish;
Remove the metal bump above the metal level of substrate surface and through hole, only retain the metal in through hole.
6. coat of metal processing method according to claim 5, it is characterized in that, the metal bump above the metal level of described removal substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of cmp.
7. coat of metal processing method according to claim 5, is characterized in that, carries out second time annealing process before the metal bump above the metal level of described removal substrate surface and through hole to the metal level of substrate surface.
8. coat of metal processing method according to claim 7, it is characterized in that, the metal bump above the metal level of described removal substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of cmp.
9. coat of metal processing method according to claim 7, it is characterized in that, the metal bump above the metal level of described removal substrate surface and through hole comprises: remove the metal bump above the metal level of substrate surface and through hole in the mode of unstressed electrochemical polish.
10. coat of metal processing method according to claim 5, it is characterized in that, described substrate is dielectric layer, through hole is formed in dielectric layer, through hole just extending towards the back side of dielectric layer from dielectric layer, the front of the diapire of through hole and sidewall and dielectric layer is formed with barrier layer, and metal level is formed on barrier layer.
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| CN106558503A (en) * | 2015-09-24 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method |
| CN107210209A (en) * | 2015-02-15 | 2017-09-26 | 盛美半导体设备（上海）有限公司 | Optimize the method for metal planarization technique |
| CN107731838A (en) * | 2017-11-09 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of nand memory and preparation method thereof |
| CN112420601A (en) * | 2020-10-21 | 2021-02-26 | 中国科学院微电子研究所 | Manufacturing method of copper interconnection line and semiconductor device |
| CN112563194A (en) * | 2020-12-04 | 2021-03-26 | 武汉新芯集成电路制造有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112652520A (en) * | 2020-12-21 | 2021-04-13 | 上海华力微电子有限公司 | Method for improving LCOS process defect |
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