CN104347481B - Coat of metal processing method - Google Patents
Coat of metal processing method Download PDFInfo
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- CN104347481B CN104347481B CN201310330145.3A CN201310330145A CN104347481B CN 104347481 B CN104347481 B CN 104347481B CN 201310330145 A CN201310330145 A CN 201310330145A CN 104347481 B CN104347481 B CN 104347481B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 279
- 239000002184 metal Substances 0.000 title claims abstract description 279
- 238000003672 processing method Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims abstract description 82
- 238000000137 annealing Methods 0.000 claims abstract description 42
- 239000000126 substance Substances 0.000 claims abstract description 21
- 238000000227 grinding Methods 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims description 48
- 239000010410 layer Substances 0.000 description 212
- 238000007747 plating Methods 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 15
- 238000005240 physical vapour deposition Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- 238000005498 polishing Methods 0.000 description 9
- 230000005518 electrochemistry Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000007517 polishing process Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 230000005611 electricity Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Present invention discloses a kind of coat of metal processing methods, comprising the following steps: provides substrate, substrate is formed with through-hole；Metal and the forming metal layer on surface in substrate are filled into the through-hole of substrate；Metal layer is polished to the surface close to substrate in a manner of unstressed electrochemical polish；Annealing process is carried out to the metal layer of substrate surface, the metal layer above through-hole forms metal bump；The metal layer for removing substrate surface and the metal bump above through-hole only retain the metal in through-hole.The metal bump above the metal layer and through-hole of substrate surface is usually removed in a manner of chemical mechanical grinding.Coat of metal processing method of the present invention is by integrating unstressed electrochemical polish, chemical mechanical grinding and annealing process, and the technical bottleneck of the warpage of substrate and through-hole upper metal protrusion, improves the quality of integrated circuit device caused by breaching because of metal layer internal stress.
Description
Technical field
The present invention relates to manufacturing method for integrated curcuit more particularly to a kind of coat of metal processing methods.
Background technique
In recent years, through silicon via (TSV) technology has become the hot spot of microelectronic industry concern, and TSV technology is by chip
Between chip, vertical conducting is made between wafer and wafer, the state-of-the-art technology interconnected to each other is realized, with previous IC package
It is bonded the density maximum different with the superimposing technique using salient point, TSV can be such that chip stacks in three-dimensional, outer dimension is most
It is small, and substantially improve the performance of chip speed and low-power consumption.The key technology of TSV be Z axis interconnection and electric isolution technology, wherein
It include: the filling (plating) of the deposit of the formation of through-hole, stacking form, bonding pattern, insulating layer, barrier layer and seed layer, copper
With removal, redistribution lead (RDL) plating, wafer be thinned, measurement and detection etc..
Since the through-hole in TSV technology has biggish depth-to-width ratio, generally from 5:1 to 10:1 or even 20:1, big is deep wide
Than will cause in the technique of plating filling copper, through-hole can not be filled up.In order to fill up through-hole, gap is not generated in through-hole, is led to
It often can excessively be electroplated, thus cause substrate (wafer or chip) surface metal layers of copper blocked up, generally 3 to 5 microns.And metallic copper
Stress in layer increases with the increase of metal copper layer thickness, and the stress in metal copper layer, which crosses conference, makes substrate form warpage.
The conventional method for removing substrate surface metal copper layer is chemical mechanical grinding (CMP), in combination with annealing process.Though annealing process
Lower film resiativity and preferable electromigration resisting property can be so obtained, metal grain defect is eliminated, but after annealing process
Metal copper layer internal stress increases, and substrate warpage is even more serious, especially will lead to the metal copper layer above through-hole and forms protrusion.To change
When the mode of mechanical lapping removes the metal copper layer of substrate surface, the stronger lower pressure that chemical mechanical grinding generates can make to stick up
Bent substrate breakage, and if the metal bump above through-hole is larger, chemical mechanical grinding cannot be removed effectively above through-hole
Metal bump.
Summary of the invention
The object of the present invention is to provide a kind of coat of metal processing method, this method can not only be broken through because answering in metal layer
Power causes the warpage of substrate and the technical bottleneck of through-hole upper metal protrusion, and can be improved the quality of integrated circuit device.
To achieve the above object, coat of metal processing method proposed by the present invention, comprising the following steps: substrate, lining are provided
Bottom is formed with through-hole；Metal and the forming metal layer on surface in substrate are filled into the through-hole of substrate；With the throwing of unstressed electrochemistry
Metal layer is polished to the surface close to substrate by the mode of light；Annealing process, through-hole top are carried out to the metal layer of substrate surface
Metal layer formed metal bump；The metal layer for removing substrate surface and the metal bump above through-hole only retain in through-hole
Metal.
In one embodiment, removing the metal bump above the metal layer and through-hole of substrate surface includes: with chemical machine
The mode of tool grinding removes the metal bump above the metal layer and through-hole of substrate surface.
In one embodiment, removing the metal bump above the metal layer and through-hole of substrate surface includes: first with chemistry
The mode of mechanical lapping removes the metal layer of substrate surface, is then removed in a manner of unstressed electrochemical polish again above through-hole
Metal bump.
In one embodiment, substrate is dielectric layer, and through-hole is formed in dielectric layer, and through-hole is from dielectric layer just towards Jie
The back side of matter layer extends, and the bottom wall and side wall of through-hole and the front of dielectric layer are formed with barrier layer, and metal layer is formed in blocking
On layer.
To achieve the above object, another coat of metal processing method proposed by the present invention, comprising the following steps: lining is provided
Bottom, substrate are formed with through-hole；Metal and the forming metal layer on surface in substrate are filled into the through-hole of substrate；To substrate surface
Metal layer carries out annealing process, and the metal layer above through-hole forms metal bump；It will be golden in a manner of unstressed electrochemical polish
Belong to layer and is polished to the surface close to substrate；The metal layer for removing substrate surface and the metal bump above through-hole, only retain through-hole
Interior metal.
In one embodiment, removing the metal bump above the metal layer and through-hole of substrate surface includes: with chemical machine
The mode of tool grinding removes the metal bump above the metal layer and through-hole of substrate surface.
In one embodiment, the metal bump above the metal layer and through-hole of substrate surface is removed before to substrate surface
Metal layer carry out second of annealing process.The metal layer and the metal bump above through-hole for removing substrate surface include: to change
The mode for learning mechanical lapping removes the metal bump above the metal layer and through-hole of substrate surface.
In one embodiment, the metal bump above the metal layer and through-hole of substrate surface is removed before to substrate surface
Metal layer carry out second of annealing process.The metal layer and the metal bump above through-hole for removing substrate surface include: with nothing
The mode of stress electrochemical polish removes the metal bump above the metal layer and through-hole of substrate surface.
In one embodiment, substrate is dielectric layer, and through-hole is formed in dielectric layer, and through-hole is from dielectric layer just towards Jie
The back side of matter layer extends, and the bottom wall and side wall of through-hole and the front of dielectric layer are formed with barrier layer, and metal layer is formed in blocking
On layer.
In conclusion coat of metal processing method of the present invention is by integrating unstressed electrochemical polish, chemical mechanical grinding
And annealing process, the technical bottleneck of the warpage of substrate and through-hole upper metal protrusion, mentions caused by breaching because of metal layer internal stress
The high quality of integrated circuit device.
Detailed description of the invention
Fig. 1 (a) to Fig. 1 (d) discloses the process signal of coat of metal processing method according to a first embodiment of the present invention
Figure.
Fig. 2 (a) to Fig. 2 (e) discloses the process signal of coat of metal processing method according to a second embodiment of the present invention
Figure.
Fig. 3 (a) to Fig. 3 (d) discloses the process signal of coat of metal processing method according to a third embodiment of the present invention
Figure.
Fig. 4 (a) to Fig. 4 (e) discloses the process signal of coat of metal processing method according to a fourth embodiment of the present invention
Figure.
Fig. 5 (a) to Fig. 5 (e) discloses the process signal of coat of metal processing method according to a fifth embodiment of the present invention
Figure.
Specific embodiment
By the technology contents that the present invention will be described in detail, reached purpose and efficacy, below in conjunction with embodiment and cooperates figure
Formula is described in detail.
(a) discloses the process of coat of metal processing method according to a first embodiment of the present invention to Fig. 1 (d) refering to fig. 1
Schematic diagram.As shown in Fig. 1 (a), the through-hole of TSV is formed in substrate, and in the present invention, substrate is dielectric layer 110, and through-hole is from Jie
The back side just towards dielectric layer 110 of matter layer 110 extends.Metal in order to prevent, it is usually preferred to which metallic copper expands to dielectric layer 110
It dissipates, is formed with barrier layer 112 in the bottom wall and side wall of through-hole and the front of dielectric layer 110, the material on barrier layer 112 can be
Tantalum, tantalum nitride, titanium, titanium nitride or their combination, barrier layer 112 is other than it can prevent metal from spreading to dielectric layer 110, resistance
Barrier 112 can also be the adhesive layer between metal and dielectric layer 110.Then, on barrier layer in a manner of physical vapour deposition (PVD)
Metal seed layer is formed on 112.Then, metal plating is carried out in such a way that (ECP) is electroplated in electrochemistry, metal 114 fills up through-hole
And formed on the surface on barrier layer 112 with certain thickness metal layer, Fig. 1 (a) is that the section after electrochemical plating processes shows
It is intended to.
Next, needing to carry out planarization process to the metal layer on barrier layer 112, to remove metal layer, only retain logical
Metal 114 in hole.Firstly, metal layer is polished to close to barrier layer 112 in a manner of unstressed electrochemical polish.The application
Disclosed electrochemical polish in the U.S. Patent Application No. US10/590,460 that the applicant of people proposed on 2 23rd, 2005
Method and device is suitable for the present invention, therefore only briefly introduces herein to unstressed electrochemical polishing method.In an embodiment
In, unstressed electrochemical polishing method may comprise steps of: firstly, being located at nozzle at the center of substrate；Then,
Rotation of substrate, when substrate rotation, metal layer of the nozzle on substrate supplies electrolyte, to start electrochemical polish；Then,
Mobile substrate, from metal layer of the center of substrate on edge electrochemical polish substrate.Using the side of unstressed electrochemical polish
It is continuous metal layer to be thinned to discharge metal layer internal stress that metal layer is polished to the purpose close to barrier layer 112 by formula.Electricity
After chemical plating process, although metal layer internal stress causes 110 warpage of dielectric layer, due to not when unstressed electrochemical polish
Mechanical force can be generated, therefore unstressed electrochemical polish will not damage dielectric layer 110, as shown in Fig. 1 (b), Fig. 1 (b) is that nothing is answered
Diagrammatic cross-section after power electrochemical polishing process.
Then, annealing process is carried out to metal layer, since metal layer is thinned, after annealing process, metal layer internal stress
It is increased smaller, thus the metal bump formed above through-hole is smaller, as shown in Fig. 1 (c), Fig. 1 (c) is after annealing process
Diagrammatic cross-section.Finally, all removing the metal 114 other than through-hole in a manner of CMP, only retain the metal 114 in through-hole,
As shown in Figure 1 (d) shows, Fig. 1 (d) is the diagrammatic cross-section after CMP process.
Refering to Fig. 2 (a) to Fig. 2 (e), the process of coat of metal processing method according to a second embodiment of the present invention is disclosed
Schematic diagram.As shown in Figure 2 (a), the through-hole of TSV is formed in dielectric layer 210, and through-hole is from dielectric layer 210 just towards dielectric layer
210 back side extends.Metal in order to prevent, it is usually preferred to which metallic copper is spread to dielectric layer 210, in the bottom wall and side wall of through-hole
And the front of dielectric layer 210 is formed with barrier layer 212, the material on barrier layer 212 can for tantalum, tantalum nitride, titanium, titanium nitride or
Their combination, barrier layer 212 in addition to can prevent metal to dielectric layer 210 spread other than, barrier layer 212 can also be metal with
Adhesive layer between dielectric layer 210.Then, metal seed layer is formed on barrier layer 212 in a manner of physical vapour deposition (PVD).It connects
, metal plating is carried out in such a way that (ECP) is electroplated in electrochemistry, metal 214 fills up through-hole and formed on the surface on barrier layer 212
With certain thickness metal layer, Fig. 2 (a) is the diagrammatic cross-section after electrochemical plating processes.
Next, needing to carry out planarization process to the metal layer on barrier layer 212, to remove metal layer, only retain logical
Metal 214 in hole.Firstly, metal layer is polished to close to barrier layer 212 in a manner of unstressed electrochemical polish, it is therefore an objective to
Continuous metal layer is thinned to discharge metal layer internal stress, as shown in Fig. 2 (b), Fig. 2 (b) is unstressed electrochemical polish work
Diagrammatic cross-section after skill.Unstressed electricity described in the method and first embodiment of unstressed electrochemical polish described here
Chemically polishing method is identical, therefore details are not described herein.Then, annealing process is carried out to metal layer, since metal layer is thinned,
After annealing process, metal layer internal stress is increased smaller, thus the metal bump formed above through-hole is smaller, such as Fig. 2 (c) institute
Show, Fig. 2 (c) is the diagrammatic cross-section after annealing process.Then, remaining metal layer is planarized in a manner of CMP, due to through-hole
Top is formed with metal bump, chemical mechanical grinding possibly can not metal bump above completely flatization through-hole, and to lead to
Metal bump above hole becomes isolated metal pillar, if continuing abrasive metal pillar, chemical machinery by the way of CMP
The mechanical shear stress that grinding generates will cause the damage of through-hole side wall dielectric layer 210, and then lose manufactured integrated circuit device
Effect, as shown in Figure 2 (d) shows, Fig. 2 (d) are the diagrammatic cross-section after CMP process.In order to overcome defect existing for chemical mechanical grinding,
Finally, the metal bump above through-hole is removed in a manner of unstressed electrochemical polish, only retain the metal 214 in through-hole,
As shown in Fig. 2 (e), Fig. 2 (e) is the diagrammatic cross-section after unstressed electrochemical polishing process.
Refering to Fig. 3 (a) to Fig. 3 (d), the process of coat of metal processing method according to a third embodiment of the present invention is disclosed
Schematic diagram.As shown in Fig. 3 (a), the through-hole of TSV is formed in dielectric layer 310, and through-hole is from dielectric layer 310 just towards dielectric layer
310 back side extends.Metal in order to prevent, it is usually preferred to which metallic copper is spread to dielectric layer 310, in the bottom wall and side wall of through-hole
And the front of dielectric layer 310 is formed with barrier layer 312, the material on barrier layer 312 can for tantalum, tantalum nitride, titanium, titanium nitride or
Their combination, barrier layer 312 in addition to can prevent metal to dielectric layer 310 spread other than, barrier layer 312 can also be metal with
Adhesive layer between dielectric layer 310.Then, metal seed layer is formed on barrier layer 312 in a manner of physical vapour deposition (PVD).It connects
, metal plating is carried out in such a way that (ECP) is electroplated in electrochemistry, metal 314 fills up through-hole and formed on the surface on barrier layer 312
With certain thickness metal layer, Fig. 3 (a) is the diagrammatic cross-section after electrochemical plating processes.
Next, needing to carry out planarization process to the metal layer on barrier layer 312, to remove metal layer, only retain logical
Metal 314 in hole.Firstly, carrying out annealing process to metal layer, it is therefore an objective to obtain lower film resiativity and preferably resist
Electromigration eliminates metal grain defect, but metal layer internal stress increases after annealing process, so as to cause the gold above through-hole
Belong to layer and form protrusion, as shown in Figure 3 (b), Fig. 3 (b) is the diagrammatic cross-section after annealing process.Then, with unstressed electrochemistry
Metal layer is polished to close to barrier layer 312 by the mode of polishing, it is therefore an objective to which continuous metal layer is thinned to discharge in metal layer
Stress, while a degree of removal is carried out to the metal bump above through-hole, as shown in Figure 3 (c), Fig. 3 (c) is unstressed electricity
Diagrammatic cross-section after surface with chemical polishing technology.Described in the method and first embodiment of unstressed electrochemical polish described here
Unstressed electrochemical polishing method it is identical, therefore details are not described herein.Finally, planarizing remaining metal layer in a manner of CMP
With the metal bump above through-hole, only retain the metal 314 in through-hole, as shown in Fig. 3 (d), Fig. 3 (d) is cuing open after CMP process
Face schematic diagram.Since metal layer internal stress has largely discharged, above the remaining metal layer of chemical mechanical grinding and through-hole
Dielectric layer 310 will not be caused to damage when metal bump.
Refering to Fig. 4 (a) to Fig. 4 (e), the process of coat of metal processing method according to a fourth embodiment of the present invention is disclosed
Schematic diagram.As shown in Figure 4 (a), the through-hole of TSV is formed in dielectric layer 410, and through-hole is from dielectric layer 410 just towards dielectric layer
410 back side extends.Metal in order to prevent, it is usually preferred to which metallic copper is spread to dielectric layer 410, in the bottom wall and side wall of through-hole
And the front of dielectric layer 410 is formed with barrier layer 412, the material on barrier layer 412 can for tantalum, tantalum nitride, titanium, titanium nitride or
Their combination, barrier layer 412 in addition to can prevent metal to dielectric layer 410 spread other than, barrier layer 412 can also be metal with
Adhesive layer between dielectric layer 410.Then, metal seed layer is formed on barrier layer 412 in a manner of physical vapour deposition (PVD).It connects
, metal plating is carried out in such a way that (ECP) is electroplated in electrochemistry, metal 414 fills up through-hole and formed on the surface on barrier layer 412
With certain thickness metal layer, Fig. 4 (a) is the diagrammatic cross-section after electrochemical plating processes.
Next, needing to carry out planarization process to the metal layer on barrier layer 412, to remove metal layer, only retain logical
Metal 414 in hole.Firstly, to metal layer carry out first time annealing process, it is therefore an objective to obtain lower film resiativity and compared with
Good electromigration resisting property eliminates metal grain defect, but metal layer internal stress increases after annealing process, so as to cause on through-hole
The metal layer of side forms protrusion, and as shown in Figure 4 (b), Fig. 4 (b) is the diagrammatic cross-section after first time annealing process.Then, with
Metal layer is polished to close to barrier layer 412 by the mode of unstressed electrochemical polish, it is therefore an objective to by continuous metal layer be thinned with
Metal layer internal stress is discharged, while a degree of removal, as shown in Figure 4 (c), Fig. 4 are carried out to the metal bump above through-hole
It (c) is the diagrammatic cross-section after unstressed electrochemical polishing process.The method of unstressed electrochemical polish described here and the
One unstressed electrochemical polishing method as described in the examples is identical, therefore details are not described herein.Then, to remaining metal layer into
Second of annealing process of row, as shown in Fig. 4 (d), Fig. 4 (d) is the diagrammatic cross-section after second of annealing process.In the present embodiment
It using twice annealing technique, is advantageous in that: after electrochemical plating processes, the time of first time annealing process is carried out to metal layer
Shorter, temperature is lower, so that metal layer internal stress increase caused by annealing process be made to reduce as far as possible；Unstressed electrochemical polish
Afterwards, metal layer is thinned, metal layer internal stresses release, and the time for then carrying out second of annealing process to metal layer again can be more
Short, temperature can be lower, and the increase of metal layer internal stress is smaller after annealing process, and therefore, the metal bump above through-hole is smaller, and
And anneal in two times to metal layer, the angularity of dielectric layer 410 can be reduced.Finally, being planarized in a manner of CMP remaining
Metal bump above metal layer and through-hole only retains the metal 414 in through-hole, and as shown in Fig. 4 (e), Fig. 4 (e) is CMP process
Diagrammatic cross-section afterwards.
Refering to Fig. 5 (a) to Fig. 5 (e), the process of coat of metal processing method according to a fifth embodiment of the present invention is disclosed
Schematic diagram.As shown in Fig. 5 (a), the through-hole of TSV is formed in dielectric layer 510, and through-hole is from dielectric layer 510 just towards dielectric layer
510 back side extends.Metal in order to prevent, it is usually preferred to which metallic copper is spread to dielectric layer 510, in the bottom wall and side wall of through-hole
And the front of dielectric layer 510 is formed with barrier layer 512, the material on barrier layer 512 can for tantalum, tantalum nitride, titanium, titanium nitride or
Their combination, barrier layer 512 in addition to can prevent metal to dielectric layer 510 spread other than, barrier layer 512 can also be metal with
Adhesive layer between dielectric layer 510.Then, metal seed layer is formed on barrier layer 512 in a manner of physical vapour deposition (PVD).It connects
, metal plating is carried out in such a way that (ECP) is electroplated in electrochemistry, metal 514 fills up through-hole and formed on the surface on barrier layer 512
With certain thickness metal layer, Fig. 5 (a) is the diagrammatic cross-section after electrochemical plating processes.
Next, needing to carry out planarization process to the metal layer on barrier layer 512, to remove metal layer, only retain logical
Metal 514 in hole.Firstly, to metal layer carry out first time annealing process, it is therefore an objective to obtain lower film resiativity and compared with
Good electromigration resisting property eliminates metal grain defect, but metal layer internal stress increases after annealing process, so as to cause on through-hole
The metal layer of side forms protrusion, and as shown in Fig. 5 (b), Fig. 5 (b) is the diagrammatic cross-section after first time annealing process.Then, with
Metal layer is polished to close to barrier layer 512 by the mode of unstressed electrochemical polish, it is therefore an objective to by continuous metal layer be thinned with
Metal layer internal stress is discharged, while a degree of removal, as shown in Fig. 5 (c), Fig. 5 are carried out to the metal bump above through-hole
It (c) is the diagrammatic cross-section after unstressed electrochemical polishing process.Then, second of lehr attendant is carried out to remaining metal layer
Skill, as shown in Fig. 5 (d), Fig. 5 (d) is the diagrammatic cross-section after second of annealing process.Twice annealing work is used in the present embodiment
Skill is advantageous in that: after electrochemical plating processes, the time for carrying out first time annealing process to metal layer is shorter, and temperature is lower,
To make metal layer internal stress increase caused by annealing process reduce as far as possible；After unstressed electrochemical polish, metal layer is thinned,
Metal layer internal stresses release, the time for then carrying out second of annealing process to metal layer again can be shorter, and temperature can be lower,
The increase of metal layer internal stress is smaller after annealing process, and therefore, the metal bump above through-hole is smaller, moreover, in two times to metal
Layer annealing, can reduce the angularity of dielectric layer 510.Finally, being planarized in a manner of unstressed electrochemical polish again remaining
Metal bump above metal layer and through-hole only retains the metal 514 in through-hole, and as shown in Figure 5 (e) shows, Fig. 5 (e) is unstressed
Diagrammatic cross-section after electrochemical polishing process.Compared to chemical mechanical grinding, in unstressed electrochemical polishing process, due to not having
There is mechanical stress generation, thus can guarantee that dielectric layer 510 will not be caused to damage.Unstressed electrification described in the present embodiment
The method of optical polishing is identical as unstressed electrochemical polishing method described in first embodiment, therefore details are not described herein.
Coat of metal processing method of the present invention is by integrating unstressed electrochemical polish, chemical mechanical grinding and lehr attendant
Skill, the technical bottleneck of warpage and metal bump caused by breaching because of metal layer internal stress, improves the matter of integrated circuit device
Amount.
In conclusion the present invention is illustrated by above embodiment and correlative type, oneself is specific, full and accurate to disclose correlation
Technology implements those skilled in the art accordingly.And embodiment described above is used only to illustrate the present invention, rather than
Interest field of the invention for limiting, of the invention should be defined by claim of the invention.
Claims (9)
1. a kind of coat of metal processing method, which comprises the following steps:
Substrate is provided, the substrate is formed with through-hole；
Metal and the forming metal layer on surface in substrate are filled into the through-hole of substrate；
Metal layer is polished to the surface close to substrate in a manner of unstressed electrochemical polish；
Annealing process is carried out to the metal layer of substrate surface, the metal layer above through-hole forms metal bump；
The metal layer for removing substrate surface and the metal bump above through-hole only retain the metal in through-hole；
Wherein, the metal layer of the removal substrate surface and the metal bump above through-hole include: first with chemical mechanical grinding
Mode removes the metal layer of substrate surface, and the metal then removed above through-hole in a manner of unstressed electrochemical polish again is convex
It rises.
2. coat of metal processing method according to claim 1, which is characterized in that the metal layer of the removal substrate surface
And the metal bump above through-hole includes: to be removed above the metal layer and through-hole of substrate surface in a manner of chemical mechanical grinding
Metal bump.
3. coat of metal processing method according to claim 1, which is characterized in that the substrate is dielectric layer, through-hole shape
At in dielectric layer, through-hole extends from the back side just towards dielectric layer of dielectric layer, the bottom wall and side wall and dielectric layer of through-hole
Front be formed with barrier layer, metal layer is formed on barrier layer.
4. a kind of coat of metal processing method, which comprises the following steps:
Substrate is provided, the substrate is formed with through-hole；
Metal and the forming metal layer on surface in substrate are filled into the through-hole of substrate；
Annealing process is carried out to the metal layer of substrate surface, the metal layer above through-hole forms metal bump；
Metal layer is polished to the surface close to substrate in a manner of unstressed electrochemical polish；
The metal layer for removing substrate surface and the metal bump above through-hole only retain the metal in through-hole；
Wherein, the metal layer of the removal substrate surface and the metal bump above through-hole include: first with chemical mechanical grinding
Mode removes the metal layer of substrate surface, and the metal then removed above through-hole in a manner of unstressed electrochemical polish again is convex
It rises.
5. coat of metal processing method according to claim 4, which is characterized in that the metal layer of the removal substrate surface
And the metal bump above through-hole includes: to be removed above the metal layer and through-hole of substrate surface in a manner of chemical mechanical grinding
Metal bump.
6. coat of metal processing method according to claim 4, which is characterized in that the metal layer of the removal substrate surface
And second of annealing process is carried out to the metal layer of substrate surface before the metal bump above through-hole.
7. coat of metal processing method according to claim 6, which is characterized in that the metal layer of the removal substrate surface
And the metal bump above through-hole includes: the metal bump removed above through-hole in a manner of chemical mechanical grinding.
8. coat of metal processing method according to claim 6, which is characterized in that the metal layer of the removal substrate surface
And the metal bump above through-hole includes: the metal layer that substrate surface is removed in a manner of unstressed electrochemical polish.
9. coat of metal processing method according to claim 4, which is characterized in that the substrate is dielectric layer, through-hole shape
At in dielectric layer, through-hole extends from the back side just towards dielectric layer of dielectric layer, the bottom wall and side wall and dielectric layer of through-hole
Front be formed with barrier layer, metal layer is formed on barrier layer.
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| CN105990097B (en) * | 2015-02-15 | 2020-03-27 | 盛美半导体设备(上海)股份有限公司 | Polishing method of high-K dielectric silicon wafer |
| CN106558503B (en) * | 2015-09-24 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method |
| CN107731838A (en) * | 2017-11-09 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of nand memory and preparation method thereof |
| CN112420601A (en) * | 2020-10-21 | 2021-02-26 | 中国科学院微电子研究所 | Manufacturing method of copper interconnection line and semiconductor device |
| CN112563194B (en) * | 2020-12-04 | 2021-09-10 | 武汉新芯集成电路制造有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112652520A (en) * | 2020-12-21 | 2021-04-13 | 上海华力微电子有限公司 | Method for improving LCOS process defect |
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| CN102110585A (en) * | 2009-12-24 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal layer |
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| WO2010020092A1 (en) * | 2008-08-20 | 2010-02-25 | Acm Research (Shanghai) Inc. | Barrier layer removal method and apparatus |
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| CN102110585A (en) * | 2009-12-24 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal layer |
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