CN107346731B - Method for reducing thickness of copper film - Google Patents
Method for reducing thickness of copper film Download PDFInfo
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- CN107346731B CN107346731B CN201610292045.XA CN201610292045A CN107346731B CN 107346731 B CN107346731 B CN 107346731B CN 201610292045 A CN201610292045 A CN 201610292045A CN 107346731 B CN107346731 B CN 107346731B
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- 238000000034 method Methods 0.000 title claims abstract description 66
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 40
- 239000010949 copper Substances 0.000 title claims abstract description 40
- 230000008569 process Effects 0.000 claims abstract description 44
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000007747 plating Methods 0.000 claims abstract description 16
- 239000000126 substance Substances 0.000 claims abstract description 14
- 238000007517 polishing process Methods 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical group [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 4
- 239000005751 Copper oxide Substances 0.000 claims description 4
- 229910000431 copper oxide Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 11
- 238000004140 cleaning Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 239000012459 cleaning agent Substances 0.000 description 2
- 238000006056 electrooxidation reaction Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
- H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention discloses a method for reducing the thickness of a copper film, which comprises the following steps: plating a copper layer on the surface of the wafer by adopting an electrochemical copper plating process; the thickness of the copper film on the surface of the wafer is reduced by adopting an electrochemical polishing process; and removing the oxide layer on the surface of the wafer by using citric acid. The method utilizes the citric acid to clean the surface of the wafer to remove the oxide layer, and solves the problem that the oxide layer influences the removal rate and uniformity of the chemical mechanical planarization process.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing the thickness of a copper film.
Background
The three-dimensional stacked integrated circuit packaging technology (3D IC) based on the through-silicon via (TSV) technology is the latest packaging technology at present, and has the advantages of minimum size and quality, effective reduction of parasitic effect, improvement of chip speed, reduction of power consumption, and the like. The TSV technology is a latest technology for realizing interconnection between chips by making vertical conduction between the chips, and as an alternative technology of wire bonding, a through hole structure penetrating through a silicon wafer is formed to greatly shorten the interconnection distance, thereby eliminating the limitation on the number of chip stacks, and enabling the three-dimensional stacks of chips to be applied in a wider field.
The existing silicon through hole uses metal copper as a metal layer, and the front process of the copper metal layer mainly comprises the following steps: a copper seed layer vacuum Plating (PVD) process, a copper film plating process, an annealing process, and a Chemical Mechanical Polishing (CMP) planarization process. Because of the large aspect ratio of vias in TSV technology, the ratio of the depth to the width is generally from 5: 1 to 10: 1, even 20: 1. the large aspect ratio results in the copper in the hole not being filled during the copper plating process. The optimized copper electroplating process can well fill the deep hole, but can cause the copper layer on the surface of the wafer to be too thick, and the thickness is usually 3 to 5 microns. The metal internal stress increases along with the thickness, the metal surface stress of the TSV silicon chip is larger than that of a traditional wafer metal layer, and the silicon chip warps. In the annealing process, because the metal layer is thicker and the metal grains grow, the metal above the deep hole can form a bulge. These two points can cause the wafer to be broken when using the conventional chemical mechanical planarization process, and the metal bump above the deep hole cannot be planarized effectively, so it is very necessary to reduce the thickness of the copper film.
The existing method for reducing the thickness of the copper film is realized by the following steps: after the copper plating process, the thickness of the copper film on the surface of the wafer is reduced by adopting electrochemical polishing, then an annealing process is carried out, and finally a chemical mechanical planarization process is adopted. In the prior art, after electrochemical polishing, a copper oxide layer caused by electrochemical oxidation is formed on the surface of metal copper, and the copper oxide layer affects the removal rate and uniformity of the subsequent chemical mechanical planarization process and has a lower removal rate than the natural copper oxide layer.
Disclosure of Invention
The invention provides a method for reducing the thickness of a copper film, aiming at the problem that an oxide layer generated in the existing process for reducing the thickness of the copper film influences the removal rate and uniformity of a chemical mechanical planarization process.
The technical scheme adopted by the invention is realized as follows:
the invention provides a method for reducing the thickness of a copper film, which comprises the following steps:
(1) plating a copper layer on the surface of the wafer by adopting an electrochemical copper plating process;
(2) the thickness of the copper film on the surface of the wafer is reduced by adopting an electrochemical polishing process;
(3) and removing the oxide layer on the surface of the wafer by using citric acid.
Further, the citric acid is diluted citric acid with the concentration of 1% -2%.
Preferably, the method further comprises:
(4) conveying the wafer to an annealing process chamber for annealing process;
(5) and removing residual impurities on the surface of the wafer by adopting a chemical mechanical planarization process.
Further, reducing gas is introduced into the annealing chamber.
Further, the reducing gas is a mixed gas of hydrogen and nitrogen.
Further, the surface of the wafer is cleaned after the electrochemical copper plating process and before the electrochemical polishing process.
Further, the surface of the wafer is cleaned before the annealing process after the electrochemical polishing process.
Further, after the chemical mechanical planarization process is performed, the surface of the wafer is cleaned.
According to the invention, the citric acid is used for cleaning the surface of the wafer to remove the oxide layer, so that the problem that the oxide layer influences the removal rate and uniformity of the chemical mechanical planarization process is solved; according to the invention, reducing gas is introduced into the annealing process cavity, and the oxide layer formed by electrochemical oxidation on the surface of the wafer is removed by using a reducing method, so that the subsequent planarization effect is better.
Drawings
FIG. 1 is a flow chart of one embodiment of the present invention;
fig. 2 is a flow chart of another embodiment of the present invention.
Detailed Description
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention when taken in conjunction with the accompanying drawings. The drawings are not intended to be to scale, emphasis instead being placed upon illustrating the principles of the invention.
Example 1
A method of reducing the thickness of a copper film, comprising the steps of:
(1) plating a copper layer on the surface of the wafer by adopting an electrochemical copper plating process;
(2) cleaning the surface of the wafer;
(3) the thickness of the copper film on the surface of the wafer is reduced by adopting an electrochemical polishing process;
(4) and cleaning the surface of the wafer, and adding 1% -2% diluted citric acid into the cleaning agent so as to remove an oxide layer on the surface of the wafer.
Preferably, the method may further include the following steps:
(5) conveying the wafer to an annealing process chamber for annealing process;
(6) removing residual impurities on the surface of the wafer by adopting a chemical mechanical planarization process;
(7) and cleaning the surface of the wafer.
Example 2
A method of reducing the thickness of a copper film, comprising the steps of:
(1) providing a wafer, and plating a copper layer on the surface of the wafer by adopting an electrochemical copper plating process;
(2) cleaning the surface of the wafer;
(3) the thickness of the copper film on the surface of the wafer is reduced by adopting an electrochemical polishing process;
(4) cleaning the surface of the wafer, and adding 1% -2% diluted citric acid into the cleaning agent;
(5) conveying the wafer to an annealing process chamber for annealing process;
(6) introducing a reducing gas into the annealing process cavity, wherein the reducing gas is a mixed gas of hydrogen and nitrogen;
(7) removing residual impurities on the surface of the wafer by adopting a chemical mechanical planarization process;
(8) and cleaning the surface of the wafer.
It will be apparent to those skilled in the art that various modifications and variations can be made to the above-described exemplary embodiments of the present invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (8)
1. A method for reducing the thickness of a copper film, comprising the steps of:
(1) plating a copper layer on the surface of the wafer by adopting an electrochemical copper plating process;
(2) the thickness of the copper film on the surface of the wafer is reduced by adopting an electrochemical polishing process;
(3) and removing an oxide layer on the surface of the wafer by using citric acid, wherein the oxide layer is a copper oxide layer.
2. The method of claim 1, wherein the citric acid is diluted citric acid at a concentration of 1% to 2%.
3. The method of claim 1, further comprising after step (3):
(4) conveying the wafer to an annealing process chamber for annealing process;
(5) and removing residual impurities on the surface of the wafer by adopting a chemical mechanical planarization process.
4. The method of claim 3, wherein after the annealing process is completed and before the chemical mechanical planarization process, the method further comprises: and introducing a reducing gas into the annealing chamber.
5. The method according to claim 4, wherein the reducing gas is a mixed gas of hydrogen and nitrogen.
6. The method of claim 1, wherein the wafer surface is cleaned after the electrochemical copper plating process and before the electrochemical polishing process.
7. A method as claimed in claim 3, characterized in that the wafer surface is cleaned before the annealing process after the electrochemical polishing process.
8. The method of claim 3, wherein the wafer surface is cleaned after the chemical mechanical planarization process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610292045.XA CN107346731B (en) | 2016-05-05 | 2016-05-05 | Method for reducing thickness of copper film |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610292045.XA CN107346731B (en) | 2016-05-05 | 2016-05-05 | Method for reducing thickness of copper film |
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| CN107346731A CN107346731A (en) | 2017-11-14 |
| CN107346731B true CN107346731B (en) | 2021-03-16 |
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| CN201610292045.XA Active CN107346731B (en) | 2016-05-05 | 2016-05-05 | Method for reducing thickness of copper film |
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| CN109999839B (en) * | 2019-05-06 | 2021-11-16 | 淮北师范大学 | Preparation method of inorganic non-noble metal Ni-doped Cu-based bifunctional electrocatalyst |
| CN113059405A (en) * | 2019-12-30 | 2021-07-02 | 盛美半导体设备(上海)股份有限公司 | Processing method and cleaning device for semiconductor structure |
| CN114156099A (en) * | 2021-12-06 | 2022-03-08 | 北京七星飞行电子有限公司 | Method for processing capacitor lead |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882595B (en) * | 2009-05-08 | 2014-07-09 | 盛美半导体设备（上海）有限公司 | Method and device for removing barrier layer |
| CN104637862A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Method for forming semiconductor structures |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7618529B2 (en) * | 2004-05-25 | 2009-11-17 | Rohm And Haas Electronic Materials Cmp Holdings, Inc | Polishing pad for electrochemical mechanical polishing |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882595B (en) * | 2009-05-08 | 2014-07-09 | 盛美半导体设备（上海）有限公司 | Method and device for removing barrier layer |
| CN104637862A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Method for forming semiconductor structures |
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Address after: 201203 building 4, No. 1690, Cailun Road, free trade zone, Pudong New Area, Shanghai Applicant after: Shengmei semiconductor equipment (Shanghai) Co., Ltd Address before: 201203 Shanghai Zhangjiang High Tech Park of Pudong New Area Cailun Road No. fourth 1690 Applicant before: ACM (SHANGHAI) Inc. |
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