CN103219282B - Through silicon via (TSV) exposure process - Google Patents
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- CN103219282B CN103219282B CN201310163510.6A CN201310163510A CN103219282B CN 103219282 B CN103219282 B CN 103219282B CN 201310163510 A CN201310163510 A CN 201310163510A CN 103219282 B CN103219282 B CN 103219282B
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Abstract
The invention discloses a through silicon via (TSV) exposure process. After the back surface of a wafer substrate is ground and thinned mechanically, a chemical mechanical polishing (CMP) process is performed twice. In the first CMP process, a polishing solution without selection ratio is adopted, so that the total thickness variation (TTV) of the surface of the substrate is controlled to be less than 1 mu m, and the problem of low exposure uniformity caused by over-large TTV is solved. In the second CMP process, a polishing solution with high selection ratio among the substrate, a TSV medium layer and a TSV barrier layer is adopted, so that the etching is stopped at the TSV barrier layer, an internal conductive copper column is protected from being corroded, the etched substrate appearance is of a transition structure for the deposition of a seed layer, and the stability of a TSV during subsequent electric connection is improved.
Description
Technical field
The present invention relates to that microelectronics technology is a kind of to be manufactured or process semiconductor or the method for solid state device or its parts, the TSV particularly relating to transmission current between a kind of resolution element utilizing metal 3D to be interconnected in microelectronic component appears technique.
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit constantly reduces, and interconnection density improves constantly.The requirement of user to high-performance low power consumption simultaneously improves constantly.In this case, by reducing the live width of interconnection line further to propose the restriction that high performance mode is subject to physical characteristics of materials and apparatus and process, the resistance capacitance (RC) of two-dimentional interconnection line postpones the bottleneck becoming the raising of restriction semiconductor core piece performance gradually.Silicon perforation (Through Silicon Via, being called for short TSV) technique is by forming metal upright post in wafer, and be equipped with metal salient point, can to realize between wafer (chip) or direct three-dimensional interconnection between chip and substrate, the limitation of conventional semiconductor chip two dimension wiring can be made up like this.This interconnection mode and traditional Stack Technology as have compared with bonding techniques the stacking density of three-dimensional large, encapsulate the advantages such as overall dimension is afterwards little, thus greatly improve the speed of chip and reduce power consumption.Therefore, TSV technology has been widely regarded as the forth generation encapsulation technology after bonding, carrier band weldering and flip-chip, will become the mainstream technology in high-density packages field gradually.
TSV is by chip and chip, make vertical conducting hole by modes such as etching, laser drill between wafer and wafer, in via, then realized the technology of interconnection by mode depositing electrically conductive materials such as plating.Due to TSV the degree of depth usually than the chip at place and the thickness of wafer little, realize interconnect object, a reduction process must be carried out to wafer rear, expose the conduction copper column of TSV.Existing TSV reveals in process for copper, is first thinned to by mechanical lapping bottom TSV by wafer, is then removed by the silicon of wafer rear by wet etching (or dry etching), expose the copper bottom TSV.In the process, existing machinery grinding machine, when grinding, controls at 2.5 microns to amounts of thickness variation (TTV) d1 of crystal column surface, as shown in Figure 1.This variable quantity in wet at next step (/ dry) method etching dew copper, can maintain due to the isotropic of etching.Cause like this as a result, after having etched, the height that the TSV of zones of different appears is also different, and the TSV in some place appears and highly likely reaches requirement, and the TSV in some place appears and highly then not yet may reach requirement.For 10 μm of height of appearing, in the thicker region of wafer, the TSV conductive pole likely exposed only has 7-8 μm, thus causes the TSV in these regions to go wrong in follow-up electrical connection.
Summary of the invention
In view of this, a kind of new TSV is the object of the present invention is to provide to appear technique, this technique not only can avoid TTV on TSV appear part impact, ensure that all TSV all have the part of appearing of the height that meets the demands, and after TSV appears, reduce to TSV appear part destruction, improve product quality.
A kind of TSV that object according to the present invention proposes appears technique, comprises step:
The Semiconductor substrate that one has a TSV structure is provided;
One mechanical milling tech is carried out to the back side of above-mentioned Semiconductor substrate;
First time CMP (Chemical Mechanical Polishing) process is carried out to the Semiconductor substrate back side, this first time CMP (Chemical Mechanical Polishing) process employing is no more than 1 μm of place without the polishing fluid of Selection radio by bottom Semiconductor substrate polished backside to distance TSV, and the TTV on polishing back substrate surface is less than 1 μm;
Carry out second time CMP (Chemical Mechanical Polishing) process to the Semiconductor substrate back side, this second time CMP (Chemical Mechanical Polishing) process adopts carries out the polishing fluid of Semiconductor substrate, TSV dielectric layer, TSV barrier layer high selectivity;
Wet method or dry etching are carried out to the Semiconductor substrate back side, makes TSV expose more than 10 μm.
Preferably, the polishing fluid adopted in described second time CMP (Chemical Mechanical Polishing) process, it is that Selection radio between 10:1 to 100:1, TSV dielectric layer and TSV barrier layer is more than 200:1 to the Selection radio between Semiconductor substrate and TSV dielectric layer.
Preferably, the polishing fluid hydrofluoric acid adopted in described second time CMP (Chemical Mechanical Polishing) process and nitric acid mixed system, hydrofluoric acid, TMAH system or potassium hydroxide.
Preferably, in described hydrofluoric acid and nitric acid mixed system, the scope of the percent by volume of hydrofluoric acid and nitric acid is between 1:5 to 1:25, and the percentage by weight of described TMAH system is 3w%-30w%.
Preferably, after described second time CMP (Chemical Mechanical Polishing) process, TSV appears height between 0.2 μm-0.5 μm.
Preferably, the material of described Semiconductor substrate is silicon, germanium, gallium nitride or GaAs.
Above-mentioned TSV appears technique, and compared with prior art, the technical advantage had is as follows:
First time, CMP adopted the polishing fluid without Selection radio, made the TTV of substrate surface control, below 1 μm, to reduce the problem of the lack of homogeneity caused appearing because TTV is excessive.
Second time CMP adopts the polishing fluid to high selectivity between substrate, TSV dielectric layer, TSV barrier layer three; etch-stop is made to stay on the barrier layer of TSV; thus the conduction copper column of protection the inside is not corroded; and etching substrate pattern out has for transition structure during seed layer deposition, thus stability when improving the follow-up electrical connection of TSV.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is in prior art, the substrate surface schematic diagram after mechanical lapping.
Fig. 2 is that TSV of the present invention appears the concise and to the point schematic flow sheet of technique.
Fig. 3 A to 3E is the structural representation that in Fig. 2, each step is corresponding.
Embodiment
As described in the background art, existing TSV appears technique, because mechanical lapping machine is when grinding, controls at 2.5 microns to amounts of thickness variation (TTV) d1 of crystal column surface, this variable quantity during wet at next step (/ dry) method etching appears, can maintain due to the isotropic of etching.Cause like this as a result, after having etched, the height that the TSV of zones of different appears is also different, and the TSV in some place appears and highly likely reaches requirement, and the TSV in some place appears and highly then not yet may reach requirement.For 10 μm of height of appearing, in the thicker region of wafer, the copper likely exposed only has 7-8 μm, thus causes the TSV in these regions to go wrong in follow-up electrical connection.
Therefore, for these problems, the present invention proposes a kind of new TSV to appear technique, this technique not only can avoid TTV on TSV appear part impact, ensure that all TSV all have the part of appearing of the height that meets the demands, and after TSV appears, reduce to TSV appear part destruction, improve product quality.Simultaneously, use technique of the present invention carry out TSV appear operation after, there is the transitional region of certain radian in the intersection that can reveal copper end and substrate at TSV, this transitional region can make follow-up on TSV deposition plating Seed Layer time, form continuous print seed layer deposition, avoid the connection defect problem of micro convex point on follow-up TSV.
In technical scheme of the present invention, main improvement is, after adopting mechanical system grinding thinning to the back side of wafer substrate, increase by 2 CMP (Chemical Mechanical Polishing) process (CMP), first time, CMP adopted the polishing fluid without Selection radio, substrate after grinding is thinned to further the distance of bottom distance TSV about 1 μm, by the polishing of this step, the difference in height of substrate surface TTV is made to be reduced to the degree of less than 1 μm, make the height of substrate back as far as possible close to bottom TSV simultaneously, can save time for follow-up etch step.Second time CMP then adopts the polishing fluid to high selectivity between substrate, TSV dielectric layer, TSV barrier layer three, when carrying out polishing to substrate, control the etch rate to dielectric layer and barrier layer, when making substrate be etched to 0.2 μm to 0.5 μm, the etching of TSV is stopped over the barrier layer, avoids the corrosion to copper conductive pole in TSV.Simultaneously, after this step polishing, following pattern can be formed: in the place near TSV sidewall at substrate surface, substrate is by lacking of etching downwards, and away from the place of TSV, substrate is etched many downwards, thus there is the height transition region of TSV to substrate at the intersection of TSV and substrate, when this transition region can make subsequent deposition Seed Layer, help Seed Layer continuous print deposition, thus avoid the tomography problem in original vertical stratification to occur.After 2 CMP, recycling substrate etching technique carries out wet method or dry etching to substrate, continues down to etch, thus expose the TSV copper layer of desired height along the substrate shape occurred after second time CMP.
Refer to Fig. 2, Fig. 2 is that TSV of the present invention appears the concise and to the point schematic flow sheet of technique.As shown in the figure, the key step of this technique comprises:
S11: the Semiconductor substrate that has a TSV structure is provided.
S12 a: mechanical milling tech is carried out to the back side of above-mentioned Semiconductor substrate.
S13: first time CMP (Chemical Mechanical Polishing) process is carried out to the substrate back after step S12, this, CMP (Chemical Mechanical Polishing) process adopted the polishing fluid without Selection radio to be polished to bottom distance TSV by substrate back to be no more than 1 μm of place first time, and the TTV on polishing back substrate surface is less than 1 μm.
S14: carry out second time CMP (Chemical Mechanical Polishing) process to the substrate back after step S13, this second time CMP (Chemical Mechanical Polishing) process adopts carries out the polishing fluid of substrate, TSV dielectric layer, TSV barrier layer high selectivity.
S15: carry out wet method or dry etching to the substrate back after step S14, makes TSV expose more than 10 μm.
Below, will be described in detail said method by embodiment.
Refer to Fig. 3 A-3E, the structural representation that upper each step above-mentioned of Fig. 3 A to 3E is corresponding.As shown in the figure:
First, the Semiconductor substrate that has TSV structure is prepared, as shown in Figure 3A.This Semiconductor substrate 11 is semiconductor chip in one embodiment, its material is such as the semi-conducting materials such as silicon, germanium, gallium nitride, GaAs, it comprises the some electronic devices and components being formed in its substrate face 12 and/or its inside, with preferred but nonessential semiconductor interlayer structure 40, such as dielectric layer, conductive layer, conductive pattern district etc. are the connection that above-mentioned electronic devices and components form complete circuit and design and wire structures.In practical application, this semiconductor chip can also be comprise the alternation of bed that multilayer is made up of above-mentioned medium and conductive layer, and the number of plies of alternation of bed comparatively typically can be about three layers to Floor 12.This Semiconductor substrate 11 can be also directly wafer at another kind of execution mode, and now its front 12 can for not comprising the naked crystalline substance of any semiconductor device.Multiple TSV30 is fabricated in this Semiconductor substrate 11.
The concrete structure of these TSV30 refers to Fig. 3 B.The conductive pole 31 comprising the dielectric layer 2 be positioned on TSV sidewall, barrier layer 4 and wrapped up by this dielectric layer 2, barrier layer 4.Dielectric layer 2 can be silica, silicon nitride, silicon oxynitride etc., the method making this dielectric layer can be substrate is oxidized, the mode such as nitrogenize directly obtains, and the plated film modes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD) also can be used to be made.This dielectric layer 2 is arranged between conductive pole 31 and Semiconductor substrate 11, mainly plays the effect of insulation, prevents the electric conducting material in TSV from impacting the charge carrier change in semiconductor.Barrier layer 4 is usually deposited successively by multiple layer metal and forms, the arrangement of its structural rate titanium in this way/titanium tungsten/copper or the arrangement of titanium/nickel/gold etc.The effect on this barrier layer 4 can prevent when making TSV conductive pole 31, and electric conducting material infiltrates in Semiconductor substrate 11 through dielectric layer 2, thus causes damage to Semiconductor substrate and the electronic devices and components be arranged in this Semiconductor substrate.TSV conductive pole 31 is produced in this hole by the method that metal deposits.TSV conductive pole 31 preferably uses metal material, such as Al, Cu, Ag etc., also can use other electric conducting material, such as doped polycrystalline silicon or its composition etc., and in the present invention, this conductive pole 31 is preferably based on copper product.The top 32 of TSV conductive pole 31 preferably be arranged at the electronic devices and components in Semiconductor substrate 11 front or conductive layer, conductive pattern district is connected, 33, the bottom of TSV conductive pole 31 is deeply in Semiconductor substrate 11, its degree of depth generally reaches 50 μm about-100 μm, and diameter is generally at 5 μm about-50 μm.After wafer current making technology, the thickness of wafer can reach 700 μm-725 μm, therefore in order to the bottom 32 of TSV conductive pole 31 can be made to be exposed to substrate back, needs to implement a reduction process to the back side 13 of this substrate.
Refer to Fig. 3 C, first carry out thinning with the back side 13 of the means of mechanical lapping to this Semiconductor substrate 11.Because the thickness of substrate 11 is thicker, need thinning thickness usually more than 500 μm, this process need carries out with the means that thinning efficiency is higher.Therefore preferred in the mode of mechanical lapping, substrate is directly ground with grinding pad (such as emery wheel form).Because the means of mechanical lapping are more coarse comparatively speaking, the crystal column surface TTV therefore passed through after this grinding is higher, as shown in the figure, the thickness difference d1 on its surface may reach 2 μm-3 μm even more than.
Refer to Fig. 3 D, after mechanical lapping, in order to make the TTV of substrate surface within acceptable scope, first time CMP (Chemical Mechanical Polishing) process is implemented to this substrate back, this CMP (Chemical Mechanical Polishing) process adopts the polishing fluid without Selection radio to carry out, and object is controlled by the TTV of substrate surface, below 1 μm, to obtain more smooth substrate surface, simultaneously that the thickness of substrate is thinning further, make the distance d2 bottom substrate back distance TSV be less than 1 μm.This polishing fluid is depending on the material of substrate, and such as when substrate is silicon, this lapping liquid can adopt common silicon lapping liquid, and its composition comprises the compositions such as abrasive material, p H value conditioning agent, bleeding agent, lubricant, surfactant, chelating agent, deionized water.
Refer to Fig. 3 E, after first time chemico-mechanical polishing, the bottom 33 of the back side of Semiconductor substrate 11 closely TSV, now implements second time CMP (Chemical Mechanical Polishing) process to this Semiconductor substrate.This second time CMP (Chemical Mechanical Polishing) process adopts carries out Semiconductor substrate 11, TSV dielectric layer 2, polishing fluid that TSV barrier layer 4 selection and comparison is large, Selection radio wherein between Semiconductor substrate 11 and dielectric layer 2 is at 10:1 to 100:1, and the Selection radio between dielectric layer 2 and barrier layer 4 is then preferably over 200:1.So, in this second time CMP (Chemical Mechanical Polishing) process, polishing fluid is maximum for the etch rate of substrate, and it is minimum for the etch rate on barrier layer, substantially can regard as and cannot etch barrier layer, namely the etch-stop of this second time chemico-mechanical polishing in TSV part can be stayed on barrier layer 4, and cannot the conduction copper column part being positioned at inside, barrier layer 4 be etched.During second time chemico-mechanical polishing, polishing fluid, when carrying out downward erosion to substrate, due to different with the pressure of horizontal direction to substrate in the vertical direction, causes polishing fluid slightly to have difference with horizontal direction etch rate in the vertical direction.In addition, add that the etch rate of polishing fluid on TSV dielectric layer and barrier layer is far smaller than the etch rate to substrate, cause the region close to TSV, it is also affected to the etch rate of substrate.Therefore after whole second time CMP (Chemical Mechanical Polishing) process terminates, its to substrate etching formed surface topography as indicated in figure 3e, the region joined with TSV, substrate height is the highest, and reduce gradually along the direction height away from TSV, form the transitional region of a domatic.In ensuing wet etching or dry etching, because etching has isotropism, therefore only in the depth direction substrate is etched, and the transitional region of this domatic, then retained.Thus, when follow-up deposited seed layer, the effect of a buffering can be played, makes Seed Layer can form a continuous print depositional plane at this, thus improve the electrical connection effect of this TSV to outside.
This second time chemico-mechanical polishing is to the polishing degree of depth of substrate, namely the height d3 that TSV exposes preferably controls between 0.2 μm-0.5 μm, depending on the spacing between TSV, if interval is less between TSV, then the corresponding polishing degree of depth is then also selected more shallow, otherwise, if the interval between TSV is comparatively large, then can carry out darker polishing to substrate in this step.
In actual applications, the polishing fluid that this second time chemico-mechanical polishing adopts can be hydrofluoric acid and nitric acid mixed system, hydrofluoric acid, TMAH system or potassium hydroxide.In these polishing fluids, realize the regulation and control of the Selection radio to substrate and dielectric layer by controlling the percent by volume of each composition or the percentage by weight of self.Such as, the scope of the percent by volume of hydrofluoric acid and nitric acid can regulate and control between 1:5 to 1:25, and the percentage by weight of TMAH etching solution is 3w%-30w%.
After completing second time chemico-mechanical polishing, wet method or dry etch process are carried out to substrate, by substrate etching to certain depth, thus till exposing required high TSV conductive pole.This TSV appears and is highly generally more than 10 μm.
To sum up above-mentioned, TSV of the present invention appears in technique, by after adopting mechanical system grinding thinning to the back side of wafer substrate, increases by 2 CMP (Chemical Mechanical Polishing) process (CMP), thus creates following technique effect:
First time, CMP adopted the polishing fluid without Selection radio, made the TTV of substrate surface control, below 1 μm, to reduce the problem of the lack of homogeneity caused appearing because TTV is excessive.
Second time CMP adopts the polishing fluid to high selectivity between substrate, TSV dielectric layer, TSV barrier layer three; etch-stop is made to stay on the barrier layer of TSV; thus the conduction copper column of protection the inside is not corroded; and etching substrate pattern out has for transition structure during seed layer deposition, thus stability when improving the follow-up electrical connection of TSV.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (6)
1. TSV appears a technique, it is characterized in that, comprises step:
The Semiconductor substrate that one has a TSV structure is provided;
One mechanical milling tech is carried out to the back side of above-mentioned Semiconductor substrate;
First time CMP (Chemical Mechanical Polishing) process is carried out to the Semiconductor substrate back side, this first time CMP (Chemical Mechanical Polishing) process employing is no more than 1 μm of place without the polishing fluid of Selection radio by bottom Semiconductor substrate polished backside to distance TSV, and the TTV on polishing back substrate surface is less than 1 μm;
Second time CMP (Chemical Mechanical Polishing) process is carried out to the Semiconductor substrate back side, this second time CMP (Chemical Mechanical Polishing) process adopts Semiconductor substrate, TSV dielectric layer, the polishing fluid of TSV barrier layer high selectivity carries out, the etch rate of polishing fluid to described substrate of described high selectivity is maximum, minimum to the etch rate on described barrier layer, after described second time CMP (Chemical Mechanical Polishing) process terminates, it forms following surface topography to substrate etching: the region joined with described TSV structure, substrate height is the highest, and reduce gradually along the direction height away from TSV structure, form the transitional region of a domatic,
Wet method or dry etching are carried out to the Semiconductor substrate back side, makes TSV expose more than 10 μm.
2. TSV as claimed in claim 1 appears technique, it is characterized in that: the polishing fluid adopted in described second time CMP (Chemical Mechanical Polishing) process, it is that Selection radio between 10:1 to 100:1, TSV dielectric layer and TSV barrier layer is more than 200:1 to the Selection radio between Semiconductor substrate and TSV dielectric layer.
3. TSV as claimed in claim 1 appears technique, it is characterized in that: the polishing fluid hydrofluoric acid adopted in described second time CMP (Chemical Mechanical Polishing) process and nitric acid mixed system, hydrofluoric acid, TMAH system or potassium hydroxide.
4. TSV as claimed in claim 3 appears technique, it is characterized in that: in described hydrofluoric acid and nitric acid mixed system, the scope of the percent by volume of hydrofluoric acid and nitric acid is between 1:5 to 1:25, and the percentage by weight of described TMAH system is 3w%-30w%.
5. TSV as claimed in claim 1 appears technique, and it is characterized in that: after described second time CMP (Chemical Mechanical Polishing) process, TSV appears height between 0.2 μm-0.5 μm.
6. TSV as claimed in claim 1 appears technique, it is characterized in that: the material of described Semiconductor substrate is silicon, germanium, gallium nitride or GaAs.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310163510.6A CN103219282B (en) | 2013-05-03 | 2013-05-03 | Through silicon via (TSV) exposure process |
| US14/071,459 US9076699B2 (en) | 2013-05-03 | 2013-11-04 | TSV backside reveal structure and exposing process |
| US14/071,453 US20140327132A1 (en) | 2013-05-03 | 2013-11-04 | TSV Backside Reveal Structure and Exposing Process |
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| CN201310163510.6A CN103219282B (en) | 2013-05-03 | 2013-05-03 | Through silicon via (TSV) exposure process |
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| CN104810270A (en) * | 2014-01-28 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Grinding method |
| CN105590868B (en) * | 2014-10-20 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN104952720A (en) * | 2015-07-14 | 2015-09-30 | 华进半导体封装先导技术研发中心有限公司 | Method for forming height-controllable exposure of electric-conducting poles from back |
| CN107924831B (en) * | 2015-09-24 | 2023-10-10 | 英特尔公司 | Techniques for exposing a backside of an integrated circuit device and related configurations |
| CN107680906B (en) * | 2017-10-17 | 2020-02-18 | 北京半导体专用设备研究所（中国电子科技集团公司第四十五研究所） | Substrate outcrop polishing method and application thereof |
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| US8455984B2 (en) * | 2010-11-15 | 2013-06-04 | Nanya Technology Corp. | Integrated circuit structure and method of forming the same |
| CN102208362B (en) * | 2011-05-04 | 2013-11-06 | 中国科学院微电子研究所 | Preparation method of Through-Silicon-Via back coupling end |
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