TWI621234B - Method of forming interconnect structure - Google Patents

Abstract

The present invention discloses a method of forming an interconnect structure, comprising: providing a germanium having a dielectric layer; forming a first recessed region on the dielectric layer, the first recessed region for forming an interconnect structure; forming on the dielectric layer a second recessed region, wherein the second recessed region is used to form a dummy structure; a barrier layer is deposited on the dielectric layer, the barrier layer covering the first recessed region, the second recessed region of the dielectric layer, and the non-recessed region of the dielectric layer Depositing a metal layer on the barrier layer, the metal layer filling the first recessed region and the second recessed region and covering the non-recessed region; removing the metal layer on the non-recessed region; The barrier is removed. The present invention forms a virtual structure on the dielectric layer of the cymbal. When the metal layer on the non-groove area is over-polished, the current will be more transmitted from the dummy structure, and the barrier layer is prevented from being oxidized, thereby enabling uniform, The barrier layer on the non-recessed area is completely removed.

Description

Method of forming interconnect structure

The present invention relates to the field of semiconductor process technology, and more particularly to a method of forming an interconnect structure.

Semiconductor devices are typically fabricated from a semiconductor material, such as a ruthenium, through a series of processes. The ruthenium may be subjected to processes such as masking, etching, deposition, etc. to form a circuit of the semiconductor device. As the integration of semiconductor devices continues to increase, metal interconnect structures are rapidly evolving and used in semiconductor devices. Multiple masking and etching processes enable the formation of recessed regions in the dielectric layer on the wafer. Then, a deposition process is performed to deposit a metal layer in the recessed region and the non-groove region of the dielectric layer. The metal layer deposited on the non-groove area of the dielectric layer needs to be removed to isolate the pattern of the recessed regions and form an interconnect structure. In order to prevent the metal layer from diffusing or intruding into the dielectric layer, a barrier layer is usually deposited on the dielectric layer before depositing the metal layer on the dielectric layer, and then the metal layer is deposited on the barrier layer.

Conventional methods of removing metal and barrier layers on non-recessed regions of a dielectric layer include, for example, chemical mechanical polishing (CMP). CMP methods are widely used in the semiconductor industry to polish and planarize metal layers on non-recessed regions of dielectric layers to form interconnect structures. In the CMP process, the cymbals are placed Located on the polishing pad on the polishing pad, pressure is applied to the die to press the die against the polishing pad, and the die and polishing pad move relative to each other while pressure is applied to polish and planarize the surface of the blade. During the polishing process, the polishing liquid is dispensed onto the polishing pad to facilitate polishing. Although the CMP method can achieve global planarization of the surface of the ruthenium, the CMP method has a detrimental effect on the semiconductor structure due to the strong mechanical force of the CMP, especially when the feature size of the semiconductor structure becomes smaller and smaller, copper and When a low-k/ultra-k dielectric layer is used in a semiconductor structure, strong mechanical forces may cause stress-related defects in the semiconductor structure.

Another method of removing the metal layer on the non-recessed regions of the dielectric layer is an electrochemical polishing process. The electrochemical polishing process removes the metal layer with high uniformity and high selectivity to the barrier layer. The electrochemical polishing process is a stress-free polishing process. However, in the electrochemical polishing process, in order to ensure that all of the metal layers on the non-recessed regions of the dielectric layer are removed, there is usually an over-polishing process. After over-polishing, some areas are found, such as a field area, a relatively wide area between two adjacent metal lines, or both sides of an isolated metal line. In the over-polishing stage, these areas are not recessed. The metal layers are all removed such that the barrier layer is exposed and current is conducted through the barrier layer, resulting in the upper surface of the barrier layer being oxidized to form an oxide film in these regions. In other words, the thickness of the oxide film formed on the surface of the barrier layer in the region where the metal interconnect density is low may be thicker than the thickness of the oxide film formed on the surface of the barrier layer in the region where the metal interconnect density is higher. This is because metal interconnects, such as copper, have a much lower resistance than the barrier, in areas with high copper density. The current is conducted more from the copper wire. The oxide film formed on the surface of the barrier layer hinders the removal of the barrier layer, and if the barrier layer cannot be uniformly removed, it causes failure of the semiconductor device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming an interconnect structure capable of not oxidizing a barrier layer when over-polishing a metal layer on a non-recessed region of the dielectric layer, thereby subsequently removing the non-recessed region of the dielectric layer The barrier layer on the non-recessed area can be removed uniformly and completely.

In order to achieve the above object, a method for forming an interconnect structure according to the present invention includes: providing a germanium having a dielectric layer; forming a first recessed region on the dielectric layer, wherein the first recessed region is used to form an interconnect structure; Forming a second recessed region on the dielectric layer, the second recessed region is for forming a dummy structure; depositing a barrier layer on the dielectric layer, the barrier layer covering the first recessed region, the second recessed region and the dielectric layer of the dielectric layer a non-recessed region; a metal layer is deposited on the barrier layer, the metal layer fills the first recessed region and the second recessed region and covers the non-recessed region; and the metal layer on the non-recessed region is removed; The barrier layer on the recessed area is removed.

In summary, the present invention forms a virtual structure on the dielectric layer of the cymbal. When the metal layer on the non-groove area is overpolished, the current will be more transmitted from the dummy structure to prevent the barrier layer from being oxidized. Thereby, the barrier layer on the non-groove area can be uniformly and completely removed.

200‧‧‧Virtual structure

201‧‧‧ Picture

202‧‧‧ dielectric layer

203‧‧‧Block

204‧‧‧metal layer

205‧‧‧Oxide film

300‧‧‧Virtual structure

400‧‧‧Virtual Structure

Figure 1 discloses a flow chart of a damascene process of an embodiment.

Figure 2 is a schematic cross-sectional view showing the damascene process of an embodiment.

Figure 3 discloses a flow chart of another embodiment of the damascene process.

Figure 4 discloses a top view of the formation of a virtual structure on the field of the cymbal, wherein the barrier layer on the non-recessed area is not removed.

Figure 4 (a) is a cross-sectional view taken along line A-A of Figure 4;

Figure 4 (b) is a cross-sectional view of Figure 4 taken along line B-B.

Figure 5 discloses a top view of the formation of a virtual structure on the field of the cymbal, wherein the barrier layer on the non-recessed area has been removed.

Figure 5 (a) is a cross-sectional view taken along line A-A of Figure 5.

Figure 5 (b) is a cross-sectional view of Figure 5 taken along line B-B.

Figure 6 discloses a top view of a relatively wide area between two adjacent metal lines on a hapten to form a virtual structure in which the barrier layer on the non-recessed area has been removed.

Figure 7 discloses a top view of the virtual structure formed on both sides of the isolated metal line on the cymbal, wherein the barrier layer on the non-recessed area has been removed.

Figures 8(a) through 8(i) illustrate various shapes of the virtual structure.

Figure 9 (a) shows a top view of a scanning electron microscope (SEM) of a ruthenium without a dummy structure after removal of the barrier layer.

Figure 9(b) shows a top view of a scanning electron microscope (SEM) of a ruthenium formed with a virtual structure after removal of the barrier layer.

The details of the technical contents, the objects and effects achieved by the present invention will be described in detail below with reference to the embodiments.

Referring to Figures 1 and 2, a damascene process for forming an embodiment of an interconnect structure in a semiconductor device is disclosed. Figure 1 discloses a flow chart of a damascene process of an embodiment. Figure 2 is a schematic cross-sectional view showing the damascene process of an embodiment. 1 and 2, in step 110, a die 201 or other similar substrate is provided. The die 201 has an inter-metal dielectric layer (IMD) 202, hereinafter referred to as a dielectric layer. The material of the dielectric layer 202 may be cerium oxide or a material similar to cerium oxide, or other dielectric material having a lower dielectric constant than cerium oxide to reduce parasitic capacitance between interconnect structures. In step 120, a recessed region is formed on the dielectric layer 202. In step 130, a barrier layer 203 is deposited over the dielectric layer 202. The barrier layer 203 may be deposited on the dielectric layer 202 using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The barrier layer 203 covers the recessed and non-recessed regions of the dielectric layer 202. Considering that the dielectric layer 202 may also have a hole-like structure, the barrier layer 203 may be composed of a material capable of preventing the metal layer 204 deposited in a subsequent process from diffusing into the dielectric layer 202, the barrier layer 203 to the dielectric layer 202 and the metal layer 204. Has good adhesion. Generally, the barrier layer 203 may be composed of, for example, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, tungsten nitride, tantalum nitride (TaSiN), and tantalum nitride (WSiN).

In step 140, a metal layer 204 is deposited over the barrier layer 203. Can be used, for example, chemical vapor deposition (CVD), physical vapor deposition A metal layer 204 is deposited on the barrier layer 203 by methods such as PVD, atomic layer deposition (ALD), or electroplating. Preferably, the seed layer may be deposited on the barrier layer 203 prior to depositing the metal layer 204. The material of the seed layer is identical to the metal layer 204 for the purpose of facilitating deposition and adhesion of the metal layer 204 to the barrier layer 203. The metal layer 204 fills the recessed area and covers the non-recessed area. The metal layer 204 may be composed of various conductive materials such as copper, aluminum, nickel, zinc, silver, gold, tin, chromium, superconducting materials, and the like. Preferably, the material of the metal layer 204 is copper.

In step 150, the metal layer 204 on the non-recessed region of the dielectric layer 202 is removed. The metal layer 204 on the non-recessed regions of the dielectric layer 202 can be removed by electropolishing. For a detailed description of electropolishing, reference is made to U.S. Patent Application Serial No. 09/497,894, the disclosure of which is incorporated herein by reference.

In step 160, the barrier layer 203 on the non-recessed region of the dielectric layer 202 is removed. The barrier layer 203 on the non-recessed region of the dielectric layer 202 can be removed by, for example, wet etching, dry chemical etching, dry plasma etching, or the like. Preferably, the barrier layer 203 on the non-recessed region of the dielectric layer 202 is removed using a XeF ₂ vapor phase etch. As shown in FIG. 2, in order to remove all of the metal layer 204 on the non-groove area of the dielectric layer 202, over-polishing is performed when the metal layer 204 on the non-groove area of the dielectric layer 202 is removed. After over-polishing, the metal layer 204 on the non-recessed regions of the dielectric layer 202 is completely removed, and the barrier layer 203 on the non-groove regions of the dielectric layer 202 is exposed. Current is conducted through the barrier layer 203, resulting in regions located on the non-recessed regions of the dielectric layer 202, such as a field area, a relatively wide area between adjacent two metal lines, or both sides of an isolated metal line. The barrier layer 203 is oxidized to form an oxide film 205 on the surface of the barrier layer 203. In order to remove the barrier layer 203 on the non-groove area of the dielectric layer 202, the oxide film 205 on the surface of the barrier layer 203 needs to be removed first. Further, the thickness of the oxide film 205 is related to the density of the interconnect structure. That is, the thickness of the oxide film formed on the surface of the barrier layer in the region where the metal interconnect density is low is thicker than the thickness of the oxide film formed on the surface of the barrier layer in the region where the metal interconnect density is higher. This is because the metal layer 204, such as a copper layer, has a much lower electrical resistance than the barrier layer 203, and conducts more current from the copper wire in areas where the copper wire density is higher. The oxide film 205 formed on the surface of the barrier layer 203 hinders the removal of the barrier layer 203, and if the barrier layer 203 cannot be uniformly removed, it causes failure of the semiconductor device.

In order to solve the above technical problems, a damascene process of another embodiment is disclosed with reference to FIGS. 3 to 5(b). Compared with the damascene process disclosed in the foregoing embodiments, the damascene process of the present embodiment forms the dummy structure 200 in the field area of the dielectric layer to avoid oxidation on the surface of the barrier layer 203 when the over-polished metal layer 204 is applied. Film 205. As shown in FIG. 3, the damascene process of this embodiment includes the following steps.

In step 210, a ruthenium 201 or other similar substrate having a metal interlayer dielectric layer (IMD) 202, hereinafter referred to as a dielectric layer, is provided. The material of the dielectric layer 202 may be cerium oxide or a material similar to cerium oxide, or other dielectric material having a lower dielectric constant than cerium oxide. To reduce the parasitic capacitance between the interconnect structures.

In step 220, a first recessed region is formed on dielectric layer 202, the first recessed region being used to form an interconnect structure.

In step 230, a second recessed region is formed on the dielectric layer 202, and the second recessed region is used to form the dummy structure 200. In one embodiment, the virtual structure 200 is formed in a field region of the dielectric layer 202. In one embodiment, the interconnect structure and dummy structure 200 can be formed simultaneously on the dielectric layer 202. The depth and width of the virtual structure 200 are consistent with the depth and width of the interconnect structure. It will be understood by those skilled in the art that the dummy structure 200 may also be separately formed on the dielectric layer 202, and the depth and width of the dummy structure 200 may also be different from the depth and width of the interconnect structure. The material of the dummy structure 200 may be the same as or different from the material of the interconnect structure.

In step 240, a barrier layer 203 is deposited over the dielectric layer 202, the barrier layer 203 covering the first recessed regions of the dielectric layer 202, the second recessed regions, and the non-recessed regions of the dielectric layer 202.

In step 250, a metal layer 204 is deposited over the barrier layer 203, and the metal layer 204 fills the first recessed region and the second recessed region and overlies the non-recessed region. Preferably, the seed layer may be deposited on the barrier layer 203 prior to depositing the metal layer 204. The material of the seed layer is identical to the metal layer 204 for the purpose of facilitating deposition and adhesion of the metal layer 204 to the barrier layer 203.

In step 260, the metal layer 204 on the non-recessed region of the dielectric layer 202 is removed. Preferably, the removal process of the metal layer 204 on the non-groove area comprises two steps. The first step uses chemical mechanical polishing to remove part of the metal layer 204 to obtain better surface flatness, and the second step uses electricity. The chemical polishing method removes the remaining metal layer 204 on the non-recessed regions to prevent damage to the device.

In step 270, the barrier layer 203 on the non-recessed region of the dielectric layer 202 is removed. Preferably, the barrier layer 203 on the non-recessed region of the dielectric layer 202 is removed using a XeF ₂ vapor phase etch. The metal layer 204 remaining in the first recess region forms an interconnect structure. The metal layer 204 remaining in the second recess region forms the dummy structure 200. As shown in FIGS. 5 to 5(b), since the dummy structure 200 is formed in the field region on the cymbal, even if the metal layer 204 is excessively polished, since the resistance of the dummy structure 200 is much smaller than that of the barrier layer 203, the current More is conducted from the dummy structure 200, and therefore, the barrier layer 203 is not oxidized, so that the barrier layer 203 on the non-groove area can be uniformly removed.

As shown in FIGS. 3 to 5(b), the density of the dummy structure 200 formed in the dielectric layer field region is 50% to 100% of the density of the interconnect structure on the cymbal. The pitch W1 between the two adjacent interconnect structures and the dummy structure 200 is 20 nm to 5000 nm. The size of the dummy structure 200 is 20 nm to 5000 nm. Specifically, the width Dw of the dummy structure 200 is 20 nm to 5000 nm, and the length D1 of the dummy structure 200 is 20 nm to 5000 nm.

In one embodiment, if the spacing between adjacent two metal lines, that is, between adjacent two interconnect structures is too wide, the surface of the barrier layer 203 is also easily oxidized to form an oxide film when the over-polished metal layer 204 is implemented. 205. Therefore, the dummy structure 300 can also be formed on a wider area between adjacent metal lines on the dielectric layer of the cymbal to avoid the formation of the oxide film 205 on the surface of the barrier layer 203 when the metal layer 204 is excessively polished, as shown in FIG. 6. Shown. The pitch W3 between adjacent two metal lines is 60 nm or more. Virtual knot The size of the structure 300 can be the same as the size of the virtual structure 200.

In one embodiment, if the two sides of the isolated metal wire on the die are wider, the surface of the barrier layer 203 is also easily oxidized to form the oxide film 205 when the over-polished metal layer 204 is applied. Therefore, the dummy structure 400 can also be formed on both sides of the isolated metal line on the dielectric layer of the cymbal to avoid the formation of the oxide film 205 on the surface of the barrier layer 203 when the over-polishing metal layer 204 is applied, as shown in FIG. The density of the dummy structure 400 is between 20% and 80% of the density of the interconnect structure on the cymbal. The size of the virtual structure 400 can be the same as the size of the virtual structure 200.

Referring to Figures 8(a) through 8(i), various shapes of the virtual structure are listed. The shape of the virtual structures 200, 300, 400 may be square, rectangular, circular, elliptical, cruciform, triangular, circular, or the like. Although a series of shapes are listed above, it will be understood by those skilled in the art that the shape of the virtual structure is not limited to the above shape, and the selection of the shape of the virtual structure depends on the actual needs of the process.

Referring to FIG. 9(a) and FIG. 9(b), the SEM top view after removing the barrier layer and the SEM top view after removing the barrier layer are performed on the ruthenium without the dummy structure after removing the barrier layer. In contrast, it can be seen that the ruthenium of the dummy structure is not disposed, and the barrier layer near the interconnect structure can be completely removed, but the barrier layer in the smear field is not completely removed, and a part of the residual barrier layer exists. In the cymbal field, a virtual structure of the cymbal is formed, and all the barrier layers on the cymbal can be completely removed.

As can be seen from the above, the present invention transmits a relatively wide area between the field regions of the cymbal, the adjacent two metal wires, or both sides of the isolated metal wire. The domains form a virtual structure, and when the over-polished metal layer is implemented, current is more transmitted from the dummy structure, and the barrier layer is prevented from being oxidized, so that the barrier layer on the non-groove region can be uniformly and completely removed. The virtual structure of the present invention is not limited to the field region formed on the cymbal, the relatively wide region between adjacent two metal lines, or the two sides of the isolated metal line, as long as the area of the ruthenium having a lower pattern density can be formed. Virtual structure.

In view of the above, the present invention has been specifically and specifically disclosed by the above-described embodiments and related drawings, and can be implemented by those skilled in the art. The above-mentioned embodiments are only intended to illustrate the invention, and are not intended to limit the invention. The scope of the invention should be defined by the scope of the invention.

Claims (14)

A method of forming an interconnect structure, comprising: providing a germanium having a dielectric layer; forming a first recessed region on the dielectric layer, the first recessed region for forming an interconnect structure; forming on the dielectric layer a second recessed region, wherein the second recessed region is used to form a dummy structure; a barrier layer is deposited on the dielectric layer, the barrier layer covering the first recessed region, the second recessed region of the dielectric layer, and the non-recessed region of the dielectric layer Depositing a metal layer on the barrier layer, the metal layer filling the first recessed region and the second recessed region and covering the non-recessed region; removing the metal layer on the non-recessed region; The barrier is removed. A method of forming an interconnect structure according to claim 1, wherein the dummy structure is formed in a field region of the dielectric layer. A method of forming an interconnect structure according to claim 2, wherein the density of the dummy structure is 50% to 100% of the density of the interconnect structure on the cymbal. The method for forming an interconnect structure according to claim 2, wherein a pitch W1 between the adjacent interconnected structure and the dummy structure on the germanium is 20 nm to 5000 nm. The method for forming an interconnect structure according to claim 1, wherein the size of the dummy structure is 20 nm to 5000 nm, wherein a width Dw of the dummy structure is 20 nm to 5000 nm, and a length D1 of the dummy structure is 20 nm to 5000 nm. . A method of forming an interconnect structure according to claim 1, wherein the dummy structure is formed in a wider area between adjacent two interconnect structures on the dielectric layer. A method of forming an interconnect structure according to claim 6, wherein a pitch W3 between the adjacent two interconnect structures is greater than or equal to 60 nm. A method of forming an interconnect structure according to claim 1, wherein the dummy structure is formed on both sides of an isolated interconnect structure on the dielectric layer. A method of forming an interconnect structure according to claim 8, wherein the density of the dummy structure is 20% to 80% of the density of the interconnect structure on the cymbal. A method of forming an interconnect structure according to claim 1, wherein the virtual structure has one or more different shapes. A method of forming an interconnect structure according to claim 1, wherein the interconnect structure and the dummy structure are simultaneously formed on the dielectric layer. A method of forming an interconnect structure according to claim 1, wherein the material of the dummy structure is the same as the material of the interconnect structure. The method of forming an interconnect structure according to claim 1, wherein the step of removing the metal layer on the non-groove area further comprises removing a portion of the metal layer by chemical mechanical polishing, and then employing The electrochemical polishing method removes the remaining metal layer. The method of forming an interconnect structure according to claim 1, wherein the step of removing the barrier layer on the non-groove region further comprises removing the non-groove of the dielectric layer by using a method of XeF ₂ vapor phase etching. The barrier on the area.